先進金氧半場效電晶體考慮溫度相依之高頻小訊號及雜訊特性分析

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電子工程學系 電子研究所

博 士 論 文

先進金氧半場效電晶體考慮溫度相依之高頻

小訊號及雜訊特性分析

High-Frequency Small-Signal and Noise Characterization for

Advanced MOSFETs Considering Temperature Dependence

研 究 生:王生圳

指導教授:蘇彬 博士

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先進金氧半場效電晶體考慮溫度相依之高頻小訊號

及雜訊特性分析

High-Frequency Small-Signal and Noise Characterization for

Advanced MOSFETs Considering Temperature Dependence

研 究 生:王生圳 Student:Sheng-Chun Wang

指導教授:蘇彬 博士 Advisor:Dr. Pin Su

國 立 交 通 大 學

電子工程學系 電子研究所

博 士 論 文

A Dissertation

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

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i

先進金氧半場效電晶體考慮溫度相依之高頻小訊號

及雜訊特性分析

研究生:王生圳

指導教授:蘇彬 博士

國立交通大學 電子工程學系 電子研究所

摘要

本篇論文對於現今各種的平面金氧半場效電晶體(MOSFET)作了完整的高頻小訊號 及雜訊特性分析和模型化工作,這些元件包括傳統MOSFET(bulk MOSFET)、絕緣層上

矽MOSFET(SOI MOSFET)、絕緣層上矽動態起始電壓 MOSFET(SOI DT MOSFET)和應

變MOSFET(strained MOSFET)等。建立於傳統 MOSFET 架構下的等效射頻小訊號電路

模型將被適當地修改以考量存在於各別元件的寄生效應,並藉由在適當的位置擺入各雜 訊源,我們便可以建立各元件對應的高頻雜訊模型。此外,本篇論文也首次探討到各元 件在溫度變化下的高頻行為表現。

部分空乏SOI MOSFET 中性體區(neutral-body)的寄生效應,會影響到元件的輸出特

性,其影響甚至可到數個 GHz 的操作頻率。由於通道電導高溫時減小,造成了 bulk

MOSFET 和 SOI MOSFET 的通道雜訊都呈現具負溫度係數的特性。此外,SOI 元件中

的自發熱效性(self-heating effect)和浮體效應(floating-body effect)會使得其雜訊因子

(noise factor)高於傳統 MOSFET。不利於高頻雜訊的浮體效應(在低閘電壓下較明顯)可藉 由升溫加以抑制,而自發熱效應則因為高閘極電壓伴隨的低電導而可扺掉一部分效應。

SOI DT MOSFET 的基底寄生元件和串聯電阻對最大震盪頻率( fmax)的影響比對截

止頻率( f )來的大。此外,在一般操作所使用的低閘極和低汲極偏壓(t VDD)下,由於轉

導(g )會隨溫度上升而上升,造成m f 和t fmax都和溫度成正相依關係。實驗結果顯示當

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雜訊來得大,我們發現其等效熱雜訊電阻R 將具有負的溫度係數。進一步的研究發現,n 基底的連接電阻R 所產成的雜訊會不利於最低雜訊指數b NFmin,且低VDD偏壓下的較大 b R 對於NFmin的溫度相依情形反而影響不大。 舒張形變n 型 MOSFET(tensile-strained nMOSFET)因為擁有較大載子移動率及和傳 統 MOSFET 相近的飽和電壓,所以以相同的偏壓條件來說,會有較大的通道雜訊。然 而,實驗結果顯示對於相同的功率消耗條件來說,其較大的轉導會使得 tensile-strained

nMOSFET 在 f 、t fmaxNFminR 的表現上都會比傳統 MOSFET 來的優異。 n

最後,本論文探討65 奈米 MOSFET 應用於毫米波時的雜訊表現。實驗結果顯示,

持續上升的通道雜訊對整體毫米波雜訊模型化工作和特性分析的影響愈來愈重要。除此 之外,以寄生效應來看,閘極電阻對毫米波的雜訊影響程度比基板電阻來的大。

關鍵字:動態起始電壓金氧半場效電晶體, 毫米波, 雜訊因子, 雜訊參數, 射頻, 絕緣層 上矽金氧半場效電晶體, 小訊號, 溫度相依, 應變

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iii

High-Frequency Small-Signal and Noise Characterization for

Advanced MOSFETs Considering Temperature Dependence

Student: Sheng-Chun Wang

Advisor: Dr. Pin Su

Department of Electronics Engineering and Institute of Electronics

National Chiao Tung University

Abstract

This dissertation provides a comprehensive high-frequency small-signal and noise characterization and modeling for various kinds of modern planar MOSFET devices, including the bulk MOSFET, silicon-on-insulator (SOI) MOSFET, partially-depleted SOI dynamic threshold voltage (DT) MOSFET, and strained MOSFET. The traditional RF small-signal equivalent circuit for the bulk MOFET will be modified to include existing parasitic components present in each kind of MOSFETs. Based on each tailored small-signal model, the corresponding high-frequency noise model can be built by adding the noise sources in place. For the first time, the temperature dependence of the high-frequency performance will also be discussed.

The SOI MOSFET has the inherent neutral-body effect, which will be found to influence the output characteristic even in GHz applications. The channel noise S has been shown to id

have a negative temperature coefficient for both the bulk and SOI MOSFETs due to the lowered channel conductance at high temperature. Besides, the self-heating effect (SHE) and the floating-body effect (FBE) of the SOI MOSFET would make its noise factor higher than

the bulk MOSFET. It shows that the FBE, which dominates at low V regime, can be GS

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be partly counterbalanced by the lowered channel conductance at high temperature.

The body-related parasitics and the series resistance of the SOI DT MOSFET are found to have more impact on fmax (maximum oscillation frequency) than f (cut-off frequency). t

Besides, in the normal bias condition - low gate and drain voltage (low VDD) regime, both

t

f and fmax have positive temperature coefficients due to the increased g m

(trans-conductance) at high temperature. We also show that the DT MOSFET would get a negative temperature coefficient for equivalent noise resistance R towards the weaker n

inversion region due to the much higher 2

m

g than S with increasing temperature. id

Furthermore, our research results show the noise arising from the body resistance R can b

degrade the minimum noise figure NFmin, and the larger R encountered in the low b VDD

regime would have less impact on the temperature dependence of NFmin.

The tensile-strained nMOSFET presents larger S than the control device due to its id

enhanced mobility and nearly the same saturation voltage for a given bias point, and has the same temperature dependence of S as the control device. However, our measured data id

indicates that the enhanced carrier trans-conductance in the tensile nMOSFET would contribute to better f , t fmax, NFmin and R than the control device for a given DC power n

consumption.

Finally, for the emerging millimeter-wave applications, we examine the millimeter wave noise behavior of 65nm MOSFETs. The experimental results show that the continually increasing S makes it play a more and more important role in the millimeter-wave noise id

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v

誌謝

本篇論文能夠完成,該感謝的人很多。首先,我要感謝指導教授蘇彬

博士,這些年來在論文研究上的專業指導,使得這篇論文與相關研究能順

利完成。

感謝國家奈米元件實驗室的黃國威、陳坤明、吳師道、邱佳松、蕭宇

劭和陳文林等諸位博士,在高頻分析上的指導。此外,亦感謝學長鄧裕民、

學弟陳柏源、蕭治華、林書毓、劉汶德和廖榮彦等人在儀器操作與使用上

的幫忙與協助。

感謝聯電提供製程上的協助。另外,感謝交大蘇彬教授實驗室的學長

和學弟妹李維、陳柏年、陳燦堂、郭俊延、吳育昇、胡璧合、范銘隆與呂

昆諺在實驗上的幫忙和協助。

最後,感謝我的老婆佩菁對我的體諒與包容,讓我可以全力以赴地完

成我的學業。

2011.3

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Contents

Abstract (Chinese) ...i

Abstract (English) ...iii

Acknowledgement (Chinese) ...v

Contents ...vi

Table Captions ...viii

Figure Captions ...ix

Chapter 1 Introduction ...1

Chapter 2 RF Small-Signal Modeling and Characterization for SOI MOSFETs 2-1 Introduction ...8

2-2 Devices and Experiments ...9

2.3 Neutral-Body Effect on the Resistance Extraction ...9

2.4 Neutral-Body Effect on the Intrinsic Modeling ...12

2.5 Neutral-Body Effect on the Output Characteristics ...15

2.6 Summary ...16

Chapter 3 RF Noise Characterization for Bulk and SOI MOSFETs 3.1 Introduction ...37

3.2 Devices and Experiments ...37

3.3 RF Noise Characterization for Bulk MOSFETs ...38

3.3.1 RF Noise Characteristics for Medium-Long Devices ...38

3.3.2 RF Noise Characteristics for Deep-Submicron Devices ...40

3.4 RF Noise Characterization for SOI MOSFETs ...41

3.5 Summary ...43

Chapter 4 RF Noise Modeling and Characterization for SOI Dynamic Threshold Voltage MOSFETs 4.1 Introduction ...64

4.2 Devices and Experiments ...65

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vii

Chapter 5 RF Noise Characterization for the Tensile-Strained nMOSFET

5-1 Introduction ...103

5-2 Devices and Measurements ...103

5-3 Channel Noise Characterization ...104

5-4 Noise Parameters Characterization ...106

5-5 Summary ...107

Chapter 6 Millimeter-Wave Noise Characterization 6.1 Introduction ...123

6.2 Devices and Experiments ...123

6.3 Channel Noise Source Characterization and Modeling ...124

6.4 Noise Parameter Characterization and Modeling ...126

6.4.1 Intrinsic Noise Parameters ...127

6.4.2 The Impact of Gate Resistance on Noise Parameters ...127

6.4.3 The Impact of Substrate Resistance on Noise Parameters ...128

6.5 Summary ...129

Chapter 7 Conclusion ...144

Vita (Chinese) ...147

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Table Captions

Chapter 2

Table 2-1 Extracted model parameters for the extrinsic resistances. The values of

G F F N N W

L/ / / for FET1, FET2 and FET3 are 0.12μm/2.4μm/16/3 ,

μm/2/18 8 . 1 / μm 12 . 0 , and 0.12μm/3.6μm/11/4, respectively. ...20 Table 2-2 Extracted model parameters for the intrinsic modeling. (VGS=1.2V ) ...21

Chapter 3

Table 3-1 Extracted gd0, C0 and their normalizations with respect to cases at -40℃ for the bulk MOSFET. (L0.36μm ) ...48

Table 3-2 Extracted Rs , Rd , and R for both the SOI and bulk devices. g

(L0.12 μm )... 49

Chapter 4

Table 4-1 Extracted model parameters for bias condition VGS 0.8V,andVDS 1V .

G F F N N W L/ / / =0.24μm/1μm/8/16) ...79

Chapter 6

Table 6-1 Extracted intrinsic small-signal parameters that can benefit the characterization of the noise parameters. (VGS 1.0V,VDS 1.2V) ...132

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ix

Figure Captions

Chapter 2

Figure 2-1 ID versus V curves for the RF SOI MOSFETs showing their properties of DS

being partially depleted. (L/WF /NF /NG = 0.12μm/2.4μm/16/3) ...22 Figure 2-2 Traditional equivalent circuit for the bulk MOSFET under the zero condition.

...23 Figure 2-3 Resistance curves for the bulk and PD SOI MOSFETs. (L/WF /NF /NG =

μm/16/3 4 . 2 / μm 12 . 0 ) ...24 Figure 2-4 (a) Cross-sectional view of the SOI MOSFET under the zero condition, and (b)

its corresponding equivalent circuit. ...25

Figure 2-5 Model-data comparison for the extraction of extrinsic resistances.

(L/WF /NF /NG = 0.18μm/2.4μm/16/3) ...26 Figure 2-6 Modeling results for extrinsic resistance extraction considering the neutral-body

effect. (symbols: measured data; lines: models) ...27 Figure 2-7 Correlation between Re

Z22Z12

, Re Z

 

12 , and Re

Z11Z12

. (symbols:

measured data; lines: models) ...28 Figure 2-8 Intrinsic small-signal model considering the neutral-body effect for the SOI

MOSFET. ...29 Figure 2-9 Modeling results of Cgs, C and gd g . (symbols for measured data, lines for m

models, and L/WF /NF /NG = 0.12μm/3.6μm/16/2) ...30 Figure 2-10 Modeling results of (a) G , and (b) out C . (symbols for measured data, lines for out

models, and L/WF /NF /NG = 0.12μm/3.6μm/16/2) ...31 Figure 2-11 Modeling results of (a) S11 and S22, and (b) S21 and S12. (frequency: 0.2 ~ 10GHz, symbols for measured data, lines for models, and L/WF /NF /NG =

μm/16/2 6 . 3 / μm 12 . 0 ) ...32

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Figure 2-12 Modeling results of (a) S11 and S22, and (b) S21 and S12 with and without considering the neutral-body effect (NBE). The anomalous behaviors are highlighted, and the bias conditions for Bias A and B are VGS 0.4V ,

V 2 . 1  DS

V and VGS 1.2V,VDS 1.2V, respectively. (frequency: 1MHz ~

6GHz, and L/WF /NF /NG = 0.12μm/2.4μm/16/3) ...33 Figure 2-13 Modeling results of (a) S22 and S22, and (b) S21 and S21 with and

without considering the neutral-body effect (NBE). The bias conditions for Bias A and B are VGS 0.4V , VVDS 1.2 and VGS 1.2V , VVDS 1.2 , respectively. (L/WF /NF/NG = 0.12μm/2.4μm/16/3) ...34 Figure 2-14 gDC and g versus b VDS for different VGS . ( L/WF /NF /NG =

μm/16/2 6 . 3 / μm 12 . 0 ) ...35 Figure 2-15  versus V for different DS V . (GS L/WF /NF /NG = 0.12μm/3.6μm/16/2)

...36

Chapter 3

Figure 3-1 Induced gate noise (S ) versus frequency for the bulk MOSFET under different ig

temperatures. (L0.36μm , and VGSVDS 1.2V) ...50 Figure 3-2 Channel noise (S ) versus frequency for the bulk MOSFET under different id

temperatures. (L0.36μm , and VGSVDS 1.2V) ...51 Figure 3-3 Correlation noise (Sigd*) versus frequency for bulk MOSFET under different

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xi

Figure 3-6 Temperature dependence of  for bulk devices with different channel lengths. ... 55 Figure 3-7 Temperature dependence of g for bulk devices with different channel lengths.d0

...56 Figure 3-8 Temperature dependence of S for bulk devices with different channel lengths.id

...57 Figure 3-9 Temperature dependence of g for bulk devices with different channel lengths.m

...58

Figure 3-10 Temperature dependence of (a) NFmin and (b) R for bulk devices with n

different channel lengths. ...59 Figure 3-11 Noise factor  for both SOI (symbols) and bulk (lines) devices with different

channel lengths. ...60 Figure 3-12 Temperature dependence of noise factor  for both SOI (symbols) and bulk

(lines) devices. ...61 Figure 3-13 The comparison of (a) S , (b) id g , and (c) m C versus current for a given gg

voltage between the bulk and SOI MOSFETs. (VDS 1.0V) ...62 Figure 3-14 The comparison of (a) NFmin, and (b) R versus current for a given voltage n

between the bulk and SOI MOSFETs. (VDS 1.0V) ...63

Chapter 4

Figure 4-1 Temperature dependence of the threshold voltage for SOI DT MOSFETs. ...80

Figure 4-2 RF small-signal equivalent circuit for the SOI DT MOSFET.

...81 Figure 4-3 Model-data comparison for the extraction of series resistances using zero method.

(L/WF /NF /NG 0.24μm/1μm/8/16, and VGSVDS 0V) ...82 Figure 4-4 Proposed parameter extraction flow. ...83

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Figure 4-5 Modeling results for (a) Re

 

Y and (b) Im

 

Y .

(L/WF /NF /NG=0.24μm/1μm/8/16). ...84 Figure 4-6 RF small-signal and noise equivalent circuit for the SOI DT MOSFET.

...85 Figure 4-7 Noise modeling results for (a) NFmin, R , and (b) n  . (opt id = 60 pA Hz, and L/WF /NF /NG=0.24μm/1μm/8/16) ...86 Figure 4-8 (a) g , (b) m R , and (c) ds C versus gs VDD characteristics for DT and standard MOSFETs with different channel lengths. (WF /NF /NG= μm/8/161 ) ...87 Figure 4-9 (a) gmb and g , (b) m Cj,sb and Cj,db , and (c) R versus b VDD

characteristics for DT MOSFETs with different channel lengths. (WF /NF /NG= μm/8/161 ) ...88 Figure 4-10 Temperature dependences of (a) C , (b) gs R , and (c) ds g for SOI DT m

MOSFETs. (L/WF /NF /NG=0.12μm/1μm/8/16) …...…………89 Figure 4-11 Temperature dependences of (a) Cj,sb and Cj,db, (b) R , and (c) b g for the mb

SOI DT MOSFET. (L/WF /NF /NG=0.12μm/1μm/8/16) ...90 Figure 4-12 (a) Model-data comparison for (a) f , and (b) t fmax. ...91

Figure 4-13 Temperature dependences of (a) H21 and (b) U for the SOI DT MOSFET.

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xiii

………...………..………96 Figure 4-18 Channel noise versus VDD.

(WF /NF /NG= μm/8/161 ) ...97 Figure 4-19 The temperature dependences for (a) S , and (b) id g . d0

(WF /NF /NG= μm/8/161 ) ...98 Figure 4-20 The temperature dependences for (a) R , and (b) n 2

m g .

(WF /NF /NG= μm/8/161 ) ...99 Figure 4-21 (a) The noise contribution from the body noise to the output noise current with respect to that from the channel noise. (b) The extracted body resistance as a function of VDD. (WF /NF /NG= μm/8/161 ) ...100

Figure 4-22 Sensitivity analysis of the variation of R to its noise contribution. b

(WF /NF /NG= μm/8/161 ) ...101 Figure 4-23 NFmin as a function of VDD at different temperatures for various channel

length devices. (WF /NF /NG= μm/8/161 ) ...102

Chapter 5

Figure 5-1 Tensile stress in the channel of a high-strained nMOSFET.

...111

Figure 5-2 IV characteristics for the strained and control devices. ( L 60nm)

...112 Figure 5-3 f and t fmax versus drain current for the strained and control devices.

(L60nm). ...113

Figure 5-4 The measured and modeled results for NFmin and R . (n L 60nm)

...114 Figure 5-5 Power spectrum density of the channel noise (Sid) versus temperature for the

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Figure 5-6 (a) Similar drain saturation voltage (VD,sat) for the strained and control devices at

each temperature, and (b) the good match between the measured Sid and

Asgaran model (Equ. (5-1)). (L60nm) ...116 Figure 5-7 (a) Channel conductance at zero drain bias (gd0) and (b) noise factor ( ) versus temperature. (L60nm). ...117

Figure 5-8 Noise factor versus channel length for different ambient temperatures.

...118 Figure 5-9 Trans-conductance (gm) versus drain current for the strained and control devices.

The insets show the gate capacitance versus drain current. (L60nm). ...119 Figure 5-10 Sid versus drain current for the strained and control devices. ( L 60nm)

... 120 Figure 5-11 (a) NFmin , (b) Rn, (c) opt , and (d) opt versus drain current for the

strained and control devices. (L60nm) ...121 Figure 5-12 Access resistances for the strained and control devices. Rs, R , and d Rg are

access resistances associated with the source, drain and gate terminals, respectively. (L60nm) ...122

Chapter 6

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xv

the frequency dependence. ...135 Figure 6-4 Short-circuit current gain (|H21 |), unilateral power gain (U ), and associated

gain (Ga,ass) versus frequency. ...136 Figure 6-5 Noise factor  versus gate length. ...137 Figure 6-6 Extracted channel noises (symbols) and their theoretical values (lines) calculated

using Equ. (6-2) versus drain current. ...138 Figure 6-7 Saturation voltage versus channel length. ...139 Figure 6-8 Modeled (a) NFmin, (b) Rn, (c) Gopt , and (d) Bopt versus frequency. The

impact of Sig, the gate resistance and the substrate resistance on these noise

parameters are also shown. ...140 Figure 6-9 Sid and Rn,int versus 2

m

g . ...141

Figure 6-10 Extracted gate resistance (Rg) versus channel length. ...142 Figure 6-11 Rb and Sib Sid versus gate length. ...143

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Chapter 1

Introduction

With the advantages of low cost, low power, high integration capability, and easy access to technology [1][2], CMOS technology has become an attractive choice for RF applications. Specifically, the continuous downscaling of CMOS processes beyond the deep sub-micron generation has led to the improved cut-off frequency ( ft) and minimum noise figure (NFmin) of MOSFETs [3]-[5].

To save time to market and reduce the design cycle, the demand for accurately modeling the RF characteristics is strong and has attracted a bunch of studies. Recently, a lot of investigations on the RF small-signal characterization and modeling for the traditional bulk MOSFET have been reported. The equivalent circuit used to analyze and model the RF small-signal behaviors for bulk MOSFETs is well-built, and the parameter extraction methodology has been well-developed, either for the intrinsic or extrinsic components [6]-[10]. Based on this mature equivalent circuit, many reports on RF noise characterization and modeling have been presented accordingly. They have shown that both the channel noise and noise factor would increase with decreasing channel length [11][12], and this can harm the RF noise performance. Besides, the impact of parasitics associated with the probing pad and substrate has been examined [13][14]. The temperature dependent noise behavior for the bulk MOSFET, however, has rarely been discussed.

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2

to the above mega-hertz application [19]. In fact, we will show that the coupling path through the quasi-neutral body region may still play an important role in the RF SOI modeling in several GHz. Besides, several studies have considered the self-heating effect to capture the noise behavior for the SOI MOSFETs [20][21]. Nevertheless, the direct comparison of RF noise performance between the bulk and SOI MOSFETs in terms of noise parameters and white- noise factor has not been widely reported.

Another novel device formed by connecting the gate and body terminal together is the dynamic-threshold voltage MOSFET (DT MOSFET). The DT MOSFET, which can be fabricated using the SOI process, has the advantages of larger current driving ability and low leakage current [22]. Hence, it is also attractive for RF application [23]. To give a comprehensive discussion, we will cover the study on the temperature effect of body-related parasitics and series resistances on ft and fmax . The RF noise behavior and its temperature dependence will be addressed as well.

To maintain the scaling trends of CMOS devices while bypassing the other physical and technological issues, strain-engineering technology has become a popular way to fabricate devices. Recently, the strained CMOS technology has demonstrated its excellent RF performance with a high cut-off frequency ( ft) [24]. However, the effects of the highly tensile stressors on the high frequency noise characteristics have rarely been unveiled. Hence, it is necessary to investigate and analyze the high frequency noise characteristics of tensile-strained nMOSFETs.

Besides, with the continuous downscaling of channel length toward deca-nanometer regime, RF MOSFETs have entered the field of millimeter-wave applications [25]. The previous works have discussed the RF noise behavior for deep sub-micron MOSFETs operating mainly in several GHz, and the experimental results for the millimeter-wave noise characterization and its corresponding modeling are deficient. We will use an external tuner-based method to demonstrate a complete millimeter-wave noise characterization and modeling up to 60GHz for 65nm MOSFETs. Since the gate resistance and substrate loss have

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been reported to be main issues to degrade the RF noise performance, these effects will be considered in this thesis.

This dissertation is organized as follows. Chapter 2 presents small-signal modeling for RF SOI MOSFETs. Especially, we have incorporated the neutral-body effect in our RF SOI model. This effect can not be ignored in both RF extrinsic and intrinsic modeling stages. In addition, we have developed a physically-accurate parameter extraction method based on our analytical expressions. Our modeling results agree well with the measured data and can capture the frequency dependences of both output conductance and capacitance in the GHz frequency region. The anomalous S22 and S21 behaviors as well as the output conductance rising effect observed in our measurements can be predicted and described using the proposed model.

In chapter 3, we experimentally study the temperature dependence of the power spectrum densities (PSDs) of the intrinsic noise sources for both the RF bulk and SOI MOSFETs. The popular van der Ziel’s model is used to check its applicability at different temperatures. The power spectral density (PSD) for the channel noise current is found to decline as temperature increased due to the decreased channel conductance. Along with the extracted small-signal and van der Ziel’s model parameters, their temperature dependences can be well described. For completeness, their temperature-dependent noise parameters are demonstrated as well. Besides, for SOI MOSFETs, our experimental results reveal that the significant floating body effect and the self-heating effect may contribute to the higher noise

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4

minimum noise figure (NFmin). Our study may provide insights for RF circuit design using advanced SOI DT MOSFETs.

The high-frequency noise behavior of tensile-strained nMOSFETs, including its temperature dependency, is experimentally examined in Chapter 6. Our experimental results indicate that with similar saturation voltages, the strained nFET is found to have a larger channel noise than the control device at the same bias point. For a given DC power consumption, however, due to enhanced trans-conductance, the strained nFET has better small signal behaviors (higher ft and fmax) and noise characteristics (smaller NFmin and Rn) than the control device.

Using an external tuner-based method, Chapter 6 demonstrates a complete millimeter-wave noise characterization and modeling up to 60GHz for 65nm MOSFETs for the first time. Due to channel length modulation, the channel noise continues to increase and remains the most important noise source in the millimeter-wave band. Our experimental results further show that, with the downscaling of channel length, the gate resistance has more serious impact on the high frequency noise parameters than the substrate resistance even in the millimeter-wave frequency.

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References

[1] P. H. Woerlee, M. J. Knitel, R. Langevelde, D. B. M. Klaassen, L. F. Tiemeijer, A. J. Scholten, and A. Duijnhoven, “RF-CMOS performance trends,” IEEE Trans. Electron

Devices, vol. 48, pp. 1776–1782, Aug. 2001.

[2] A. A. Abidi, “RF CMOS comes of age,” IEEE J. Solid State Circuits, vol. 39, pp. 549–561, Apr. 2004.

[3] E. Morifuji, H. S. MoMose, T. Ohguro, T. Yoshitomi, and H. Kimijima, “Future perspective and scaling down roadmap for RF CMOS,” in VLSI Tech. Symp., 1999, pp. 163–164.

[4] C. S. Chang, C. P. Chao, J. G. J. Chern, and J. Y. C. Sun, “Advanced CMOS technology portfolio for RF IC application,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1324–1334, Jul. 2005.

[5] H. S. Bennett, R. Brederlow, J. C. Costa, P. E. Cottrell, W. M. Huang, A. A. Immorlica, J. E. Mueller, M. Racanelli, H. Shichijo, C. E. Weitzel, and B. Zhao, “Device and technology evolution for Si-based RF integrated circuits,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1235–1257, Jul. 2005.

[6] S. Lee, H. K. Yu, C. S. Kim, J. G. Koo, and K. S. Nam, “A novel approach to extracting small-signal model parameters of silicon MOSFET’s,” IEEE Microw. Guided Wave Lett., vol. 7, no. 1, pp. 75–77, Jan. 1997.

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6

Integrated Circuits (RFIC) Symp., Seattle, WA, Jun. 2002, pp. 355–35.

[10] S.-C. Wang, G.-W. Huang, K.-M. Chen, A.-S. Peng, H.-C. Tseng, and T.-L. Hsu, “A practical method to extract extrinsic parameters for the silicon MOSFET small signal model,” in Proc. NSTI Nanotechnol. Conf., Boston, MA, 2004, pp. 151–154.

[11] C. H. Chen, M. J. Deen, Y. Cheng, and M. Matloubian, “Extraction of the induced gate noise, channel noise and their correlation in sub-micron MOSFET’s from RF noise measurements,” IEEE Trans. Electron Devices, vol. 48, pp. 2884–2892, Dec. 2001. [12] A. F. Tong, W. M. Lim, K. S. Yeo, C. B. Sia, and W. C. Zhou, “A scalable RFCMOS

noise model, ” IEEE Trans. Microwave Theory Tech., vol. 57, no. 5, pp. 1009-1019, May 2009.

[13] C. Enz, “An MOS transistor model for RF IC design valid in all regions of operation,”

IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 342–359, Jan. 2002.

[14] J.-C. Guo, Y.-H. Tsai, “A broadband and scalable lossy substrate model for RF noise simulation and analysis in nanoscale MOSFETs with various pad structures,” IEEE Trans.

Microwave Theory Tech., vol. 57, no. 2, pp. 271-281, Feb. 2009.

[15] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Trans. Electron Devices, vol. 44, pp. 2252–2261, Dec. 1997.

[16] E. Zencir, N. S. Dogan, and E. Arvas, “Modeling and performance of spiral inductors in SOI CMOS technology,” IEEE Canadian Conference on Electrical and Computer

Engineering, May 2002, pp. 408-411.

[17] D. Lederer, D. Flandre, and J.-P. Raskin, “Frequency degradation of SOI MOS device output conductance,” Semicond. Sci. Technol., vol. 20, pp. 469–472, 2005.

[18] W. Jin, P. C. H. Chan, S. K. H. Fung, and P. K. Ko, “Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFETs,” IEEE Trans.

Electron Devices, vol. 46, pp. 1180–1185, June 1999.

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SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling,” IEEE Trans. Electron Devices, vol. 45, pp. 1017–1025, May 1998.

[20] G. Dambrine, J.-P. Raskin, F. Danneville, D. Vanhoenacker-Janvier, J.-P. Colinge, and A. Cappy, “High-frequency four-noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits,” IEEE Trans. Electron

Devices, vol. 46, pp. 1733–1741, Aug. 1999.

[21] W. Jin, P. C. H. Chan, and J. Lau, “A physical thermal noise model for SOI MOSFET,”

IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 768–773, Apr. 2000.

[22] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans.

Electron Devices, vol. 44, pp. 414–422, Mar. 1997.

[23] C.-Y. Chang, J.-G. Su, H.-M. Hsu, S.-C. Wong, T.-Y. Huang, and Y.-C. Sun, “Investigation of bulk dynamic threshold-voltage MOSFET with 65 GHz ‘nomal mode’ ft and 220 GHz ‘over-drive mode’ ft for RF applications,” in VLSI Technol. Tech. Symp.

Dig., 2001, pp. 89–90.

[24] D. V. Singh, K. A. Jenkins, J. Sleight, Z. Ren, M. Ieong, and W. Haensch, “Strained ultrahigh performance fully depleted nMOSFETs with ft of 330 GHz and sub-30-nm gate lengths,” IEEE Electron Device Lett., vol. 27, no. 3, pp. 191-193, March 2006.

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8

Chapter 2

RF Small-Signal Modeling and Characterization for SOI

MOSFETs

2.1 Introduction

Due to its highly integrated nature and good scaling capabilities, CMOS technology has become an excellent choice for RF applications. SOI CMOS is especially a promising candidate for the RF system-on-chip integration because of its low source and drain parasitic capacitances, high process capability with the traditional bulk Si process, reduction in cross-talk between RF and digital circuits, and easy integration of high quality passive elements [1][2]. With the penetration of SOI CMOS into RF applications [3][4], RF SOI small-signal modeling has become a crucial design issue.

Although several investigations [5]-[8] regarding the RF SOI small-signal modeling have been carried out in the past, it was assumed that the RF small-signal equivalent circuit of the SOI MOSFET is essentially identical to that of the bulk counterpart. Moreover, Lederer et al. proposed a SOI model suitable for body-tied devices without considering the neutral-body region underneath the gate oxide layer [6]. However, we will show that the coupling path between the source and drain terminals through the quasi-neutral body region may play an important role in the RF SOI modeling [9].

In this chapter, we will present a comprehensive RF SOI small-signal model considering this neutral-body path [10]. Based on this model, the methods suitable for RF extrinsic and intrinsic parameter extractions will also be demonstrated. Finally, the neutral-body effect on the output characteristics will be investigated as well [11].

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2.2 Devices and Experiments

The RF SOI MOSFETs used in this work were fabricated using UMC 0.13 μm SOI technology. The thicknesses for gate oxide, SOI layer and buried oxide are 1.4nm, 40nm, and 200nm, respectively. These RF devices were laid out in the multi-finger and multi-group structure with the following denotations: L for channel length, WF for finger length, NF

for the number of fingers, and NG for the number of groups (i.e. total gate width

G F

F N N

W

W    ). The presence of current kinks in Fig. 2-1 shows that the devices under

study are partially depleted (PD).

On-wafer 2-port common-source S parameters were measured using network analyzers with microwave probes. To eliminate the inevitable parasitic accompanied with the probing

pads, the S parameters of devices’ corresponding open dummy ware measured and then

used to perform the de-embedding procedure. After that, the de-embedded S parameters of the devices will be transformed to Z parameters to participate in the following extraction of the extrinsic terminal resistances.

To further minimize possible substrate resistive loss through the buried oxide layer [12], a bias-network connected to the chuck of the probe station was used to provide the substrate DC ground (i.e. back-gate voltage VES = 0) with RF floating.

2.3 Neutral-Body Effect on the Resistance Extraction

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10

derived to directly determine Rs, R , and d Rg, respectively.

 

Z21 Re

 

Z12 Rs Re (2-1)

Z22Z12

Rd Re (2-2)

Z11Z12

Rg Re (2-3)

Figure 2-3 compares the resistance curves versus frequency characteristics under the zero condition for PD SOI MOSFET and its bulk counterpart with identical layout structure and geometry. All of these curves more or less are frequency-dependent. The poor shapes for the bulk MOSFET can be attributed to the complicated and significant substrate resistive loss [17][18]. For the SOI MOSFET, however, the substrate loss may not be responsible for this frequency-dependent behavior because the thick buried oxide layer in the SOI transistor has provided good isolation from the substrate.

We turn to consider the neutral-body parasitics beneath the channel of the SOI MOSFET. Figure 2-4(a) shows its cross-sectional view under the zero condition. The neutral-body coupling path is constituted by source- and drain-side junction capacitances (Cj,sb and Cj,db),

and body resistances (R ). Its corresponding equivalent circuit is depicted in Fig. 2-4(b). Here b

the neutral-body coupling path is represented by a lumped junction capacitance C b

[

1

1 , 1 ,   

Cjsb Cjdb ] and a body resistance R . Based on this equivalent circuit, the following b

more general resistance expressions regarding Rs, R , and d Rg can be derived:

 

 

B A R Z Z s     12 2 21 Re Re  (2-4)

 

 

B A R Z Z d      12 2 22 Re Re   (2-5)

 

 

B A R Z Z g       12 2 11 1 Re Re    (2-6) where

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2

1 1  Cgd Cgs Cgd Cb RbA , (2-7)

 



2 1 2 2 2 2 2 2 2 2 4 2 2                  b b ds gd gs gd gs ds b gd gs gd gs b ds ds gd gs ds b gd gs b gd gs R C C C C C C C C C C C C C C C C C C C C C C C C B , (2-8) gd gs C C   , (2-9) and

gs ds

gd ds b

gd gs

ds gs b

ds gd

b gd gsC C C C C C C C C C C C C C C 2 2 2 2 2 2 2 2 2   . (2-10)

The frequency independent parameters, A , B ,  and , are all constants involved with intrinsic parameters under the zero condition. Besides, as shown in Fig. 2-3, whether the substrate RF ground is provided or not, the resistance curves are almost unchanged. This indicates that the substrate effect is negligible in our experiments. Therefore, to simplify the equivalent circuit, any substrate parasitic through the buried oxide has been omitted here.

According to Equs. (2-4) to (2-6), it is obvious that these resistance expressions are frequency dependent, and the extrinsic resistances are equal to their high frequency asymptotes. In practice, although we cannot rely on the very high frequency measurement to directly obtain these resistance values, they can be obtained by fitting the resistance expressions with their corresponding measured data. The achieved model-data comparison for the extraction of Rs, Rd, and Rg are shown in Fig. 2-5. It can be seen that the measured

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12

regions were out-connected at only one side. In addition, the interconnection between each group can provide additional resistance for the drain terminal and result in discrepancy between Rs and Rd . Also note that the nearly unity  implies CgsCgd , which is

reasonable for multi-finger structures and has been widely used under the zero condition [15]. The good agreements between the modeled and measured data for the resistance curves with various layout geometries can be found in Fig. 2-6 ( 1). Besides, according to Equs. (2-4) to (2-6), Re(Z22Z12), Re(Z12), and Re(Z11Z12) are mutually correlated [14] by:

Z22 Z12

Re

 

Z12 Rds Re (2-11)

Z11Z12

0.5Re

 

Z12 Rgs Re (2-12)

Z11Z12

0.5Re

Z22Z12

Rgd Re (2-13)

where RdsRdRs, RgsRg 0.5Rs, and RgdRg0.5Rd. Equations (2-11) to

(2-13) have been verified in Fig. 2-7.

The extracted extrinsic resistances and model parameters A , B , Rds, Rgs, and

d g

R for each SOI device are listed in Table 2-1. Besides, since all the involved device

conductance and capacitances in Equs. (2-4) to (2-6) are proportional to the total gate width

W , the parameter A should increase as W decreases. As indicated in Fig. 2-6, the

resistance curves for the device with smaller W indeed have a larger deviation from its high-frequency asymptote in the lower frequency regime. Therefore, one can minimize the extraction error resulted from the SOI neutral-body effect by using the wide device.

2.4 Neutral-Body Effect on the Intrinsic Modeling

After extracting Rs/Rd /Rg, we can obtain the intrinsic Z parameters (Zi) of the

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                 s d s s s g i i i i R R Z R Z R Z R R Z Z Z Z Z 22 21 12 11 22 , 21 , 12 , 11 , . (2-14)

Then, the intrinsic Y parameters (Y ) can be obtained directly from the Z -to- Y i

parameter transformation of Z . i

Based on the equivalent circuit proposed in [20], Figure 2-8 shows the intrinsic small-signal equivalent circuit for SOI devices under the active operation, where the neutral-body parasitic is represented by a series combination of two junction capacitances,

sb j

C , and Cj,db, and a body resistance R along with the body trans-conductance b g . It is mb

worth noting that, instead of the particular access resistance introduced via the external body

contacts in body-tied or dynamic-threshold SOI MOSFETs [6][7], R may represent the b

un-depleted body resistance for all kinds of SOI MOSFETs. In addition, to simplify the following derivations, some modifications have been made to this circuit. First, the junction related conductances are neglected in the equivalent circuit because the junction capacitances would dominate the entire junction admittances at high frequency. Second, the conductance caused by the body potential through the impact ionization is also omitted due to its low pass nature [20]. Finally, the intrinsic body node is assigned to be located just next to the source-body junction as usually done in bulk MOSFET models.

Since the major impact of the neutral-body effect on the equivalent circuit lies in the output admittance Yout , which is equal to Yi,22Yi,12 and defined by the dashed box shown

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14

Figure 2-9 shows these extraction results, and their frequency independences also reveal the accuracy of the resistance extraction method presented in the previous section. Note that for our devices with cut-off frequency larger than 90 GHz, the delay time constant  can be neglected for the operating frequency not exceeding 10 GHz.

To extract Yout-related components, however, the following analytical equations must be used.

 

            2 , , 2 2 , 2 , 2 , , , 2 , 2 , 2 1 1 Re db j sb j b db j sb j sb j db j ds db j mb ds b db j sb j ds out out C C R C C C C R C g R R C C R Y G   (2-18)

 

          2 , , 2 2 , 2 , 2 , , , , , 1 Im db j sb j b db j sb j ds b db j mb db j sb j db j sb j ds out out C C R C C C R C g C C C C C Y C   (2-19) One can find that Equs. (2-18) and (2-19) will tend to saturate at 1 1

b ds R

R and Cds,

respectively at very high frequency. This is because the short-circuited junction capacitances at high frequencies (both the junction impedances

jCj,sb

1 and

jCj,db

1 approach 0) cause the residual body resistance to be parallel with the channel resistance, and makes no other capacitance except Cds left. Therefore, RF output conductance (denoted as gRF ) extracted from the high frequency asymptote of Gout would be the parallel combination of channel conductance and body conductance ( 1 1

b ds R

R ) and is larger than sole channel

conductance 1

ds

R , which can be extracted from the DC current-voltage (IV) measurement

(denoted as gDC).

The modeling results of Gout and Cout for various drain bias conditions with gate bias 1.2V are shown in Figs. 2-10(a) and (b), respectively, where the frequency dependence natures of both Gout and Cout can be described by our model (Equs. (2-18) and (2-19)). Here, 1

ds

R is directly extracted from gDC, 1

b

R from gRFgDC, and Cds from the high frequency asymptote of Cout, and for clarity, all the extracted component values are listed in

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Table 2-2. These figures show that the neutral-body effect would play an important role

mostly in the low GHz region. To be more completed, the good modeling results of S

parameters considering the neutral-body effect (NBE) have been verified and are shown in Fig. 2-11.

It is also worth noting that, for SOI MOSFETs, our model can predict the occurrence of anomalous behaviors in the S parameters. In Fig. 2-12(a), two abnormal phenomena in S22

can be observed - the inductance-like behavior for Bias A condition and the kink behavior for Bias B. Also, the abnormal S21 behaviors can be observed in Fig. 2-12(b). The modeling results for their magnitude and phase versus frequency characteristics can also be found in Fig. 2-13. In these figures, only the proposed model considering the neutral-body effect can capture these abnormal phenomena prominent in lower frequency region. This also indicates the need of considering the neutral-body effect when it comes to the RF SOI modeling especially below several GHz.

2.5 Neutral-Body Effect on the Output Characteristics

We have shown how the SOI-specific neutral-body affects the small-signal model structure and the parameter extraction for both extrinsic and intrinsic parts of RF SOI MOSFETs. For RFIC designers, it is also important to evaluate the significance of the neutral-body effect on the increase of the RF output conductance, which may dominate the circuit performance.

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16

figures show that the body conductance gb has the chance to be comparable with or even larger than the channel conductance gDC. Therefore, the neutral-body effect can influence the RF performance to a great extent.

2.6 Summary

The SOI neutral-body coupling effect should be considered for the characterization and modeling of SOI MOSFETs, although the thick buried oxide can block the complicated substrate network. An equivalent circuit including the neutral-body parasitics has been proposed, and a new set of model equations capturing the frequency dependence of extrinsic resistances and output characteristics has been derived accordingly. After taking into account the impact of quasi-neutral body, we have completed a physically accurate RF small-signal characterization and modeling for SOI MOSFETs.

The neutral-body parasitics predict and explain the existence of anomalous S22 and

21

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References

[1] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Trans. Electron Devices, vol. 44, pp. 2252–2261, Dec. 1997.

[2] E. Zencir, N. S. Dogan, and E. Arvas, “Modeling and performance of spiral inductors in SOI CMOS technology,” IEEE Canadian Conference on Electrical and Computer

Engineering, May 2002, pp. 408-411.

[3] J. Kim, J.-O Plouchart, and N. Zamdmer, “Design and manufacturability aspect of SOI CMOS RFICs,” in Proc. Custom Integrated Circuit Conf., Oct. 2004, pp. 541-548.

[4] T. Douseki, T. Tsukahara, Y. Yoshida, F. Utsunomiya, and N. Hama, “A batteryless wireless system with MTCMOS/SOI circuit technology,” in Proc. Custom Integrated

Circuit Conf., Sept. 2003, pp. 163-168.

[5] J. P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker-Janvier, and J. P. Colinge, “Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling,” IEEE Trans. Electron Devices, vol. 45, pp. 1017–1025, May 1998.

[6] D. Lederer, D. Flandre, and J.-P. Raskin, “Frequency degradation of SOI MOS device output conductance,” Semicond. Sci. Technol., vol. 20, pp. 469–472, 2005.

[7] D. Lederer, O. Rozeau, and J.-P. Raskin, “Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements,” in Proc. IEEE Int. SOI Conf., 2005,

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18

Wireless Components Lett., vol. 17, no. 5, pp. 364–366, May 2007.

[10] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “RF extrinsic resistance extraction considering neutral-body effect for partially-depleted SOI MOSFETs,” in Proc. VLSI-TSA, Hsinchu, Taiwan, Apr. 2006, pp. 1-2.

[11] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “Radio-frequency silicon-on-insulator modeling considering the neutral-body effect,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2087-2091, April 2008.

[12] C. L. Chen et al., “High-frequency characterization of sub-0.25-μm fully depleted silicon-on-insulator MOSFETS,” IEEE Electron Device Lett., vol. 21, pp. 497–499, Oct. 2000.

[13] J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Direct extraction method of SOI MOSFET transistors parameters,” in Proc. IEEE Int. Conf. Microelectron. Test

Structures, vol. 9, pp. 191-194, Mar. 1996.

[14] J.-P. Raskin, G. Dambrine, and R. Gillon, “Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFET’s,” IEEE Microwave

Guided Wave Lett., vol. 7, no. 12, pp. 408-410, Dec. 1997.

[15] A. Bracale, V. Ferlet-Cavrois, N. Fel, D. Pasquet, J. L. Gautier, J. L. Pelloie, and J. du Port de Poncharra, “A new approach for SOI devices small-signal parameters extraction,” in Analog and Integrated Circuits and Signal Processing. Norwell, MA: Kluwer, 2000, pp. 157-169.

[16] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors,” in Proc. IEEE MTT-S Dig., 1994, pp. 865–868.

[17] W. Liu et al, “R.F.MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” in Proc. Int. Electron Devices

Meeting, Dec. 1997, pp. 309–312.

[18] R. T. Chang et al., “Modeling and optimization of substrate resistance for RF-CMOS,”

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[19] S. Lee, “Response to Comments on ‘A direct extraction technique for a small-signal MOSFET equivalent circuit with substrate parameters’,” Microwave Opt. Technol. Lett., vol. 43, pp. 268-269, 2004.

[20] R. Howes and W. Redman-White, “A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFETs,” IEEE J. Solid-State Circuits, vol. 27, pp. 1186–1192, Oct. 1992.

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20

Table 2-1 Extracted model parameters for the extrinsic resistances. The values of

G F F N N W

L/ / / for FET1, FET2 and FET3 are 0.12μm/2.4μm/16/3, 0.12μm/1.8μm/2/18, and 0.12μm/3.6μm/11/4, respectively. W ( μm ) A (1021F1s1) B (1020s2) s d R  ( ) s g R  (  ) d g R  ( ) s R ( ) d R ( ) g R ( ) FET1 115.2 4.9 7.2 1.4 1.45 2.15 0.1 1.5 1.4 FET2 64.8 6.4 6.4 2.9 1.35 2.8 0.1 3 1.3 FET3 158.4 3.5 7.4 0.9 1.55 2 0.1 1 1.5

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Table 2-2 Extracted model parameters for the intrinsic modeling. (VGS = 1.2V ) ) V ( DS V Cgs(fF) Cgd(fF) gm(mS) Cds(fF) Rds() Rb() Cj,sb(pF) Cj,db(pF) gmb(mS) 0.8 109 56 96 14 119 63 61 50 32 1 109 53 96 24 156 73 64 58 25 1.2 109 51 96 29 167 88 74 20 53

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22

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0

10

20

30

40

50

60

70

V

GS

= 0.4 V

V

GS

= 0.8 V

V

GS

= 1.2 V

I

D

(mA)

V

DS

(V)

Figure 2-1 ID versus VDS curves for the RF SOI MOSFETs showing their properties of being partially depleted. (L/WF/NF /NG = 0.12μm/2.4μm/16/3)

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24 0 5 10 15 20 -10 -5 0 5 10 15 20 25 30 35 40

Curves for resistance extraction (

)

Frequency (GHz)

Re(Z12) for bulk MOSFET

Re(Z

22-Z12) for bulk MOSFET

Re(Z11-Z12) for bulk MOSFET

Re(Z12) for SOI MOSFET

Re(Z

22-Z12) for SOI MOSFET

Re(Z11-Z12) for SOI MOSFET

Re(Z12) for SOI MOSFET with substrate RF ground

Re(Z

22-Z12) for SOI MOSFET with substrate RF ground

Re(Z11-Z12) for SOI MOSFET with substrate RF ground

Figure 2-3 Resistance curves for the bulk and PD SOI MOSFETs. (L/WF /NF /NG = μm/16/3 4 . 2 / μm 12 . 0 )

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Figure 2-4 (a) Cross-sectional view of the SOI MOSFET under the zero condition, and (b) its corresponding equivalent circuit.

(a)

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26

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0

2

4

6

8

10

Rg = 0.4  Rd = 2.2 

Re(

Z

12

) and Re(

Z

22

-Z

12

) (

)

Frequency (GHz)

model

measurement

Re(Z

22

-Z

12

)

Rs = 0.5 

A = 6.5

10

21

F

-1

s

-1

B = 7

10

8

s

-2

= 1.04

Re(

Z

11

-Z

12

) (

)

Figure 2-5 Model-data comparison for the extraction of extrinsic resistances.

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0

5

10

15

20

-10

-8

-6

-4

-2

0

2

4

6

8

10

0

2

4

6

8

10

12

14

16

18

20

Lf/Wf/NF/NG = 0.12m/2.4m/16/3 Lf/Wf/NF/NG = 0.12m/1.8m/2/18 L f/Wf/NF/NG = 0.12m/3.6m/11/4

Re(Z

22

-Z

12

)

Re(Z

11

-Z

12

)

Re(Z

11

-Z

12

) or Re(12) (

)

Frequency (GHz)

Re(Z

12

)

Re(Z

22

-Z

12

) (

)

Figure 2-6 Modeling results for extrinsic resistance extraction considering the neutral-body effect. (symbols: measured data; lines: models)

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28 0 1 2 3 4 5 6 -8 -7 -6 -5 -4 -3 -2 -10 1 2 3 4 5 6 7 8 9 100 2 4 6 -2 -1 0 1 2 Lf/Wf/NF/NG = 0.12um/2.4um/16/3 Lf/Wf/NF/NG = 0.12um/1.8um/2/18 Lf/Wf/NF/NG = 0.12um/3.6um/11/4 Re(Z 11-Z12) Re(Z 11 -Z 12 ) or Re(Z 22 -Z 12 ) (  ) Re(Z 12) () Re(Z22-Z12) Re(Z 11 -Z 12 ) (  ) Re(Z22-Z12) ()

Figure 2-7 Correlation between Re

Z22Z12

, Re Z

 

12 , and Re

Z11Z12

. (symbols: measured data; lines: models)

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Figure 2-8 Intrinsic small-signal model considering the neutral-body effect for the SOI MOSFET.

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30 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 20 40 60 80 100 120 140 C gs and C gd (fF) Frequency (GHz) Cgd Cgs g m (mS) g m

Figure 2-9 Modeling results of Cgs, Cgd and gm. (symbols for measured data, lines for models, and L/WF /NF /NG = 0.12μm/3.6μm/16/2)

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0 1 2 3 4 5 15 20 25 VDS = 1.2 V, VGS = 1.2 V VDS = 1 V, VGS = 1.2 V G out (m S ) Frequency (GHz) VDS = 0.8 V, VGS = 1.2 V 0 1 2 3 4 5 0 50 100 300 400 500 VDS = 0.8 V, VGS = 1.2 V V DS = 1 V, VGS = 1.2 V V DS = 1.2 V, VGS = 1.2 V C out (fF) Frequency (GHz)

Figure 2-10 Modeling results of (a) Gout, and (b) Cout. (symbols for measured data, lines for models, and L/W /N /N = 0.12μm/3.6μm/16/2)

(a)

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32 S11 VDS = 0.8 V, VGS = 1.2 V VDS = 1 V, VGS = 1.2 V VDS = 1.2 V, VGS = 1.2 V S22 0 1 2 3 4 5 0 45 90 135 180 225 270 315 0 1 2 3 4 5 10S12 S21 S22 VDS = 0.8 V, VGS = 1.2 V VDS = 1 V, VGS = 1.2 V VDS = 1.2 V, VGS = 1.2 V

Figure 2-11 Modeling results of (a) S11 and S22, and (b) S21 and S12. (frequency: 0.2 ~

10GHz, symbols for measured data, lines for models, and L/WF /NF /NG =

μm/16/2 6 . 3 / μm 12 . 0 )

(a)

(b)

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measurement

simulation without NBE simulation with NBE

A Bias B Bias 22 S 11 S measurement

simulation without NBE simulation with NBE

A Bias B Bias 22 S 11 S 0 1 2 3 4 5 6 0 45 90 135 180 225 270 315 0 1 2 3 4 5 6 measurement

simulation without NBE simulation with NBE

21 S A Bias B Bias 12 S 10 0 1 2 3 4 5 6 0 45 90 135 180 225 270 315 0 1 2 3 4 5 6 measurement

simulation without NBE simulation with NBE

21 S A Bias B Bias 12 S 10

Figure 2-12 Modeling results of (a) S11 and S22, and (b) S21 and S12 with and without

(a)

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34 106 107 108 109 0.0 0.2 0.4 0.6 0.8 Bias B measurement

simulation without NBE simulation with NBE measurement

simulation without NBE simulation with NBE

|S 22 | Frequency (Hz) 106 107 108 109 -80 -60 -40 -20 0 20 Bias A Bias B 

S

22

(

)

Bias A 106 107 108 109 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 measurement

simulation without NBE simulation with NBE

|S 21 | Frequency (Hz) 106 107 108 109 170 172 174 176 178 180 182 184 186 188 190 Bias B measurement

simulation without NBE simulation with NBE

S

21

, (

)

Bias A Bias B Bias A

Figure 2-13 Modeling results of (a) S22 and S22, and (b) S21 and S21 with and

without considering the neutral-body effect (NBE). The bias conditions for Bias A and B are V 4 . 0  GS V , VVDS 1.2 and VGS 1.2V, VVDS 1.2 , respectively. (L/WF/NF/NG = μm/16/3 4 . 2 / μm 12 . 0 )

(a)

(b)

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0.8 0.9 1.0 1.1 1.2 0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24 g DC for VGS = 0.8 V g DC for VGS = 1 V g DC for VGS = 1.2 V g DC (mS) VDS (V) gb for VGS = 0.8 V g b for VGS = 1 V g b for VGS = 1.2 V g b =R b -1 (m S)

Figure 2-14 gDC and gb versus VDS for different VGS. (L/WF /NF /NG = 0.12μm/3.6μm/16/2)

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36

0.8

0.9

1.0

1.1

1.2

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VGS = 1 V VGS = 1.2 V 

V

DS

(V)

VGS = 0.8 V

Figure 2-15  versus VDS for different VGS. (L/WF /NF /NG = 0.12μm/3.6μm/16/2)

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Chapter 3

RF Noise Characterization for Bulk and SOI

MOSFETs

3.1 Introduction

The noise performance of RF MOSFETs is critical to RF applications, especially to the design of low noise amplifiers, resulting in a need for the accurate noise modeling [1]. Besides, it is well known that both the small-signal circuit parameters and noise sources play important roles in RF noise modeling. There have been many studies on the RF noise characterization and modeling for both bulk and SOI MOSFETs [1]-[9], and the temperature dependence of their small-signal performances has also been widely discussed [10]-[12]. However, the study on the temperature dependence of their RF noise sources and noise parameters was deficient. Therefore, for the purpose of temperature modeling and understanding the underlying physics, the temperature dependence of RF noise behaviors demands investigation.

Pascht et al. have presented the temperature noise model by exploiting the circuit simulator [2]. However, only the noise source for the bulk MOSFET has been discussed, and its temperature dependence was not clear. In this chapter, we will experimentally study the temperature dependence of the power spectrum densities (PSDs) of the intrinsic noise sources

數據

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參考文獻

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