低壓高速動態比較器之實現

Implementation of Low Voltage, High Speed

Dynamic Comparators

Bo-Jyun Kuo

Implementation of Low Voltage, High Speed

Dynamic Comparators

Student Bo-Jyun Kuo

Advisor Prof. Chia-Ming Tsai

A Thesis

Submitted to Department of Electronics Engineering & Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Electronics Engineering Nov. 2012

i

“ ” 65nm CMOS 0.6 GHz 0.6V 1GHz (1 ) 6mV (1 ) 0.65mV 3mV BER=10-9 38 W 0.6V 1.3GHz (1 ) 7.5mV (1 ) 0.5mV 4.2mV BER=10-9 64 W

ii

Implementation of Low Voltage, High Speed

Dynamic Comparators

Student

Bo-Jyun Kuo Advisor

Prof. Chia-Ming Tsai

Department of Electronics Engineering & Institute of Electronics

National Chiao Tung University

Abstract

This thesis presents two low voltage, high speed dynamic comparators. It

improves the core circuit “latch architecture”, so the comparators can operate

at low supply voltage. The comparators have the large enough overdrive

voltage to keep the transconductance, so the comparators can maintain the

high speed operation.And realizing comparators in 65nm CMOS. The first

comparator operate at supply voltage is 0.6V, the operating speed is 1GHz,

and the input referred offset(1 ) is 6mV, the input referred noise(1 ) is

0.65mV, and the sensitivity is 3mV to achieve the BER is 10-9. And the power

consumption is only 38 W. The second comparator operate at supply voltage

is 0.6V, the operating speed is 1.3GHz, and the input referred offset(1 ) is

7.5mV, the input referred noise(1 ) is 0.5mV, and the sensitivity is 4.2mV to

iii

iv ... i ... ii ...iii ... iv ...vii ... viii ... 1 1.1 ... 1 1.2 ... 2 ... 3 2.1 ... 3 2.2 ... 4 2.2.1 ... 4 2.2.2 ... 8 2.3 ... 10 2.3.1 ... 10 2.3.2 - ... 12 2.3.3 - ... 14 2.3.4 - (signal dependent) ... 15 2.4 ... 16 2.4.1 ... 16 2.4.2 ... 16 (I) ... 17 3.1 ... 17 3.2 (I) ... 18

v 3.2.1 ... 18 3.2.2 ... 19 3.2.3 ... 23 3.2.4 ... 25 3.2.5 ... 33 3.3 (I) ... 33 3.3.1 ... 33 3.3.2 ... 37 3.4 ... 45 (II) ... 47 4.1 ... 47 4.2 (II) ... 48 4.2.1 ... 48 4.2.2 ... 49 4.2.3 ... 52 4.2.4 - Cross-Coupled Latches ... 59 4.3 (II) ... 60 4.4 ... 63 4.5 ... 71 ... 73 5.1 ... 73 5.2 ... 74 5.3 (I) ... 78 5.3.1 ... 78 5.3.2 ... 82 5.4 (II) ... 85 5.4.1 ... 85

vi

5.4.2 ... 89

... 94 ... 95

vii 3.1 (1) (a) (b) ... 24 3.2 (2) (a) (b) ... 25 3.3 ... 38 3.4 ... 39 3.5 ... 39 3.6 ... 43 3.7 ... 44 3.8 (I) ... 46 3.9 (I) ... 46 4.1 ... 61 4.2 ... 62 4.3 ... 62 4.4 ... 64 4.5 ... 65 4.6 (II) ... 72 4.7 (II) ... 72 5.1 (I) ... 77 5.2 (I) ... 80 5.3 (II) ... 84 5.4 (II) ... 87 5.5 (I) (II) ... 88 5.6 (I) ... 88 5.7 (I) ... 89 5.8 (II) ... 89

viii 1.1 |Vgs| (fT) ... 1 1.2 ... 2 2.1 ... 3 2.2 ... 3 2.3 ... 4 2.4 ... 4 2.5 ... 5 2.6 ... 5 2.7 |Vgs| (fT) ... 6 2.8 |Vgs| (fT) ... 7 2.9 (2) ... 8 2.10 - ... 10 2.11 - ... 11 2.12 - ... 12 2.13 - ... 13 2.14 - ... 14 2.15 - ... 15 3.1 ( Vin) .... 17 3.2 (I) ... 18 3.3 ... 19 3.4 ... 20 3.5 ... 21 3.6 ... 21 3.7 Vboost ... 22

ix 3.8 ... 23 3.9 N ... 23 3.10 (a) (b) ... 24 3.11 ... 25 3.12 (Phase 1) ... 26 3.13 ... 26 3.14 X Vx.Vy ... 28 3.15 X ... 29 3.16 ... 30 3.17 - Equalize ... 32 3.18 -P ... 32 3.19 ... 34 3.20 N ... 34 3.21 -DP.DN ... 35 3.22 M1 ... 36 3.23 OUTP.OUTN - ... 38 3.24 OUTP1.OUTN1 - ... 38 3.25 OUTP.OUTN OUTP1.OUTN1 - ... 39 3.26(a)(b) CLK CLKd ... 40 3.26(c)(d) CLK CLKd ... 41 3.27 (I) ... 42 3.28 ... 42 3.29 ... 43 3.30 (I) ... 45 4.1 [1][2] ... 47 4.2 (II) ... 48 4.3 ... 49

x 4.4 ... 50 4.5 ... 51 4.6 ... 51 4.7 ... 52 4.8 (Phase 1) ... 53 4.9 ... 54 4.10(a)(b) Vdd=0.6V, X Vx.Vy ... 55 4.10(c)(d) Vdd=0.9V, X Vx.Vy ... 56 4.11 X ... 57 4.12 ... 58 4.13 -P ... 59 4.14 OUTP.OUTN - ... 60 4.15 OUTP1.OUTN1 - ... 61 4.16 - ... 61 4.17 (II) ... 62 4.18 ... 63 4.19 ... 64 4.20 ... 66 4.21 ... 67 4.22 ... 68 4.23 ... 68 4.24 (level shifter) ... 69 4.25 SR (SR latch) ... 69 4.26 (output buffer) ... 69 4.27 D (D-flip flop) ... 70

4.28 (Current Mode Logic, CML) ... 70

xi

5.1 ... 73

5.2 (Bit Error Rate, BER) ... 74

5.3 ... 75 5.4 ... 75 5.5 ... 76 5.6 ... 77 5.7 ... 78 5.8 (I) ... 78 5.9 (I) ... 79 5.10 (I) ... 79 5.11 (I) ... 80 5.12 (I) ... 80 5.13 (I) ... 82 5.14 (I) ... 82 5.15 (I) ... 83 5.16 (I) ... 83 5.17 ... 85 5.18 (II) ... 86 5.19 (II) ... 86 5.20 (II) ... 87 5.21 (II) ... 87 5.22 (II) ... 89 5.23 (II) ... 89 5.24 (II) ... 90 5.25 (II) ... 90

1

1.1

(low supply voltage)

(high speed) 1.1 |Vgs| (|Vgs|=|Vds|) |Vgs| 1.1 |Vgs| (fT) (ADC) (comparator) (Flash ADC) 1.2 1.2

2 1.2 (latch) [1][2] [1][2] (SRAM) (comparator) (flip-flop)

1.2

3

2.1

[3] 2.1

0

in in

V

V

1

V

in

V

in

0

0 2.1 2.2 2.2 (amplifier) (latch) 1 0 (CLK) (dynamic comparator) (latch)

4

2.2

2.2.1

2.3 2.4

M1~M4 Mr1 Mr2 (reset) M_tail

0 (reset phase) M_tail

Mr1 Mr2 OUTN OUTP (Vdd)

1 (comparison phase) (regeneration

phase) Mr1 Mr2 M_tail M_tail

(triode region) M1~M4

2.3

5 M_tail (common-mode operation) 2.5 2.1 2.5 dd GSN GSP thN thP OVN OVP V V V V V V V ( 2.1) P (M3 M4) (regeneration) P M1~M4 (full swing) [4] M1 M2 M3 M4 2.6 2.6

6

2.3 2.4

Gm Go CL

V0 VOUT_X

2.4 V0 VOUT_X (tlatch)

OUT OUTP OUTN

V

V

V

( 2.2) OUT OUT m o L dV V G G C dt ( 2.3) 0exp , 0 0 m o OUT OUT L G G V t V t V V t t C ( 2.4) _ latch 0 ln OUT X , L L latch m o m o V C C t G G V G G ( 2.5) 2.5 (time constant) (Vov : overdrive voltage Vov =|Vgs|-|Vth|) 2.7 (fT) |Vds|=|Vgs| 2.7 |Vgs| (fT)

7 2.8 |Vgs| (fT) |Vgs| 0.6 |Vgs| |Vgs| 2.1 N P N P 2.1 2.7 thN thP th

V

V

V

( 2.6)

2

dd GSN SGP th OVN OVP

V

V

V

V

V

V

( 2.7) N P

8

2.2.2

[1] 2.9 B. Goll H. Zimmermann ISSCC’09

N P P N P 2.8 ~ 2.11 2.9 (2) 1,2 3,4

1. 2 :

_{dd GSN SDP}

NMOS M M

V

V

V

( 2.8) 3,4 1,2

1. 2 :

_{dd SDP th OVN}

NMOS M M

V

V

V

V

( 2.9) 5,6 3,4

3. 4 :

_{SDP SGP}

PMOS M M

V

V

( 2.10) 5,6 3,4

3. 4 :

_{SDP th OVP}

PMOS M

M

V

V

V

( 2.11)

9 M1~M4 Mr1~Mr4 (CLK=“0”. CLKB=“1”.CLKB CLK ) M_tail Mr1 .Mr2 OUTP.OUTN M5.M6 Mr3 .Mr4 FBP.FBN M3.M4 OUTP.OUTN N (M1.M2) P (M1.M2) 2.9 2.11 N P N ( - ) (VDS) P VSDP5,6 2.11 2.12 3,4

3. 4 :

_{dd th OVP}

PMOS M M

V

V

V

( 2.12) (CLK=“1”. CLKB=“0”) OUTP.OUTN FBP.FBN M_tail M1.M2 M3.M4 OUTP.OUTN Mr3.Mr4 M5.M6 OUTP.OUTN FBP.FBN M3.M4 FBN.FBP OUTP M6 FBN M3 OUTP OUTN M5 FBP M4 OUTN M3.M4 M1.M2 FBP.FBN

(offset voltage, VOS) (sensitivity)

FBP.FBN

P M3.M4

10

2.3

2.3.1

2.10 M5.M6

[5][6]

(input referred offset voltage)( )

(kickback noise) (current reuse) [2] 2.11

( 2.2.3)

0.65

2.10

11

-12

2.3.2

2.12 M5.M6

(cascade)

M_tail_in M_tail [7][8]

OUTNP OUTN M_tail

(input referred noise)( )

M_tail_L

M1

M2

M3

M4

CLK

CLK

CLK

_M

_r1

_M

_r2

M_tail

CLK

INN

M5

M6

INP

OUTN

OUTP

2.12 -[1] 2.13 0.6 M9.M10 M7 M8

13

-14

2.3.3

[9] 2.14 2007 M5.M6 M7.M8 M7.M8 M_tail DP.DN ( 2.3.2) M7.M8

M_tail_in M5.M6 (weak inversion)

gm/id

M_tail

M7.M8

-15

2.3.4

(signal dependent)

[10] 2.15 2008 [9]

(signal dependent)

-16

2.4

2.4.1

17

(I)

3.1

[1] 3.1 (delay time) ( 2.2.1) 0.6 ( 2.2.3) [1] 1.2 22 0.6 47 [2] (0.65 ) 3.1 ( Vin) VCo

18

3.2

(I)

3.2.1

2.6 3.1 N P 3.2 (boost) 2 O V N O V P d d t h V V V V ( 3.1) 2 O V N O V P d d th boo st V V V V V ( 3.2) 3.2 Ms1~Ms4 (CLK=“1”. CLKB=“0”.CLKB CLK ) Ms1~Ms4 OUTP(OUTN) OUTP1(OUTN1) Mr1.Mr2 (CLK=“0”. CLKB=“1”) Ms1~Ms4 OUTP1.OUTN1 M3.M4 OUTP.OUTN M1.M2 OUTP1.OUTN1 3.2 (I)

19 P OUTP.OUTN OUTP1.OUTN1 P N [9] N N OUTP1.OUTN1 P M3.M4

(deep triode region) OUTP.OUTN N

M1.M2 M1~M4

3.2.2

(Mr1.Mr2) Ms1~Ms4 OUTP.OUTN OUTP1.OUTN1 N P (OUTP.OUTN) (OUTP1.OUTN1) 3.3 3.3 dd

V

GSN SGP

I

SW

Z

SW

V

V

( 3.3)

2

OVN OVP dd th SW SW

V

V

V

V

I

Z

( 3.4)

20 boost SW SW

V

I

Z

( 3.5) 3.4 N P ZSW OUTP.OUTN OUTP1.OUTN1 3.4 3.4 (CLK=500MHz, Vdd=Vicm=0.6V,Vin=1mV) [7] (CLK=“0”. CLKB=“1”) (CLK=“1”. CLKB=“0”) N P |Vgs| (300 )

21

3.5 3.4

3.6

3.5

22 3.6 M1~M4 |Vgs| 470 |Vgs|( 300 ) 50% Ms1~Ms4 (transmission gate) Vboost Vboost M1~M4 3.7 Vboost Ms1~Ms4 PVT M1~M4 Ms1~Ms4 3.7 Vboost Vboost M1.M2 M3.M4 P M1.M2 M3.M4 Ms1~Ms4 N

23

3.2.3

(rising) (falling) 3.8 P (gm) P N (3:1) 3.8 P N OUTP.OUTN OUTP1.OUTN1 N OUTP.OUTN OUTP1.OUTN1 P 3.9 3.9 N

24

N

P OUTP1.OUTN1 P

3.10

3.1 ( VOUT=|VOUTP-VOUTN VOUT1=|VOUTP1-VOUTN1|)

3.10 (a) (b)

Delay of “ VOUT=300mV ” Delay of “ VOUT1=300mV ” Power

(a) 557 ps 601 ps 24 W (b) 453 ps 750 ps 23 W 3.1 (1) (a) (b) (300 ) 3.1 OUTP.OUTN 1.2 OUTP1.OUTN1 P OUTP1.OUTN1 3.2

Delay of “ VOUT1=200mV ” Delay of “ VOUT1=300mV ”

(a) 552 ps 601 ps

(b) 560 ps 750 ps

25

3.2.4

[6] (comparison phase) 3.11: (Phase 1) : Ms1~Ms4 M1~M4 M1~M4 OUTP.OUTN OUTP1.OUTN1 3.12 3.13 P (common mode) OUTP.OUTN Vx OUTP1.OUTN1 Vy Vx Vy<Vth M1~M4 Vthn=|Vthp|=Vth COUT OUTP.OUTN COUT1 OUTP1.OUTN1 3.6 3.7 3.11

26 3.12 (Phase 1) 0 _ _ _ OUT dd x OUT sw ave p ave C V V t I I ( 3.6) 1 0 _ 1 _ _ OUT y OUT sw ave n ave C V t I I ( 3.7) In. Ip. Isw In_ave.

Ip_ave. Isw_ave OUTP.OUTN Vx_mid=0.5×(Vdd+Vx) OUTP1.OUTN1

Vy_mid=0.5×(Vy) t0_OUT

t0_OUT1 OUTP.OUTN OUTP1.OUTN1

27 Vx Vy<Vth OUTP.OUTN OUTP1.OUTN1 3.13 3.8 2 3 2 1 2 1 1 1 dd x stable P dd y thp AP y N x thn AN x y NSW dd y thn AN V V I K V V V V V K V V V V V K V V V V ( 3.8) P N P N X( X= WMS3 / WM1 ) Vx.Vy 3.9 Vx Vy 3.10 3 1 MS M dd x y

W

X

W

V

V

V

( 3.9) 1 1 2 1 1 2 1 A y A x y A dd x A dd y V V X V V V V X V X V X V X X V V X ( 3.10) M1.M3 X 3.11 (TT corner) 3.14(a) 3.14(b) X

28 3 2 3 1 1 , 1 2 2 dd th dd th dd A A A V V V V V X V V V ( 3.11) Vx.VyFF corner Vx.VyTT corner Vx.VySS corner Vxsimulation Vysimulation

(a)

(b)

Vxmodel Vymodel 3.14 X Vx.Vy

29 3.15 X 3.5 X (TT corner) X 0.45 0.75 Vgs 0.45 0.75 X=0.45 (Phase 2 ) : Ms1~Ms4 M1~M4 M1~M4 M1.M2 M3.M4 M1.M2 |Vgs| 3.16 gmp.gmn M3.M4 M1.M2 gmswn N gop.gon M3.M4 M1.M2 gosw cp.cn OUTP.OUTN OUTP1.OUTN1 (cp=cgsn+ cgsswp+ cgdswn cn=cgsp+ cgsswn+ cgdswn) cgdl P N cgd (cgdl=cgdn+ cgdp) 3.12 3.15 OUTP.OUTN.OUTP1.OUTN1

30 3.16 1 1 1 1 OUTP: 0 OUTP OUTN OUTP OUTN mp P OUTP op gdl

OUTP mswn OUTP OUTP osw

d V V dV V g c V g c dt dt V g V V g ( 3.12) 1 1 1 1 OUTN: 0 OUTN OUTP OUTN OUTP mp P OUTN op gdl

OUTN mswn OUTN OUTN osw

d V V dV V g c V g c dt dt V g V V g ( 3.13) 1 1 1 1 1 OUTP1: OUTP OUTN OUTP OUTP mn n OUTP on gdl

OUTP mswn OUTP OUTP osw

d V V dV V g c V g c dt dt V g V V g ( 3.14) 1 1 1 1 1 OUTN1: OUTN OUTP OUTN OUTP mn n OUTN on gdl

OUTN mswn OUTN OUTN osw

d V V dV V g c V g c dt dt V g V V g ( 3.15) 3.16 3.17

31

1 1 1

OUTP OUTN OUT OUTP OUTN OUT

V V V V V V ( 3.16) 1 1 1 1 1 0 OUT OUT OUT OUT mp OUT op p gdl OUT OUT OUT OUT mn OUT on n gdl d V V dV V g V g c c dt dt d V V dV V g V g c c dt dt ( 3.17) OUT OUT m o L dV V G G C dt ( 2.3) 1 1 2 2 OUT mp on OUT mn op gdl p OUT gdl n OUT V g g V g g d c c V c c V dt ( 3.18) 3.17 2.3 3.18 2.3 VOUT (gmn -gop) (2 cgdl+ cp) VOUT1 (gmp -gon) (2 cgdl+ cn) VOUT VOUT VOUT1 P N M1~M4 Ms1~Ms4 (Phase 3 ) : M1~M4 (Reset Phase) M1~M4 Mr1.Mr2 (low impedance) (Equalize) 3.17

32 P ( 3.18) N OUTP.OUTN N 3.17 - Equalize 3.18 -P

33

3.2.5

: 1. 2. N P 3. : 1. 2. : 1. PVT

3.3

(I)

3.3.1

[9][10] ( 3.19) M2.M3 3.20 N I-V

34 3.19 3.20 N I-V Vgs 400 (exponential) Vgs 400 600 (square law) N (DP.DN) 3.21 M1 Vtail_in M2.M3 DP.DN DP.DN D) DP.DN M2.M3 D DP.DN 150 D M2.M3 M2.M3 Vtail_in M1 M1 Vtail_in

35 3.21 -DP.DN D DP.DN [10] P P N DP.DN P M1 Vtail_in M2.M3 DP.DN M1

36 3.22 M1 3.22 M1 M1 DP.DN M1 M2.M3 3.19 2 ,3 2,3 2 2 2,3 2,3 2,3 2,3 2 2 2 2 2,3 2 2 os D TH GS TH GS TH V W C V L _D V V V V W C L ( 3.19)

37 M2.M3 DP.DN M2.M3 M4.M5 M4.M5 DP.DN DP.DN M4.M5

3.3.2

N Ms1.Ms2 CLKB DP.DN CLKB OUTP.OUTN 3.23 M11 DP.DN M9.M10 M7.M8 P N OUTP1.OUTN1 3.24 M7.M8 M3.M4 OUTP.OUTN M7.M8 DP.DN CLKB CLK M11.M12 M9.M10 M7.M8 M11 3.3

38 3.23 OUTP.OUTN -3.24 OUTP1.OUTN1 -( VOUT=300mV) 629ps 420ps 26 W 27 W 3.3 OUTP.OUTN OUTP1.OUTN1 3.25 DP.DN OUTP.OOUTN M7_0.M8_0

39 OUTP.OUTN OUTP1.OUTN1 M1.M2 M7_1.M8_1 OUTP1.OUTN1 3.25 OUTP.OUTN OUTP1.OUTN1 -( VOUT=300mV) 420s 576ps 27 W 32 W 3.4 CLKB DP.DN Vos(1 ) 14mV 12mV 3.5 M7.M8

40 Ms3.Ms4 CLKd CLK 3.26(a)~(d) CLK CLKd 80ps 5% DP.DN (metastable) 40% 40ps~80ps

41

(c)

(d)

3.26(a)~(d) CLK CLKd 60ps variation ±20 ps variation variation M7.M8 3.27 CLK CLKd DP.DN 0.6 TT GHz

42

3.27 (I)

3.28

43 3.29 M_tail M8 M9 INN.INP 13fF 5fF 3.29 3.6 0.6 1.1GHz [3]

FoM FoM=[Speed × (Accuracy)2]/Power Accuracy

(Vdd/ Vos) FoM

Conventional comparator Proposed I Comparator

CLK rate 0.5GHz 1.1GHz Accuracy (Vdd/ Vos) 600/8.5 600/10 Power 17 W 34 W FoM 146.55 116.47 3.6 M1~M5 Mdn Mdp 3.20 _ _ 1 _ 2 2 2 2 os total os st os st V V V ( 3.20)

44 Conventional comparator Proposed I Comparator (w/ timing control) Proposed I Comparator (w/o timing control) Total input referred offset

( Vos_total)

8.5mV 10mV 14mV

Input referred offset of 1st stage ( Vos_1st)

5.5mV 5.5mV 5.5mV

Input referred offset of 2nd stage ( Vos_2nd)

5mV 8mV 11mV

45

3.4

TSMC 65nm 1P9M 3.30 common centroid layout 3.30 (I)

46 1.2 0.6 (corner) 3.8 Ms3.Ms4 0.9 (corner) 3.9 Pre-simulation Post-simulation corner SS TT FF SS TT FF Vdd (V) 0.6 0.6 0.6 0.6 0.6 0.6 CLK rate (GHz) 0.6 1.1 1.7 0.4 0.8 1.1 Vicm (V) 0.6 0.6 0.6 0.6 0.6 0.6 Vos-1 (mV) 12 10 11 12 10 11 Noise-1 (mV) 1.1 0.8 0.9 1 0.9 0.9 Energy/decision (fJ)* 30 34 44 35 42 55 3.8 (I) Pre-simulation Post-simulation corner SS TT FF SS TT FF Vdd (V) 0.9 0.9 0.9 0.9 0.9 0.9 CLK rate (GHz) 3.5 4 4.6 2.5 3 3.2 Vicm (V) 0.9 0.9 0.9 0.9 0.9 0.9 Vos-1 (mV) 12 10 10 12 10 10 Noise-1 (mV) 1.1 0.8 0.9 1 1 1 Energy/decision (fJ)* 89 107 129 104 122 146 3.9 (I) * 1mV

47

(II)

4.1

[1][2] 4.1 N P [1][2] N FBP.FGN P N P 4.1 [1][2]

48

4.2

(II)

4.2.1

[1][2] N N ( 4.1 ) P ( 4.1 ) N P 4.2 (II) 4.2 (II) OUTP.OUTN OUTP1.OUTN1 M5.M6 OUTP1.OUTN1 OUTP.OUTN M3.M4 N ? 4.3 OUTP M1.M2 N OUTN M5.M6 OUTP.OUTN OUTP1 OUTN1 OUTP.OUTN M7.M8

49 P OUTP1.OUTN1 OUTP1 OUTN1 OUTP.OUTP1 M2.M6 M4.M8 OUTP.OUTP1 OUTN.OUTN1 ”Cross-Coupled Latches” 4.3 OUTP.OUTN OUTP1.OUTN1 |Vgs| OUTP.OUTN OUTP1.OUTN1

4.2.2

(Mr1.Mr2) MNSW.MPSW N-type ( M1.M2 N

N-type P-type) M1.M2 OUTP.OUTN

M3.M4 OUTP.OUTN

P-type OUTP1.OUTN1

4.4 MNSW.MPSW

50 N P Vgs Vds N P Vgs 4.4 1 3 GSN dd SWN SDP

V

V

V

V

( 4.1) 5 3 GSN dd SDP

V

V

V

( 4.2) 7 5 SGP SWP DSN

V

V

V

( 4.3) 3 5 SGP dd DSN

V

V

V

( 4.4) MNSW.MPSW N P |Vgs| MNSW.MPSW MNSW 2 M2 MPSW 2 M7 MNSW.MPSW |Vds| 4.5 N-type P-type M9~M13 M1.M2.M5.M6 10% 4.6 (CLK=500MHz, Vdd=Vicm=0.6V,Vin=1mV)

51

4.5

52 4.6 OUTP.OUTN OUTP1.OUTN1 OUTP.OUTN N OUTP1.OUTN1 P

4.2.3

[6] (comparison phase) 4.7: 4.7

53

(Phase 1) :

M1.M2.M7.M8 M3.M4.M5.M6

OUTP.OUTN OUTP1.OUTN1

4.8 4.9

(common mode) OUTP.OUTN

Vx OUTP1.OUTN1 Vy In Ip In1 Ip1 M3.M4.M5.M6 M1.M2.M7.M8 4.8 (Phase 1) 0 _ _ _ OUT dd x OUT n ave p ave C V V t I I ( 4.5) 1 0 _ 1 1 _ 1 _ OUT y OUT p ave n ave C V t I I ( 4.6) In. Ip. In1. Ip1 4.5

4.6 In_ave. Ip_ave. In1_ave. Ip1_ave OUTP.OUTN Vx_mid=0.5×

(Vdd+Vx) OUTP1.OUTN1 Vy_mid=0.5×(Vy)

t0_OUT t0_OUT1 OUTP.OUTN OUTP1.OUTN1

4.9 4.7

P N

54 4.9 N-type P P-type P (1:X) N-type N P-type N (1:X) 4.9 _ _ 1 1 stable X p n stable Y p n I I I I I I ( 4.7) _ _ , , SWN dd SWP dd dd x y stable X stable Y V V V V V V V I I ( 4.8) 4.8 4.9 X M3.M5 X 4.10 2 ₂ _ 3 1 2 ₂ _ 7 5 1 1 1 1 dd x x SWN stable X P dd y thp N x SWN thn AP AN SWP y y stable Y P SWP y thp N x thn AP AN V V V V I K V V V K V V V V V V V V I K V V V K V V V V ( 4.9)

55 2 2 1 1 dd x x th A dd dd y dd dd y th A V V V V V X V V V V V V V V ( 4.10) 10% 4.13(a) 0.6 (TT corner) (b) 0.6 Vxmodel Vymodel Vxsimulation Vysimulation Vx.VyFF corner Vx.VyTT corner Vx.VySS corner

(a)

(b)

4.10(a)(b) Vdd=0.6V, X Vx.Vy

56 Vxmodel Vymodel Vxsimulation Vysimulation Vx.VyFF corner Vx.VyTT corner Vx.VySS corner

(c)

(d)

4.10(c)(d) Vdd=0.9V, X Vx.Vy X Vx.Vy 0.6 X 0.8~1.1 0.9 X 0.7~0.8 4.11 X VX M1.M7 X 1.1 M3.M5 M1.M7 X M3.M5 M1.M7 X=1

57 4.11 X (Phase 2 ) : M1.M2.M7.M8 M3.M4.M5.M6 M1~M8 OUTP.OUTN OUTP.OUTN OUTP1.OUTN1 M1.M2.M5.M6 M1.M2 |Vgs| M5.M6 M1.M2 |Vgs| 4.12 4.11 4.12 gmp7.gmn1 M7.M8 M1.M2 gmp3.gmn5 M3.M4 M5.M6

gon.gon1 OUTP.OUTN OUTP1.OUTN1

(go=gop3+gon1 go1=gop7+gon5)

cL.cL1 OUTP.OUTN OUTP1.OUTN1

(cL=cgsn1+ cgsn5 cL1=cgsp3+ cgsp7)

cgd P N cgd

VOUT=VOUTP-VOUTN VOUT1=VOUTP1-VOUTN1

i1 i2 i1= i2

58 4.12 1 1 1 3 1 1 3 5 1 1 7 5 1 7 3 5 1 1 1 4 4 1 2 OUT OUT g OUTP

OUTN mn OUTN mp L gdn OUTP o OUTN OUTP

gdp gdn

OUTN

dp gdn

OUTP mp OUTP mn L gdp OUTN o

d V V dV i V g V g c c V g dt d V V c c dt dV V g V g c c d c t V d g c t ( 4.11) 1 3 5 2 1 1 3 1 1 3 5 1 1 7 5 1 7 1 1 4 4 1 2 OUTN

OUTP mn OUTP mp L gdn OUTN o OUTN OUTP gdp gdn OUTP OUTN mp OUTN mn L gd OUT OUT gdp gd p OUT n P o dV i V g V g c c V g dt d V V c c dt dV V g V g d V V c c dt c c V g dt ( 4.12) 1 1 1 3 3 5 1 1 1 1 1 3 3 5 1 7 4 4

OUT OUT OUT

OUT mn o OUT mp gdp gdn L gdn

OUT OUT OUT

OUT mn o OUT mp gdp gdn L gdp d V V dV V g g V g c c c c dt dt d V V dV V g g V g c c c c dt dt ( 4.13) 1 1 3 1 1 4 7 2 3 2 5 4 1 2 3 2 5 OUT OUT mn mp o OUT L gdp gdp gdn OUT L gdn gdp gdn V V g g g d V c c c c V c c c c dt ( 4.14) 2.3 4.14 VOUT (gmn1+gmp3 -go) (cL+4 cgdn1l+ 2(cgdp3+cgdn5)) VOUT1 (gmn1+gmp3 -go) (cL1+4 cgdp7l+ 2(cgdp3+cgdn5)) VOUT VOUT1

59 M1~M8 M3.M4.M5.M6 (Phase 3 ) : M1~M8 (Reset Phase) P ( 4.13) N OUTP.OUTN N 4.13 -P

4.2.4

- Cross-Coupled Latches

: 1. 2. 3.

60

4.3

(II)

OUTP.OUTN OUTP1.OUTN1 4.14 4.15 OUTP.OUTN OUTP1.OUTN1 M9.M10 DP.DN CLKB CLK M11.M12 M11.M12 M9.M10 M13 4.1 (CLK=0.8GHz,Vdd=Vicm=0.6V,Vin=1mV)

( VOUT=|VOUTP-VOUTN VOUT1=|VOUTP1-VOUTN1|)

-61 4.15 OUTP1.OUTN1 -1( VOUT=300mV) 504ps 362ps 2( VOUT1=300mV) 534ps 410ps 39 W 46 W 4.1 OUTP1.OUTN1 OUTP.OUTN CLKB DP.DN 4.16 4.16

-62 1( VOUT=300mV) 362ps 322ps 2( VOUT1=300mV) 410ps 361ps 46 W 47 W 4.2 4.3 Vos(1 ) 22mV 10mV 4.3 40ps 4.17 4.18 CLK 1.3GHz 4.17 (II)

63 M9.M10 M11.M12 M13 4.18 4.19 INN.INP 13fF 5fF

64 M_tail M8 M9 MPSW M8_1 M9_1 MNSW M6_0 M7_0 X=1 4.19 4.4 0.6 1.6GHz

Conventional comparator Proposed I Comparator

CLK rate 0.5GHz 1.6GHz

Accuracy (Vdd/ Vos) 600/8 600/10

Power 20 W 40 W

FoM 140.63 144

65 M1~M5 4.15 _ _ 1 _ 2 2 2 2 os total os st os st V V V ( 4.15)

Conventional comparator Proposed II Comparator Total input referred offset

( Vos_total)

8.5mV 10mV

Input referred offset of 1st stage ( Vos_1st)

5.5mV 5.5mV

Input referred offset of 2nd stage ( Vos_2nd) 5mV 8mV 4.5

4.4

P (Vdd-|Vth|) N (|Vth|) 4.20

66 4.20 P N N P 4.21 MN.MP N MCLK CLK MN.MP

67 4.21 N P N P N P N P 4.22 OUTP1 MP1 MN1 OUTPB OUTN1 MP2 MN2 4.23 (level shifter) SR (SR latch) 4.24 4.25

(output buffer) D (D-flip flop)

68

4.22

69

4.24 (level shifter)

4.25 SR (SR latch)

70

4.27 D (D-flip flop)

71

4.5

TSMC 65nm 1P9M 4.29 common centroid layout 4.29 (II)

72 1.2 0.6 (corner) 4.4 0.9 (corner) 4.5 Pre-simulation Post-simulation corner SS TT FF SS TT FF Vdd (V) 0.6 0.6 0.6 0.6 0.6 0.6 CLK rate (GHz) 0.8 1.6 2 0.4 1 1.5 Vicm (V) 0.6 0.6 0.6 0.6 0.6 0.6 Vos-1 (mV) 11 10 11 12 10 11 Noise-1 (mV) 1 0.9 0.8 1 0.9 0.9 Energy/decision (fJ)* 35 40 53 42 49 60 4.4 (II) Pre-simulation Post-simulation corner SS TT FF SS TT FF Vdd (V) 0.9 0.9 0.9 0.9 0.9 0.9 CLK rate (GHz) 3.5 4 4.6 2.8 3.1 3.4 Vicm (V) 0.9 0.9 0.9 0.9 0.9 0.9 Vos-1 (mV) 11 10 10 11 10 10 Noise-1 (mV) 1 0.9 0.8 1 1 0.9 Energy/decision (fJ)* 112 130 151 136 153 177 4.5 (II) * 1mV

73

5.1

5.1 (I) (I) (II) 5.1

74

5.2

(Bit Error Rate, BER)

(Bit Error Rate, BER) 5.2 Agilent N4901B

(Serial BERT) (PRBS 27-1)

5.2 (Bit Error Rate, BER)

5.3

Agilent 16902B (Logic analysis system)

Agilent

E8257D( )

5.4

0 1 1

75

5.3

76 5.4 5.5 |3 | 99.73002% (1-99.73002%=2.6998×10-3) 2.7×10-3 |3 | |1 |2 |2 | 4.55×10-2 |1 ( ) |1 5.5 : (DC) (AC) 0 1 1 0 5.6

77 5.6 : 5.4 50% |1 1 |3 2.7×10-3 0.35V~0.45V 0.4V~0.5V 0.4V 0.4V

78

5.3

(I)

5.3.1

5.7 5.8 5.7 5.8 (I)

79

5.9 (I)

80

5.11 (I)

81

5.9 5.10 5.11 5.12

PRBS 27-1 FF corner

FF corner 5.1 FF

Post-sim Measurement result CMOS Process 65nm Vdd (V) 0.6 CLK rate (GHz) 1.1 1 Vicm (V) 0.6 0.4 0.6 Offset Vos (mV) 11 (50 amples) 6 (20 amples) 11 (20 amples) Noise noise (mV) 1 0.65 1.1 Sensitivity (mV) @BER=10-9 NA 3 4.5 Energy/decision (fJ) 44 @vin=50mV 55 @vin=1mV 35 @vin=50mV 38 @BER=10-9 38 @vin=50mV 40 @BER=10-9 Comparator area ( m2) 200 5.1 (I)

82

5.3.2

5.13 (I)

83

5.15 (I)

84

5.13 5.14 5.15 5.16

4 PRBS 27-1 FF corner

FF corner 5.2 FF

Post-sim Measurement result CMOS Process 65nm Vdd (V) 0.9 CLK rate (GHz) 3.2 3.1 Vicm (V) 0.9 0.6 0.9 Offset Vos (mV) 10 (50 amples) 8.5 (20 amples) 8.5 (20 amples) Noise noise (mV) 1 0.45 0.65 Sensitivity (mV) @BER=10-9 NA 3.5 4.8 Energy/decision (fJ) 128 @vin=50mV 146 @vin=1mV 110 @vin=50mV 120 @BER=10-9 111 @vin=50mV 121 @BER=10-9 Comparator area ( m2) 200 5.2 (I)

85

5.4

(II)

5.4.1

5.17 5.17

86

5.18 (II)

87

5.20 (II)

88

5.18 5.19 5.20 5.21

PRBS 27-1 FF corner

FF corner 5.3 FF

Post-sim Measurement result CMOS Process 65nm Vdd (V) 0.6 CLK rate (GHz) 1.5 1.3 Vicm (V) 0.6 0.4 0.6 Offset Vos (mV) 11 (50 amples) 8.5 (20 amples) 7.5 (20 amples) Noise noise (mV) 1 0.5 0.5 Sensitivity (mV) @BER=10-9 NA 6 4.2 Energy/decision (fJ) 55 @vin=50mV 60 @vin=1mV 45 @vin=50mV 49 @BER=10-9 45 @vin=50mV 49 @BER=10-9 Comparator area ( m2) 265 5.3 (II)

89

5.4.2

5.22 (II)

90

5.24 (II)

91

5.22 5.23 5.24 5.25

PRBS 27-1 FF corner

FF corner 5.4 FF

Post-sim Measurement result CMOS Process 65nm Vdd (V) 0.9 CLK rate (GHz) 3.4 3.3 Vicm (V) 0.9 0.6 0.9 Offset Vos (mV) 10 (50 amples) 6 (20 amples) 6 (20 amples) Noise noise (mV) 0.9 0.3 0.45 Sensitivity (mV) @BER=10-9 NA 3.3 3.4 Energy/decision (fJ) 148 @vin=50mV 177 @vin=1mV 124 @vin=50mV 143 @BER=10-9 124 @vin=50mV 143 @BER=10-9 Comparator area ( m2) 265 5.4 (II)

92 5.5 30% 20% 20% GHz 5.6~ 5.8 5.5 (I) (II) 5.6 (I)

93

5.7 (II)

94

65nm

95

[1] B. Goll and H. Zimmermann, "A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47 W at 0.6V," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2009, pp.328-329,329a

[2] B. Goll and H. Zimmermann, "A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65V," IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 56, pp. 810-814, 2009.

[3] Jieh-Tsorng Wu, Data-Conversion Integrated Circuits, 2010

[4] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.

[5] Tsuguo Kobayashi, et al., "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low–Power Architecture," IEEE Journal Solid-State Circuits,, vol. 28, pp. 523-527, Apr. 1993.

[6] B. Wicht, et al., "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier," IEEE Journal Solid-State Circuits,, vol. 39, pp. 1148-1158, July 2004.

[7] B. Goll and H. Zimmermann, "A Low-Power 4GHz Comparator in 120nm CMOS Technology with a Technique to tune Resolution," in Proceedings of the 32nd European Solid-State Circuits Conference,, 2006, pp. 320-323

[8] C.-H. Chan, et al., "A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS," in Solid-State Circuits Conference, 2011. ASSCC '11. IEEE Asian, 2011, pp. 233-236.

[9] D. Schinkel, et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time" in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2007, pp. 314-315.

[10] M. Miyahara, et al., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," in Solid-State Circuits Conference, 2008. ASSCC '08. IEEE Asian, 2008, pp. 269-272.

[11] L. Kong, et al., "A Multi-GHz Area-Efficient Comparator with Dynamic Offset Cancellation," in IEEE Custom Integrated Circuits Conference,, 2011, pp. 1-1.

[12] M. Miyahara and A. Matsuzawa, "A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique," in Solid-State Circuits Conference, 2009. ASSCC '09. IEEE Asian, 2009, pp. 233-236.

96

[13] G.Van der Plas, et al., "A 0.16pJ/Conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2006, pp. 556-567.

[14] M. Miyahara, et al., "A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC," in Solid-State Circuits Conference, 2010. ASSCC '10. IEEE Asian, 2010, pp. 1-4. [15] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000 [16] B.-W. Chen, et al., "A 6-Bit, 1.2-GS/s ADC with Wideband THA in 0.13 m

CMOS," in Solid-State Circuits Conference, 2008. ASSCC '08 IEEE Asian, 2008, pp. 381-384.

[17] Pedro M. Figueiredo and João C. Vital, "Kickback Noise Reduction Techniques for CMOS Latched Comparators," IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 53, pp. 541-545, 2006.

[18] A. Matsuzawa, "Energy efficient ADC design with low voltage operation," in ASIC(ASICON), 2011. ASIC '11. IEEE International Conference,, 2011, pp. 508-511.