Low-power low-voltage reference using
peaking current mirror circuit
M.-H. Cheng and Z.-W. Wu
A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 mm CMOS technology, achieving the minimum supply voltage 1.4 V, the refer-ence voltage around 580 mV, the temperature coefficient 62 ppm=C,
the supplied current 2.3 mA, and the power supply noise rejection ratio of 84 dB at 1 kHz.
Introduction: Since the bandgap reference was proposed in[1], many bandgap reference circuits have been designed to decrease the temperature sensitivity, the power dissipation, and the supply voltage
[2–4]. Recently, particular research on generating a low-power and low-voltage reference was based on exploiting the properties of devices operated in the subthreshold region [5]. To obtain a low-power consumption, the operated current should be modest. The peaking circuit[2, 6, 7], with the MOSFETs operated in the weak-inversion region, has been recognised as a useful low-current refer-ence. This Letter exploits the peaking circuit to realise a low-power low-voltage reference source. The proposed reference circuit merely consists of a self-biased peaking current source with a series resistor; thus it is easy to design, simple to realise and can meet the low-power, low-voltage requirement.
Circuit configuration: The proposed reference circuit is depicted in
Fig. 1. The elements M3, M4and R1constitute the peaking current
source, while the elements M1and M2, connected in a current mirror,
serve for realising the function of self-biasing. The MOSFETs M3, M4
are designed to operate in the subthreshold region such that the required low supply voltage, low power consumption, and low reference voltage output can be achieved. The M1, M2mirror is designed to make the drain
currents of M3and M4operate in the peaking relation, then the voltage
across R1is proportional to the absolute temperature (PTAT). Hence,
the resistor ratio R2=R1can be used to compensate for the variation of
the gate-source voltage of M3with respect to the temperature. A steady
reference voltage output, Vout, is therefore obtained.
Fig. 1 Schematic diagram of reference voltage
Circuit analysis: For an n-MOSFET of aspect ratio W=L operated in the subthreshold region, its drain current is given by[2],
ID¼ W LqXDnnp0exp VGS=N þ C VT 1 exp VDS VT ð1Þ where X denotes the thickness of the depletion layer, Dnthe electron
diffusion constant, np0 the electron density in the p-type silicon,
VT¼kT=q the thermal voltage, and N, C are constants. Denote
Ki¼(W=L)i, I0¼qXDnnp0 exp(C=VT), the drain currents of M3, M4
can be expressed as ID3¼K3I0exp VGS3 NVT ; ID4¼K4I0exp VGS4 NVT ð2Þ
Note that the factor exp(VDS=VT) is neglected because in the circuit
the operated drain-source voltage of each MOSFET is much greater than 3VT. The relation between two currents, therefore, is
ID4¼ID3 K4 K3 exp VGS4VGS3 NVT ð3Þ The circuit configuration, as shown, constrains the difference between two gate-source voltages of M3, M4in a relation given by
VGS4VGS3¼ ID3R1 ð4Þ
Substituting (4) into (3), we obtain ID4¼ID3 K4 K3 exp ID3R1 NVT ð5Þ The peaking circuit is designed such that ID4is at its peaking value. It
can be achieved by zeroing the derivative of ID4with respect to ID3
using (5), yielding the design condition to maintain the current peaking ID3R1¼NVT ð6Þ
If the condition is satisfied, then the drain currents of M3, M4, via (5),
are related by
ID4¼ID3
K4
K3
e1 ð7Þ
Hence, the self-biasing mirror is designed to make ID3, ID4satisfy the
relation in (7); consequently, the peaking condition (6) is maintained. For example, if K4=K3¼e, then setting K1¼K2will make ID3¼ID4and
the peaking condition is satisfied.
The voltage across R1under the peaking condition, as shown by (6),
is therefore PTAT. Using this property, we obtain the reference voltage output Voutas follows
Vout¼ID3R2þVGS3¼
R2
R1
NVTþVGS3 ð8Þ
Note that the drain current of M3is also PTAT. It has been known[2]
that for an n-MOSFET with a PTAT drain current, the voltage VGS3with
respect to the temperature can be expressed as
VGS3¼A0þA1T þ A2T ln T ð9Þ
where the constants A0, A1 and A2 are dependent on the process
technology. Hence, the resistor ratio R2=R1can be designed to make
the temperature coefficient of Voutequal zero at a selected temperature
T0; i.e. which yields
R2
R1
¼ q
kNðA1þA2þA2ln T0Þ ð10Þ Table 1: Element dimensions and values
Element Value M1 4=16 M2 4=16 M3 32=16 M4 79.04=16 R1 50 kO R2 58 kO Cout 4.5 pf
Design example: An example design has been implemented in standard 0.35 mm CMOS technology for verification. In this design, we let ID4¼ID3by setting the dimensions of M1, M2identical to each
other in the mirror circuit. Thus, using (7) we obtain K4=K3¼e, the
ratio between the aspect ratio of M3and that of M4is determined.
Since the process technology has the parameter N at about 2.06, we set R1¼50 kO such that the drain current of M3at room temperature,
by (6), is approximately equal to 1 mA. We obtain the parameters A0,
A1, A2using the curve-fitting technique via the least-squares method
from the SPICE post-simulation data. Then, setting the nominal temperature T0¼300K (27C) and using (10), we have
R2¼58 kO. The designed aspect ratios of MOSFETs and other
element values are listed inTable 1. Note that small aspect ratios of M1, M2are chosen to obtain a higher output impedance and yield a
better performance of line regulation. The required area of the chip is about 0.126 mm2.
The reference output voltages of six test chips have been measured with the supply voltages Vssset at 1.4, 1.7, 2, 2.3, 2.6, 2.9, 3 or 3.3 V and
temperatures at 0, 27, 43, 57 or 70C. The measured reference output
voltages against temperatures with Vssof 1.4, 2, 3 V are shown inFig. 2.
InFig. 3, the output voltages against supply voltages with the tempera-ture at 0, 27, 57C are depicted. The nominal specifications are listed in Table 2.
Fig. 2 Reference voltage Voutagainst temperature T at various supply
voltages
Fig. 3 Reference voltage Vout against supplied voltage Vss at various
temperatures
Table 2: Specifications Specification Value Supplied current 2.3 mA at Vss¼2 V
Minimum operating voltage 1.4 V Output voltage 0.579 V at Vss¼2 V
PSRR 84 dB at 1 kHz Line regulation 3.9 mV=V at 27C
Temperature coefficient 62 ppm=C at V ss¼2 V
Conclusion: A low-power, low-voltage reference circuit using the peaking circuit with MOSFETs operated in the subthreshold region is reported. The reference output voltage is around 580 mV, the operated current 2.3 mA, and the minimum supply voltage 1.4 V. This circuit is easy to design, simple to realise, and suitable for use in low-power, low-voltage applications.
Acknowledgments: This work was supported by the National Science Council, Taiwan, under NSC92-2213-E-009-084. The authors wish to thank the National Chip Implementation Center (CIC) for chip fabrication.
#IEE 2005 7 February 2005
Electronics Letters online no: 20050316 doi: 10.1049/el:20050316
M.-H. Cheng and Z.-W. Wu (Department of Electrical and Control Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 30010, Taiwan)
E-mail: [email protected] References
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