A process for high yield and high performance carbon nanotube field effect transistors

A process for high yield and high performance carbon nanotube field

effect transistors

Tseng-Chin Lee

_{, Bing-Yue Tsui}

_{, Pei-Jer Tzeng}

_{, Ching-Chiun Wang}

_{, Ming-Jinn Tsai}

Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC b

Electronics and Opto-Electronics Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, ROC

a r t i c l e

i n f o

Article history:

Received 13 December 2009

Received in revised form 7 January 2010 Available online 5 March 2010

a b s t r a c t

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candi-dates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low sub-threshold swing of 139 mV/dec, high transconductance of 1.27lS, and high Ion/Ioffratio of 106can be eas-ily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.

Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction

In recent years, to further scale down the geometry of field ef-fect transistors and improve device performance, carbon nanotube field effect transistors (CNTFETs) have attracted much attention as a candidate for beyond-Si technology[1–3]. The diameter of a sin-gle-wall carbon nanotube (SWCNT) ranges from 1 nm to 2 nm. The quasi one-dimensional structure enhances carrier mobility dra-matically. According to literatures, the intrinsic mobility of a semi-conducting SWCNT can exceed 100,000 cm2_V 1_s 1 _{at room}

temperature and some high performance CNTFETs have been dem-onstrated[4–6].

Most of the CNTFETs studied so far have adopted a top-gate structure, as shown in Fig. 1a [5,6]. The top-gate CNTFET is a SWCNT-first and gate-last process. The SWCNT channel can be fab-ricated by either in situ growth or spin-coating process. For the in situ growth of SWCNT, it is still hard to control the chirality and the number of SWCNT across between source and drain. In addition, the source/drain (S/D) contact metal is usually patterned by lift-off process instead of dry etching process, and the gate dielectric must be deposited by atomic-layer deposition technique to obtain good surface coverage on the SWCNTs. Therefore, the most apparent drawbacks of the conventional top-gate CNTFETs are: (1) high gate leakage current caused by the source/drain lift-off process at the gate to S/D overlap region and (2) low manufac-turing yield due to the SWCNTs spin-coating process.

To further reduce the gate leakage current at the gate to S/D overlap region and increase the manufacturing yield of the CNT-FETs, we proposed a gate-first local bottom-gate (LBG) process. The gate electrode is patterned by dry etching process instead of the typically used lift-off process. The schematic device structure is shown inFig. 1b. After process optimization, the LBG-CNTFETs can achieve high yield and high performance goals using a simple SWCNTs spin-coating process.

2. Device fabrication

The starting material was a silicon substrate covered by a 15 nm thick pad oxide (SiO2) formed by thermally oxidation and a 150 nm

thick silicon nitride (Si3N4) formed by low-pressure chemical vapor

deposition (LPCVD). Two kinds of LBG stacks were prepared, one is n+ _{poly-Si(60 nm)/Al}

2O3(10 nm) and the other is TiN(40 nm)/

Si3N4(30 nm). The 60 nm thick n+poly-Si gate was deposited by a

in situ phosphorus doped LPCVD process followed by a 900 °C ra-pid-thermal annealing for 20 s to activate the dopants. The 40 nm thick TiN gate electrode was deposited by a sputtering sys-tem. The poly-Si local bottom-gate was patterned by a dry etching process to form individual local bottom-gate electrodes, while the TiN local bottom-gate was patterned by a lift-off process. In order to control the thickness of these two LBG stacks to 70 nm accu-rately, a 10 nm thick Al2O3 gate dielectric was deposited by an

atomic-layer deposition (ALD) system, while a 30 nm thick Si3N4

was deposited by a plasma-enhanced chemical vapor deposition (PECVD) process.

0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved.

doi:10.1016/j.microrel.2010.01.008

*Corresponding author. Tel.: +886 3 5712121x54127; fax: +886 3 5724361. E-mail addresses:[email protected],[email protected](T.-C. Lee).

Microelectronics Reliability 50 (2010) 666–669

Contents lists available atScienceDirect

Microelectronics Reliability

The CNTs were commercially available Carbolex AP-grad SWNTs which were grown by arc-discharge technique. The average diameter of the SWCNTs is 1.4 nm, which is calculated from the ra-dial breathing mode (RBM) of a high-resolution Raman spectros-copy [7]. For the spin-coating process, a 0.25 mg CNT powder was dissolved in 40 ml dimethylformamide (DMF) solution fol-lowed by a sonication for 24 h. The solution was then spun onto the substrates by a two-step process. The first step was at 500 rpm for 10 s and the second step was at 2500 rpm for 60 s. The purpose of the first lower rotation speed step is to distribute SWCNTs on the substrate uniformly. The rotation speed of the sec-ond step depends on the step height of the LBG stacks and will be explained later. After SWCNTs coating, the substrates were then placed on a hot plate at 150 °C for 10 min to desorb the DMF mol-ecules from substrates. Three kinds of source/drain contact metal, titanium (Ti), nickel (Ni), and chrome (Cr), were deposited by a sputtering system and were patterned by a lift-off process. The gate to S/D overlap length to modulate the schottky barrier at source/drain contact region was designed to 50 nm on each side. Finally, a post-deposition annealing (PDA) process in a high vac-uum system at 600 °C for 180 s was performed to form good ohmic contact between source/drain metal and CNTs.

3. Results and discussion

Fig. 2 shows the typical transfer characteristics (Id Vg) at

Vd= 0.1 V of the LBG-CNTFETs with a lift-off TiN gate. High gate

leakage current of 5  10 8_{A is observed at V}

g= 4 V. This high

leakage current can be explained by the cross-sectional scanning electron microscopic (SEM) image as the inset in Fig. 2. At the LBG edge, a sharp convex corner exits because of the tapered shape of the photoresist in a lift-off process. The photoresist sidewall will be covered by TiN film and the TiN film will be teared-open as the photoresist was dissolved by acetone. The convex corner can be as high as several hundred nanometers. This sharp convex corner re-sults in a non-conformal gate dielectric deposition, which in turn results in higher gate leakage current due to the gate dielectric

thinning and local electric field enhancement. Furthermore, the high and sharp convex corner will block CNTs during the spin-coat-ing process. Lots of CNTs will accumulate at gate edge to result in leakage path between source and drain. The high turn-off current shown in Fig. 2 is the result of the leakage path. This problem can be relaxed by utilizing reentrant shape or T-shape photoresist. However, the reentrant shape thick photoresist are difficult to form fine pattern. Furthermore, the actual bottom dimension of both shapes of photoresist can not be inspected by in-line SEM. Since the lift-off process have been give-up at 2

l

As the gate-first process of the LBG-CNTFETs constructs a 50– 70 nm step height, this step height will trap some CNTs at first and then these trapped CNTs will be flung across the local bot-tom-gate region during the spin-coating process. Thus, the possi-bility for CNTs to cross gate region between source and drain can be improved dramatically. The results also depend on the spin speed at the second step of the spin-coating process. These SWCNTs could not be trapped easily by the LBG at slower rotation speed (<2000 rpm) or faster rotation speed (>3000 rpm). Fig. 3 shows the SEM image of a CNT connecting source and drain metal. The most suitable step height is around 50–70 nm according to our experience. Smaller step height cannot trap CNTs efficiently and

-4 -2 0 2 4 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 Gate Drain Current (A) Gate voltage (V)

Fig. 2. Transfer characteristics of the LBG-CNTFETs with a lifted-off TiN local bottom-gate. The insert shows the cross-sectional SEM image of the sharp convex corner formed at the lifted-off gate edge.

Fig. 3. Top-view SEM image reveals a CNT crosses between source and drain electrode.

(a)

(b)

Si substrate

Isolation layer

Top gate

Sharp convex corner

Si substrate

Isolation layer

Local bottom-gated

Local bottom gate

Source Drain

Gate dielectric

carbon nanotube

Fig. 1. (a) Schematic structure of the conventional top-gate CNTFETs with sharp convex corner at the source/drain edge due to the lift-off process for source/drain patterning. (b) Schematic structure of the local bottom-gate CNTFETs. As the gate is patterned by dry etching, sharp convex corner as shown in the figure would not exist.

higher step height will accumulate too many CNTs. The yield of the LBG-CNTFETs can achieve as high as 74% (119 working devices among 160 measured devices) after process optimization.

Figs. 4 and 5shows the output (Id Vd) and transfer

character-istics (Id Vg) of the LBG-CNTFET device with poly-Si/Al2O3 gate

stack, respectively. The linearity of the output characteristics at lin-ear region agrees that Ti forms ohmic contact with the semicon-ducting CNT after PDA so that the device performance is mainly controlled by channel potential[8–11]. The drain current exceeds 2.5

l

transport mechanism is due to hole conduction because of hole-injection from source to channel at negative LBG bias and no

elec-tron-injection from drain to channel at positive LBG bias. This LBG-CNTFET exhibits superior subthreshold swing of 139 mV/dec with a turn-on/turn-off current ration (Ion/Ioff)  106 at Vd= 0.1 V.

The maximum transconductance of the same LBG-CNTFET is 1.27

l

LBG-CNTFET and several best samples reported in literatures [12–14]. It is clear that the performance of the proposed LBG-CNT-FET with poly-Si/Al2O3gate stack is compatible with the published

CNTFETs and the high performance goal has been reached. It should be noted that the PDA process greatly impacts the yield of the high performance LBG-CNTFETs. In this work, the S/D

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 Vg = 0V Vg = -2V Vg = -4V Drain current ( A ) Drain voltage (V)

Fig. 4. Output characteristic of the LBG-CNTFET with poly-Si(60 nm)/Al2O3(10 nm) gate stack. -4 -2 0 10-13 10-12 10-11 10-10 10-9 10-8 10-7

Drain current (A)

Gate voltage (V)

Fig. 5. Transfer characteristics of the LBG-CNTFET with poly-Si(60 nm)/ Al2O3(10 nm) gate stack.

Table 1

Device parameters of the proposed LBG-CNTFET and some published best results[12–14].

Sample A[12] Sample B[12] Sample C[13] Sample D[14] Our results

CNT diameter 1.7 nm 1.7 nm 1.7 nm 1.7 nm 1.4 nm

S/D metal Ti Ti Ti Pd Ti

Gate material Si Si Ti Al Si

Gate dielectric SiO2(15 nm) SiO2(90 nm) SiO2(15 nm) HfO2(8 nm) Al2O3(10 nm)

Gate length 2lm 2lm 0.26lm 0.05lm 0.8lm Ion 4.5lA 0.4lA – – 2.5lA Gm 2.6lS 0.03lS 3.3lS 30lS 1.27lS Ion/Ioff 105 105 105 103 106 SS (mV/dec) 98 165 130 110 139 -6 -4 -2 0 2 4 6 8 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 S/D:Ti before PDA after PDA

Drain current (A)

Gate voltage (V)

Fig. 6. Transfer characteristics of the LBG-CNTFET before and after 600 °C/180 sec PDA process with poly-Si(60 nm)/Al2O3(10 nm) gate stack and Ti S/D contact metal.

-6 -4 -2 0 2 4 6 8 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 S/D:Ni after PDA before PDA

Drain current (A)

Gate voltage (V)

Fig. 7. Transfer characteristics of the LBG-CNTFET before and after 600 °C/180 sec PDA process with poly-Si(60 nm)/Al2O3(10 nm) gate stack and Ni S/D contact metal. 668 T.-C. Lee et al. / Microelectronics Reliability 50 (2010) 666–669

metal was deposited by a sputtering technique which is a non-con-formal deposition process. Several nano-voids exist between CNTs and source/drain metal due to the high surface curvature of SWCNTs. These nano-voids will reduce the effective contact area. Furthermore, interfacial layer and/or contamination will also in-crease the contact resistance[15]. Hence, the contact resistance be-tween CNTs and S/D metal would deteriorate the electrical performance of the LBG-CNTFETs seriously. The PDA process can minimize the nano-voids caused by the S/D metal sputtering and form titanium carbide (TiC) phase at the Ti/CNTs contact region to form ohmic contact[16].Fig. 6shows that suitable PDA process can increase the Ionby six orders of magnitude.Figs. 7 and 8show

the transfer characteristics (Id Vg) of the LBG-CNTFET with nickel

(Ni) and chrome (Cr) as contact metal, respectively. The PDA pro-cess can increase the Ion by two orders of magnitude with Ni

source/drain. No apparent improvement for the Cr contacted de-vice due to the weak sticking and wetting effect between Cr and SWCNTs[17].

4. Conclusions

A novel LBG-CNTFETs with a gate-first process is proposed. High yield and high performance CNTFETs process using a SWCNTs spin-coating process has been demonstrated. The gate-first process con-structs a 50–70 nm step height, which enhances the probability for CNTs to cross over the gate region between source and drain, and reduce gate leakage current. The record high yield of the CNT-FETs is 74% after process optimization. High performance

LBG-CNTFET with a superior subthreshold swing of 139 mV/dec, high transconductance of 1.27

l

achieved with Ti source/drain after a 600° PDA process. Following the proposed process, a large amount of high performance CNTFETs can be fabricated easily for advanced study on the electrical char-acteristics of CNTFETs in the future.

Acknowledgment

This work is supported by the National Science Council, Taiwan, ROC under the Contract No. NSC 96-2120-M-007-001.

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Drain current (A)

Gate voltage (V)

Fig. 8. Transfer characteristics of the LBG-CNTFET before and after 600 °C/180 sec PDA process with poly-Si(60 nm)/Al2O3(10 nm) gate stack and Cr S/D contact metal.