IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 3, MARCH 2010 719
Hybrid Buck–Boost Feedforward and Reduced
Average Inductor Current Techniques in Fast Line
Transient and High-Efficiency Buck–Boost Converter
Ping-Ching Huang, Student Member, IEEE, Wei-Quan Wu, Student Member, IEEE, Hsin-Hsin Ho,
and Ke-Horng Chen, Senior Member, IEEE
Abstract—This paper presents a buck–boost converter with
high efficiency and small output ripple to extend the battery life of portable devices. Besides, the hybrid buck–boost feedforward (HBBFF) technique is integrated in this converter to achieve fast line response. The new control topology minimizes the switching and conduction losses at the same time even when four switches are used. Therefore, over a wide input voltage range, the proposed buck–boost converter with minimum switching loss like the buck or boost converter can reduce the conduction loss through the use of the reduced average inductor current (RAIC) technique. Moreover, the HBBFF technique minimizes the voltage variation at the output of error amplifier. Consequently, a fast line transient response can be achieved with small dropout voltage at the output. Especially, the converter can offer good line and load regulations to ensure a regulated output voltage without being affected by the decreasing battery voltage. Experimental results show that the output voltage is regulated over a wide battery lifetime, and the output ripple is minimized during mode transition. The peak efficiency is 97% and the transient dropout voltage can be improved substantially.
Index Terms—Fast line transient response, feedforward
tech-nique, high efficiency, noninverting buck–boost converter, smooth transition.
I. INTRODUCTION
W
ITH increasing low-voltage portable devices and grow-ing requirements of functionalities embedded into these devices, efficient power management techniques are required to extend battery life [1]–[3]. In order to effectively use the re-maining capacity of the battery, the design of dc–dc converters needs to supply the portable devices a regulated voltage over a wide battery voltage [4], [5]. The limitations of standard analog pulsewidth modulator (PWM) causes uncontrolled pulse skip-ping and significantly increased output voltage ripples when the converter operates in the transition region of the buck and boost modes [6]. That is, a buffer region, which is buck–boost mode, is required to provide a smooth and stable transition between two modes [7], [8]. As shown in Fig. 1, the converter can operate in buck, buck–boost, and boost modes when the battery volt-age decreases. Since the dc–dc converter has different operation Manuscript received May 5, 2009; revised July 15, 2009. Current version pub-lished April 2, 2010. This work was supported by the National Science Council, Taiwan, under Grant NSC 97-2221-E-009-172. Recommended for publication by Associate Editor D. Maksimovic.The authors are with the Department of Electrical and Control Engi-neering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2009.2031803
Fig. 1. Regulated output voltage versus the decreasing battery voltage.
Fig. 2. Buck–boost converter implemented by discrete components contains two dc–dc converters.
modes, the system stability, the output ripple, and the accuracy of the regulated output voltage during mode transition need to be guaranteed.
As shown in Fig. 2, the buck–boost converter implemented by discrete components contains two dc–dc converters. Con-sequently, there is twice the power loss associated with the topology that contains only one converter. Besides, the num-ber of external components is large and the complexity of two PWM control loops is hard to design. Certainly, the middle bulk capacitor that needs to absorb the pulsating current from both buck and boost stages has large value and volume. According to the design requirment, this topology causes the design of buck– boost converter hard to be implemented by the integrated chip. In order to overcome the drawbacks, the topology of H-bridge shown in Fig. 3(a) is widely used in the design of buck–boost converter [9]–[14]. The energy delivering path and the induc-tor current waveform of conventional buck–boost converter is depicted in Fig. 3(b). During phase I, switches A and C turns on to store energy in the inductor. During phase II, switches B and D turns on to deliver the energy to the output. According to voltage-second method [15], the average inductor current is 0885-8993/$26.00 © 2010 IEEE
Fig. 3. (a) Topology of H-bridge for the buck–boost converter and (b) energy-delivering path and inductor current waveform of the conventional design.
expressed as (1).
IL (avg)(1− D) = ILoad ⇒ IL (avg) =
ILoad
1− D. (1)
Either a buck or a boost converter, only two switches are turned on and off per cycle. The switching loss [16], [17] of a classic four-switch converter is double compared to the basic buck or boost converter. Especially, it causes an efficiency drop when the battery voltage approaches to the output voltage [18]. The inductor current becomes 2ILoad when VIN = VO U T and D= 50%. The conduction loss becomes four times that of a buck or a low-duty boost converter. The control topology of the conventional buck–boost converter [19], [20] has the fol-lowing disadvantages: The major drawback is the four switches are turned on/off during one switching cycle. As a result, much switching loss causes the power conversion efficiency is deteri-orated. Furthermore, the efficiency is further reduced when the value of the input voltage is close to that of the output volt-age since the avervolt-age inductor current is twice the load current. That is, the conduction loss is four times that of a pure buck or a low-duty boost converter. The design of buck–boost con-verter not only needs to simultaneously reduce the conduction and switching losses but also needs to reduce the output ripple during the mode transition. The proposed buck–boost control scheme can effectively reduce the conduction loss through the use of the reduced average inductor current (RAIC) technique for improving efficiency. Besides, it also provides a proximate-linear buffer region with smooth and stable transition between the buck and boost modes in order to achieve low-output voltage ripple.
Furthermore, the feedforward compensation can effectively and rapidly reduce line disturbance on the converter’s output to improve line transient response for the design of the
voltage-mode switching converters [21]–[24]. The implementation of the feedforward technique simply varies the peak and valley voltages of the sawtooth signal with the input voltage in buck and boost converters, respectively. In other words, one of the peak and valley voltages needs to be changed according to the variation of the input voltage for the basic buck or boost converter. However, the sawtooth signal in the voltage-mode buck–boost converter needs to have the ability to simultane-ously vary the peak and valley voltages with the input voltage according to the operation mode, as shown in Fig. 1. It means that line transient response time can be reduced whether the bat-tery voltage is higher than the output supply voltage or not. This paper presents the hybrid buck–boost feedforward (HBBFF) technique integrated in the buck–boost converter to regulate the output voltage with fast line transient response. Good line regu-lation is guaranteed to get little output voltage variation in case of the input voltage variation. That is, the HBBFF technique can improve the static and dynamic performance of the buck–boost converter without being affected by the large variation of the battery voltage.
The organization of this paper is Section II describes the proposed buck–boost converter with the RAIC technique. Section III describes the circuit implementation composed of the HBBFF technique and the mode detector to demonstrate the per-formance of the buck–boost converter. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.25 µm process, and the experimental results are shown in Section IV to verify the theory of proposed control scheme. Finally, a conclusion is made in Section V.
II. TOPOLOGY OF THEBUCK–BOOSTCONVERTER WITH THERAIC TECHNIQUE
The proposed RAIC technique in the buck–boost converter has four operations modes, denoted by mode I–mode IV. When
VIN is much higher than VO U T, the converter operates in the
basic buck mode, denoted by mode I. Switch D and switch C always turn on and off, respectively. Similarly, mode IV defines the basic boost mode when VIN is much smaller than VO U T.
Switch A and switch B always turn on and off, respectively. The efficiencies in two modes are approximately equal to the fundamental buck and boost converters, respectively. When VIN
approaches to VO U Tand the converter needs to switch the buck
operation to boost operation, the standard analog PWM control causes the uncontrolled pulse skipping and the increased output voltage ripple. The dash line of the output voltage with large ripple illustrates the limitation of the conventional control, as shown in Fig. 4. It is obvious that the uncontrolled pulse skip-ping increases the undesired large output voltage ripple. A buffer stage needs to insert between the buck and the boost modes in or-der to reduce the output ripple. Unfortunately, the new insertion of operation mode reduces the time of the basic buck and boost operations in a battery lifetime [25], [26]. Besides, the buffer stage causes the increasing inductor current level and thus the conduction loss is further increased. As a result, the switching loss is also increased because the four switches need to turn on/off during one switching cycle. That is, the longer buffer
HUANG et al.: HBBFF AND RAIC TECHNIQUES IN FAST LINE TRANSIENT AND HIGH-EFFICIENCY BUCK–BOOST CONVERTER 721
Fig. 4. Output voltage, the inductor current waveform, and the energy-delivering path when the buck–boost converter operates in (a) mode I and mode II and (b) mode III and mode IV.
stage may cause the power conversion efficiency more deteri-orated. Although a regulated and small-ripple output voltage can be achieved by the insertion of the buffer stage. However, the cost is the deteriorated efficiency. The RAIC technique is proposed to reduce the inductor current level and the switching possibility of the four switches for improving the efficiency.
Mode II and mode III constitute a proximate-linear buffer region in order to smoothly transit the operation from buck mode (mode I) to boost mode (mode IV). As conceptually illustrated in Fig. 4, the inductor waveform of the RAIC technique has lower average value without the undesired pulse skipping and large output voltage ripple. Besides, the power conversion efficiency can be improved in the proximate-linear buffer region since the RAIC technique reduces the switching possibility of the four switches during one switching period. The proximate-linear buffer region is described as follows.
When VIN is equal or slightly greater than VO U T, the
op-eration needs more buck opop-eration. The mode II uses a fixed boost duty KBo ostduring the period of TS 1. During the period of TS 2, the converter is operated in buck mode regulated by the duty cycle of DBuck. The value of KBo ost should be selected
equal to or larger than 10% to avoid the nonlinear operation of the PWM generation. The inductor current waveform and the output voltage are shown in Fig. 4(a) when the buck–boost con-verter operates in modes I and II. On the other hand, when VINis
slightly smaller than VO U T, the buck–boost converter operates
in mode III, which needs more boost operation owing to the lower input voltage. During the period of TS 1, the buck–boost converter operates in boost mode regulated by the duty cycle of
DBo ost. During the period of TS 2, the buck–boost converter op-erates in buck mode with a fixed duty cycle of KBuck. Similarly,
Fig. 5. Proposed buck–boost converter with the RAIC and HBBFF techniques.
the value of KBuck should be selected equal to or smaller than
90% to avoid the nonlinear operation of the PWM generation. Fig. 4(b) shows the inductor current waveform and the output voltage when the buck–boost converter operates in mode III and mode IV. Obviously, the pulse skipping in the conventional method can be eliminated. A regulated and low-ripple output voltage can be guaranteed.
The RAIC technique uses two switching cycles composed of one buck and one boost cycles to constitute one regulation cycle when the supply voltage approaches to the output voltage. The switching loss can be reduced since only two switches are turned on/off in one switching cycle. Furthermore, the period of
tA C that only delivers energy to the inductor is minimized and thus the average inductor current level, as shown in (2), can be close to the load current. In other words, the RAIC technique can reduce the conduction loss since the difference between the average inductor current and the output load current is reduced
ILoad = IL ,avg
(tA D+tB D)
(tA D+ tB D + tA C) ∵ tA C tA D +tB D ∴ IL ,avg∼= ILoad. (2)
III. IMPLEMENTATION OF THEPROPOSED
BUCK–BOOSTCONVERTER
Fig. 5 illustrates the schematic of the proposed buck–boost converter. The converter is composed of a power stage, a feed-back network, and a PWM control stage. A power stage contains an H-Bridge structure with power switches A–D, an inductor L, and a filtering capacitor CO U T. VO U Tis scaled down to VF B by the voltage divider, composed of resistors R1and R2. A
voltage-mode PWM controller is utilized to turn on/off switches A–D. The mode detector decides the suitable operation mode accord-ing to not only the input voltage and output voltage but also load current. Besides, the dynamic sawtooth generator for im-plementing HBBFF technique improves line response. The com-parators COMP1 and COMP2 compare the output signal VE A
Fig. 6. Frequency response of the buck–boost converter with PID compensa-tion to extend the system bandwidth.
from the error amplifier with the sawtooth signals SAWBuckand
SAWBo ostto decide buck duty DBuckand boost duty DBo ost,
re-spectively. The output filter exhibits a double pole response, and a troublesome feature in boost mode (mode IV) is the right-half plane (RHP) zero. The RHP zero limits the unity gain frequency of the closed-loop performance of the buck–boost converter. In order to achieve a higher bandwidth, the PID compensation is used. PID compensation provides two zeros to cancel out the output filter double poles and thus avoid sharply decreasing phase margin. In addition, PID compensation contributes one dominant pole and two high-frequency poles, which are used to suppress high-frequency noise. The converter is compensated for the worst-case where the boost duty cycle is at its peak value. The frequency response of the buck–boost converter with the PID compensation is depicted in Fig. 6.
A. Method and Analysis of the HBBFF Technique
According to the principle of inductor volt-second balance, the relationship between VIN and VO U T in different operation
modes is shown in (3)–(6) Mode I:VO U T VIN = DBuck = VE A− VL Buck VH Buck− VL Buck (3) Mode II:VO U T VIN = 1 + DBuck 1 + (1− KBo ost)
= 1 + [(VE A − VL Buck)/(VH Buck− VL Buck)] 2− KBo ost (4) Mode III:VO U T VIN = 1 + KBuck 1 + (1− DBo ost) = 1 + KBuck
1 + [(VH Bo ost− VE A)/(VH Bo ost− VL Bo ost)] (5) Mode IV:VO U T VIN = 1 1− DBo ost =VH Bo ost− VL Bo ost VH Bo ost− VE A . (6) VH Buckand VH Bo ostare the peak voltages of the buck saw-tooth SAWBuckand the boost sawtooth SAWBo ost, respectively.
Similarly, VL Buck and VL Bo ost are the valley voltages of the buck sawtooth SAWBuck and the boost sawtooth SAWBo ost,
Fig. 7. Conventional PWM waveform and proposed dynamic PWM waveform for buck.
Fig. 8. Conventional PWM waveform and proposed dynamic PWM waveform for boost.
respectively. For the voltage-mode operation, the input voltage change must have an effect on the output voltage to determine the desired duty cycle. As a result, the output voltage needs much time to be regulated to a stable value, which is different to the previous steady-state value. As the dash line shown in Figs. 7 and 8, the transient response is slowed down by the volt-age ∆VE A on the large compensation capacitor at the output node of the error amplifier. Thus, a feedforward path is needed to rapidly react to the input voltage change without affecting the regulated output voltage. In (3) and (4), the value of VE A is as-sumed to be constant. Keeping VL Buck constant and changing
VH Buck with a value proportional to the input voltage can sim-plify the implementation of feedforward technique. The solid line in Fig. 7 illustrates the waveform of the sawtooth SAWBuck
in modes I and II. The peak voltage of the buck sawtooth is decreased from VH Buck1 to VH Buck2 and thus the duty cy-cle, DBuck, is instantly increased to maintain a regulated output
voltage.
Similarly, in (5) and (6), the valley voltage VL Bo ostneeds to be proportional to the input voltage with a constant VH Bo ost when the converter operates in modes III and IV. As the solid line depicted in Fig. 8, VL Bo ost is decreased from VL Bo ost1 to VL Bo ost2 and thus the duty cycle, DBo ost, is instantly
in-creased to maintain a regulated output voltage. In conclusion, the feedforward technique can have much small dip voltage and fast response. Therefore, the line transient response is improved substantially.
B. Implementation of Dynamic Buck Sawtooth Generator
The sawtooth generator of the buck mode is shown in Fig. 9(a). The value of VL Buck is set equal to 0.7 through
HUANG et al.: HBBFF AND RAIC TECHNIQUES IN FAST LINE TRANSIENT AND HIGH-EFFICIENCY BUCK–BOOST CONVERTER 723
Fig. 9. (a) Proposed dynamic buck sawtooth generator. (b) States of the two switches under different mode. (c) Waveform under different supply voltages.
the use of a unity gain buffer. The charging current IC 1, which is from a voltage to current (V–I) converter composed of the transistor MN 2, a resistor RV I, and an operational amplifier, is proportional to VIN. The frequency of pulse signal clkBo ost is
the same as the converter’s switching frequency. The switch sw1
turns on while the switch sw2turns off in mode I, while sw1and
sw2are all turned on in mode II. The states of the switches are
sorted, as shown in Fig. 9(b), when converter operates in mode I and mode II. The capacitor C1 is charged by IC 1within the period of ∆tC hargeand discharged by the transistor MN 1to the low threshold voltage of 0.7 V in mode I. As a result, VL Buckis constant and VH Buck is proportional to VIN. The waveform of
the sawtooth SAWBuckand the relationship between the supply
voltage VIN and SAWBuck are shown in Fig. 9(c).
A low-pass filer composed of RF 1 and CF 1 is used to elim-inate the converter’s switching noise. The buck duty cycle will be suddenly decreased when the converter transits from mode I to mode II due to the insertion of the boost operation with fixed duty. In order to smooth the output voltage in mode transition, an extra charging current IC 2, proportional to VIN, is inserted
to compensate the mode transition error. The duty cycle would
Fig. 10. (a) Proposed dynamic boost sawtooth generator. (b) States of the four switches in different modes. (c) Waveform under different supply voltage.
decrease immediately, because the slope of SAWBuck changes
from the value of IC 1/C1 to the value of (IC 1+ IC 2)/C1 in
the charging period. Therefore, the output voltage is not influ-enced when the converter transits between modes I and II. The value of VH Buckin modes I and II is expressed as (7) and (8), respectively. VH Buck = VL Buck+ IC 1∆tC harge C1 where VL Buck = 0.7 (7) VH Buck = VL Buck+ (IC 1+ IC 2)∆tC harge C1 where VL Buck = 0.7. (8)
C. Implementation of Dynamic Boost Sawtooth Generator
The boost sawtooth generator is shown in Fig. 10(a). A unity gain buffer is used to ensure the source voltage VSis set to 1.4 V. A V–I converter is composed of the transistor MN 2, a resistor
RV I, and an operational amplifier. The current flowing through the transistor MN 1is designed larger than that flowing through the transistor MN 2. Therefore, the current flowing through the transistor MP 1is inversely proportional to the value of VIN. By
this method, the charging currents IC 3–IC 5 are also inversely proportional to VIN. The reference current IR EFcan charge the
voltage on the capacitor C2 from 1.4 V to VH Bo ostwithin the period of ∆tC harge. Both switches sw3 and sw5 turn on while
sw4 and sw6 turn off in mode IV. In mode III, four switches
sw3–sw6all turn on. The states of switches are sorted, as shown
In mode IV, the voltage on the capacitor C2is charged by IC 3 within ∆tC harge and discharged by transistor MN 2 to 1.4 V. Similar to the buck sawtooth generator, the peak voltage of
VSAW 2 is inversely proportional to VIN and the valley voltage
of VSAW 2 is fixed at 1.4. A low-pass filter composed of RF 2 and CF 2 is used to eliminate the glitch of VSAW 2 and outputs a
low noise signal VSAW 3. Then, an operational amplifier with
re-sistive negative feedback is used to ensure VSAW 3 ≈ SAWPre.
The voltage across resistor RD rop (RD rop = ∆tC harge/C2) is
equal to the difference voltage between the peak voltage of SAWPre and VH Bo ost. Therefore, the peak and valley volt-ages of SAWBo ost in mode IV are expressed as (9) and (10),
respectively. VH Bo ost= 1.4 + IC 3∆tC harge C2 − (IC 3− IR EF)RD rop = 1.4 +IR EFtC harge C2 (9) VH Bo ost= 1.4 + IC 3∆tC harge C2 − (IC 3− IR EF )RD rop = VL Bo ost+ IC 3∆tC harge C2 ⇒ VL Bo ost = 1.4− (IC 3− IR EF)RD rop. (10)
According to (9) and (10), the value of VH Bo ost is con-stant and the value of VL Bo ost is equal to the value of [1.4− (IC 3− IR EF)RD rop]. Therefore, VL Bo ost is propor-tional to VIN. The waveform of the sawtooth SAWBo ost and
the relationship between the supply voltage VIN and SAWBo ost
are shown in Fig. 10(c). The boost duty cycle increases when mode IV transits to mode III due to the insertion of the buck op-eration with fixed duty in mode III. Similarly, in order to have a smooth output voltage during mode transition, the currents IC 4 and IC 5that have the same value are introduced to increase the amplitude of VSAW 2 and keep the peak voltage of SAWBo ost
invariant. That is VH Bo ost and VL Bo ost in mode III can be expressed as (11) and (12), respectively.
VH Bo ost = 1.4 + (IC 3+ IC 4)∆tC harge C2 − (IC 3− IR EF+ IC 5)RD rop = VL Bo ost+ (IC 3+ IC 4)∆tC harge C2 = 1.4 +IR EF∆tC harge C2 (11) where VL Bo ost= 1.4− (IC 3− IR EF+ IC 5)RD rop. (12)
It shows that the peak voltage of the boost sawtooth is kept at VH Bo ost even the operating mode transits from mode IV to mode III. According to (11) and (12), the slope of SAWBo ost
ad-justs from the value of IC 3/C2to the value of (IC 3+ IC 4)/C2
immediately in the charging period in order to increase the boost duty cycle to smooth the output voltage during mode III– mode IV.
D. Mode Detector for Implementing the RAIC Technique
The design of the proposed buck–boost converter should con-sider the effect of the power MOSFET’s on-resistance. The duty cycle is not only decided by VIN and VO U T but also by load
current ILoad since ILoad flowing through the switches causes
large voltage drop VSW. Owing to the consideration of the power
MOSFET’s on-resistance, the output ripples will not be enlarged during mode transition. Correct input/output characteristics of four modes are defined in (13)–(16).
Mode I: VIN − 2 VSW DBuck = VO U T DBuck (13) Mode II: VIN− 4 1 + DBuck VSW = 2− KBo ost 1 + DBuck VO U T (14) Mode III: VIN− 4 1 + KBuck VSW = 2− DBo ost 1 + KBuck VO U T (15)
Mode IV: VIN− 2VSW = (1− DBo ost) VO U T. (16)
The proposed mode detector as illustrated in Fig. 11 can provide a smooth and stable transition among the four modes. The mode detector is composed of three parts. The voltage drop sensing circuit is used to detect the value of VSW. The current of VSW/R1flows through the resistor R2 to generate the decision
signal VD ECas expressed in (17). VD EC= VIN − 1 + R2 R1 VSW. (17)
In order to derive the boundary condition, assume DBuck = KBuck and DBo ost = KBo ost. When mode I transits to mode II,
the difference voltage, which is equal to VD EC− VO U T, needs
to compare with K1VO U T, as shown in (18). VD EC = VIN − 2 VSW KBuck = VO U T KBuck = VO U T+ K1VO U T where K1 = 1− KBuck KBuck . (18) Similarly, the difference voltage needs to compare with (−KBo ostV−), as shown in (19), when mode III transits to
mode IV.
VD EC= VIN− 2VSW = VO U T− KBo ostVO U T. (19)
Finally, VD ECneeds to compare with VO U T, as shown in (20),
when mode II transits to mode III.
VD EC = VIN−
4 1 + KBuck
VSW = VO U T. (20)
Evidently, the value of VD EC in different mode needs to be
finely adjusted according to the values of R1 and R2.
An absolute voltage VA B S that is equal to|VD EC–VO U T| is
used to decide when mode I transits to mode II and mode III tran-sits to IV. The dual modified-cascoded flipped voltage follow-ers (M-CASFVF) V–I converter can generate the signal VA B S.
The negative feedback loop in the input pair causes the out-put impedance low enough to limit the voltage variations at the drains of the transistors MN 1 and MN 2. As a result, the undesired channel-length modulation can be minimized. The advantage of the M-CASFVF circuit is the gate voltages of the
HUANG et al.: HBBFF AND RAIC TECHNIQUES IN FAST LINE TRANSIENT AND HIGH-EFFICIENCY BUCK–BOOST CONVERTER 725
Fig. 11. Proposed mode detector for implementing the RAIC technique. transistors MP 3 and MP 4 are dynamically biased. The input common mode range (ICMR) of the conventional CASFVF circuit with fixed biasing scheme is small and not suitable in the buck–boost converter that needs wide input supply volt-age. On the contrary, the transistors MP 5, MP 6, MP 7, and
MP 8 are used to dynamically bias MP 3 and MP 4 in the M-CASFVF circuit. Thus, the advantage of the M-CASFVF circuit is the ICMR is much larger than that of the conven-tional design and is suitable for wide supply voltage range. The difference between VD EC and VO U T is equal to the difference
between VP F and VNF. When VP F is greater than VNF, the switch sw1 turns on and the switch sw2 turns off. A current
with the value of (VP F–VNF)/R3 will flow through the
resis-tor R4 according to the ratio of current mirror. If R3 = R4, VA B S= VP F–VNF = VD EC–VO U T. Similarly, a programmed
current with the value of (VNF–VP F)/R3flows through the
re-sistor R4 and thus the value of VA B S is equal to the value of
(VO U T–VD EC) when VP F is smaller than VNF.
The mode decoder can generate the digital signals S[0]–S[3] to indicate mode I to mode IV. It includes two comparators and a 4–2 decoder. The signal VD 1 is the comparison result between VP F and VNF that are proportional to VD ECand VO U T,
respectively. Thus, the transient point of VD 1 represents the boundary between mode II and mode III according to (20). The signal VD 2is the comparison result between VA B Sand K1VO U T
in mode I and mode II. However, it is the comparison result between VA B Sand KBo ostVO U Tin mode III and mode IV. The
signals VD 1and VD 2pass through the 4–2 decoder and generate
Fig. 12. Chip micrograph.
S[0], S[1], S[2], and S[3] that are representative of mode I to
mode IV, respectively.
IV. EXPERIMENTALRESULTS
The buck–boost converter was fabricated by TSMC 0.25 µm 1P4M process. The filter components contain L = 4.7 µH,
CO U T= 47 µF, and RESR = 75 mΩ. The input voltage ranges
from 2.7 to 4.5V, and the nominal output voltage is 3.3 V. The switching frequency is designed as 700 kHz. Fig. 12 shows the chip micrograph with die area of 3.14 mm2.
Fig. 13. Uncontrolled pulse skipping increases output ripple around buck–boost mode.
Fig. 14. Mode I transits to mode II when VINchanges from 4.2 to 3.8 V, and IL o a dis 225 mA.
Fig. 15. Mode II transits to mode III when VINchanges from 3.6 to 3.5 V, and IL o a dis 225 mA. Fig. 13 shows the increasing output ripple due to the
un-controlled pulse skipping when the operation mode is close to the transition from buck to boost mode without the buck– boost buffer mode. After the implementation of the buck–boost buffer mode, Figs. 14–16 show the stable operation when the input voltage decreases with ILoad = 225 mA. Figs. 13 and 14
demonstrate that the output voltage ripple is reduced from 100 to within 10 mV in worst-case. The operation mode can smoothly switch from mode I to mode IV, and the inductor current is re-duced to close to the value of load current. Thus, the conduction loss can be improved. Besides, the number of switches are used
in one switching cycle is also reduced from four to two. As a result, the switching loss can be further reduced. Fig. 17 shows that the output voltage is regulated in steady state when the sup-ply voltage is equal to the output voltage. The proposed control method effectively removes the undesired pulse skipping and thus avoids increasing the output voltage ripple.
Fig. 18 shows the line transient response with and without the HBBFF technique when load current is 225 mA. The in-put voltage VIN steps from 3.9 to 3.6 V within 50 µs. At this
time, the buck–boost converter is operated at the buck–boost mode with more buck operation. The dropout voltage of the
HUANG et al.: HBBFF AND RAIC TECHNIQUES IN FAST LINE TRANSIENT AND HIGH-EFFICIENCY BUCK–BOOST CONVERTER 727
Fig. 16. Mode III transits mode IV when VINchanges from 3.2 to 2.8 V, and IL o a dis 225 mA.
Fig. 17. Waveform under steady state when supply voltage is equal to output voltage with IL o a d= 225 mA.
Fig. 18. Output voltage waveform when the input voltage VINsteps from 3.9 to 3.6 V within 50 µs. (a) Without the HBBFF technique. (b) With the HBBFF technique.
Fig. 19. Output voltage waveform when the input voltage VINsteps from 3.2 to 3.5 V and load current is 225 mA. (a) Without the HBBFF technique. (b) With the HBBFF technique.
HUANG et al.: HBBFF AND RAIC TECHNIQUES IN FAST LINE TRANSIENT AND HIGH-EFFICIENCY BUCK–BOOST CONVERTER 729
Fig. 21. Improvement of conduction and switching losses.
Fig. 22. Measured power efficiency of the proposed converter with different supply voltage and load current.
converter without the proposed control technique is 30 mV. On the contrary, the output voltage VO U T can be maintained at its
regulated voltage level owing to the fast response benefited from the HBBFF technique. It is obvious that when the input voltage drops, the converter without the HBBFF technique relies only on the voltage feedback loop. That is the reason that VO U T has
large variation during the line transient period.
In Fig. 19, when the input voltage steps from 3.2 to 3.5 V and load current is 225 mA, the buck–boost converter operates at the buck–boost mode with more boost operation. The overshoot voltage is decreased from 100 to 15 mV due to the HBBFF technique.
Fig. 20 shows the measured transient response of the output voltage and the inductor current of the proposed buck–boost converter with 200 mA load step (from 80 to 280 mA) at 3.7 V input. It demonstrates that the proposed converter not only has stable operation over wide input voltage range but also wide load current range. Fig. 21 shows the improvement of power loss. The blue line draws the conduction loss ratio defined as γC on, which
is equal to conventional buck–boost control to the proposed control. The red line draws the switching loss ratio defined as
γSw, which is equal to conventional buck–boost control to the
proposed control. Obviously, conduction and switching losses both are improved substantially by the proposed control method. Efficiency of the proposed buck–boost converter is measured and shown in Fig. 22. Maximum efficiency is 97%, operated at input supply voltage of 3.8 V and load current of 400 mA. It also shows that efficiency still maintains at relatively high value
TABLE I
SUMMARY OFSPECIFICATIONS ANDCOMPARISON
when the supply voltage is decreased to close to the output voltage. The summary of specifications is listed in Table I.
V. CONCLUSION
A buck–boost converter with a new control scheme was intro-duced in this paper. Several advantages include reintro-duced switch-ing losses through the use of only half the number of switches during each cycle and decreased conduction losses of power switches due to the RAIC technique. The efficiency is effec-tively improved. A new mode detector can select proper oper-ating mode to get a regulated output and thus enhanced control accuracy are guaranteed during mode transition. Besides, the HBBFF technique is integrated in this converter to minimize the voltage variation at the output of error amplifier. As a result, a fast line transient response can be achieved with small dropout voltage at the output. Experimental results show that the output voltage is regulated during the whole battery life, and the out-put transition is very smooth during the mode transition by the proposed control scheme. The peak efficiency is 97% and the transient dropout voltage can be improved substantially.
ACKNOWLEDGMENT
The authors would like to thank Chunghwa Picture Tubes, Ltd. for their help.
REFERENCES
[1] “High efficient single inductor buck-boost converter with 1.8 A switches,” Texas Instruments, Washington, DC, Tech. Rep. TPS63000, Jul. 2008. [2] “1A synchronous buck-boost high current LED driver,” Linear Technol.
Corp., Milpitas, CA, Tech. Rep. LTC3454, Dec. 2005.
[3] Maxim application note AN-1205. W-CDMA Power Supply Dramatically Improves Transmit Efficiency. (2001, Oct.). [Online]. Available: http:// www.maxim-ic.com/appnotes.cfm/an_pk/1205.
[4] W. R. Liou, M. L. Yeh, and Y. L. Kuo, “A high efficiency dual-mode buck converter IC for portable applications,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 667–677, Mar. 2008.
[5] S. Zhou and G. A. Rincon-Mora, “A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable appli-cations,” IEEE Trans. Circuits Syst. II, vol. 53, no. 4, pp. 319–323, Apr. 2006.
[6] R. Paul and D. Maksimovic, “Analysis of PWM nonlinearity in non-inverting buck-boost power converter,” in Proc. IEEE PESC Conf. 2008, pp. 3741–3747.
[7] D. M. Dwelley and T. W. Barcelo, “Systems andmethods for linearly varying a pulse-width modulation signal with a control signal,” U.S. Patent 6 404 251, June 11, 2002.
[8] “Micropower synchronous buck-boost DC/DC converter,” Linear Technol. Corp., Milpitas, CA, Tech. Rep. LTC3440, 2001.
[9] R. Paul, L. Corradini, and D. Maksimovic, “Modulated digitally controlled non-inverting buck-boost converter for WCDMA RF power amplifiers,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Feb. 2009, pp. 533–539.
[10] H.-J. Yang, K.-H. Chen, and Y.-P. Lee, “Feed-forward pulse width modu-lation for high line regumodu-lation buck or boost converter,” in Proc. IEEE Int.
Symp. Circuits Syst. (ISCAS 2007), May, pp. 785–788.
[11] M. D. Dwelley and T. W. Barecelo, “Control circuit and method for maintaining high efficiency in a buck-boost switching regulator,” U.S. Patent 6 166 527, Dec. 2000.
[12] C. Jingquan, D. Maksimovic, and R. W. Erickson, “Analysis and design of a low-stress buck-boost converter in universal-input PFC applications,”
IEEE Trans. Power Electron., vol. 21, no. 2, pp. 320–329, Mar. 2006.
[13] Y. J. Lee, A. Khaligh, and A. Emadi, “A compensation technique for smooth transitions in a noninverting buck-boost converter,” IEEE Trans.
Power Electron., vol. 24, no. 4, pp. 1002–1015, Apr. 2009.
[14] X. Ren, X. Ruan, H. Qian, M. Li, and Q. Chen, “Three-mode dual-frequency two-edge modulation scheme for four-switch buck-boost con-verter,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 499–509, Feb. 2009.
[15] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA: Kluwer, 2000.
[16] Y. Xiong, S. Sun, H. Jia, S. Patrick, and S. Z. John, “New physical insights on power MOSFET switching losses,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 525–531, Feb. 2009.
[17] W. Eberle, Z. Zhang, Y. F. Liu, and P. C. Sen, “A practical switching loss model for buck voltage regulators,” IEEE Trans. Power Electron., vol. 24, no. 3, pp. 700–713, Mar. 2009.
[18] T.-J. Tai and K.-H. Chen, “Switching loss calculation (SLC) and posi-tive/negative compensated dynamic droop scaling (PNC-DDS) technique for high-efficiency multiple-input single-output (MISO) systems,” IEEE
Trans. Power Electron., vol. 24, no. 5, pp. 1386–1398, May 2009.
[19] J. Chen, D. Maksimovic, and R. W. Erickson, “Buck-boost PWM convert-ers having two independently controlled switches,” in Proc. IEEE PESC
Conf. 2001, pp. 17–21.
[20] E. Schaltz, P. O. Rasmussen, and A. Khaligh, “Non-inverting buck-boost converter for fuel cell applications,” in Proc. Ind. Electron., Nov. 2008, pp. 855–860.
[21] B. Arbetter and D. Maksimovic, “Feed-forward pulse-width modulators for switching power converters,” in Proc. IEEE PESC Conf. 1995, pp. 601– 607.
[22] M. K. Kazimierczuk and L. A. Starman, “Dynamic performance of PWM DC-DC boost converter with input voltage feed-forward control,” IEEE
Trans. Circuits Syst. I, vol. 46, no. 12, pp. 601–607, Dec. 1999.
[23] S. Chae, B. Hyun, P. Agarwal, W. Kim, and B. Cho, “Digital predictive feed-forward controller for a DC-DC converter in plasma display panel,”
IEEE Trans. Power Electron., vol. 23, no. 2, pp. 627–634, Mar. 2008.
[24] X. Cao, W. J. Chiang, Y. C. King, and Y. K. Lee, “Electromagnetic energy harvesting circuit with feed-forward and feedback DC-DC PWM boost converter for vibration power generator system,” IEEE Trans. Power
Electron., vol. 22, no. 2, pp. 479–486, Mar. 2007.
[25] B. Sahu and G. A. Rincon-Mora, “A low voltage, dynamic, non-inverting, synchronous buck-boost converter for portable applications,” IEEE Trans.
Power Electron., vol. 19, no. 2, pp. 443–452, Mar. 2004.
[26] B. Sahu and G. A. Rincon-Mora, “A high efficiency WCDMA RF power amplifier with adaptivedual mode buck-boost supply and bias-current con-trol,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp. 238–240, Mar. 2007.
Ping-Ching Huang (S’09) was born in Taipei,
Taiwan. He received the B.S. and M.S. degrees from the Department of Electrical and Control En-gineering, National Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively.
He is currently a Member of the Mixed Signal and Power Management IC Laboratory, National Chiao Tung University. His research interests include the design of power management circuit, the analog in-tegrated circuit designs, and LED driver ICs.
Wei-Quan Wu (S’09) was born in Changhua,
Taiwan. He received the B.S. and M.S. degrees from the Department of Electrical and Control En-gineering, National Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively.
He is currently a member of the Mixed Signal and Power Management IC Laboratory, National Chiao Tung University. His research interests include the design of power management circuit, LED driver ICs, and the analog IC designs.
Hsin-Hsin Ho was born in Taipei, Taiwan. She
re-ceived the B.S. degree in electrical and control en-gineering in 2006 from the National Chiao Tung University, Hsinchu, Taiwan, where she is currently working toward the Ph.D. degree in electrical and control engineering.
Her current research interests include projects of LED driver ICs and power management ICs at Low Power Mixed Signal Laboratory. Other research in-terests include power management circuit designs, LED driver ICs, and analog IC designs.
Ke-Horng Chen (M’04–SM’09) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC Designer at Philips, Taipei. From 1998 to 2000, he was an Ap-plication Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power manage-ment ICs. He is currently an Associate Professor at the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 80 papers published in journals and conferences. He is the holder of several patents. His research interests include power management ICs, mixed-signal cir-cuit designs, display algorithm and driver designs of liquid crystal display TV, red, green, and blue color sequential backlight designs for optically compen-sated bend panels, and low-voltage circuit designs.
