致中板VHDL

致中板

kout

kin

kout

kin

共

陽

極

七

段

顯

示

七段解碼

a

b

c

d

e

f

g

A

B

C

D

Segin[3:0]

Segout[6:0]

燈

節

低

電

位

亮

port (segin : in std_logic_vector(3 downto 0); segout : out std_logic_vector (6 downto 0)); end entity;

architecture rtl of v_7seg is begin

with segin select

segout <= "1000000" when x"0", "1111001" when x"1", "0100100" when x"2", "0110000" when x"3", "0011001" when x"4", "0010010" when x"5", "0000010" when x"6", "1111000" when x"7", "0000000" when x“8", "0010000" when x"9", "0001000" when x"a", "0000011" when x"b", "1000110" when x"c", "0100001" when x"d", "0000110" when x"e", "0001110" when x"f"; end rtl;

共

陽

極

七

段

顯

示

七段解碼

a

b

c

d

e

f

g

A

B

C

D

Segin[3:0]

Segout[6:0]

燈

節

低

電

位

亮

port (segin : in std_logic_vector(3 downto 0); segout : out std_logic_vector (6 downto 0)); end entity;

architecture rtl of v_7seg is begin

with segin select

segout <= "1000000" when x"0", "1111001" when x"1", "0100100" when x"2", "0110000" when x"3", "0011001" when x"4", "0010010" when x"5", "0000010" when x"6", "1111000" when x"7", "0000000" when x“8", "0010000" when x"9", "0001000" when x"a", "0000011" when x"b", "1000110" when x"c", "0100001" when x"d", "0000110" when x"e", "0001110" when others; end rtl;

library ieee;

use ieee.std_logic_1164.all; entity v_7seg is

port (segin : in std_logic_vector(3 downto 0); segout : out std_logic_vector (6 downto 0)); end entity;

architecture rtl of v_7seg is begin

with segin select

segout <= "1000000" when x"0", "1111001" when x"1", "0100100" when x"2", "0110000" when x"3", "0011001" when x"4", "0010010" when x"5", "0000010" when x"6", "1111000" when x"7", "0000000" when x“8", "0010000" when x"9", "0001000" when x"a", "0000011" when x"b", "1000110" when x"c", "0100001" when x"d", "0000110" when x"e", "0001110" when x"f"; end rtl;

v_7seg

0~f字形

Tools

Netlist viewers

RTL

viewer

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component;

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component;

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

end

rtl;

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component;

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

end

rtl;

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component;

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component

;

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

七段顯示(componernt

instantiation

)

library ieee

;

use ieee.std_logic_1164.all

;

use work

.my_pkg.

all

;

entity

c_7seg

is port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end entity

;

architecture

rtl

of

c_7seg

is

begin

v_7seg0 : v_7seg

port map

(segin => segin,segout => segout);

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity m_7seg is port

( segin : in std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of v_4disp is

begin

v_7seg0 : v_7seg port map (segin =>segin, segout => segout);

end rtl;

共

陽

極

七

段

顯

示

將

component

放

入

package

主

程

式

不

用

再

寫

component

建立package程式，不須compile

add入project內

七段顯示(

package)

library ieee;

use ieee.std_logic_1164.all;

package

my_pkg

is

component

v_7seg

port

(

segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0)

);

end component

;

end

my_pkg;

無entity

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity m_7seg is port

( segin : in std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of v_4disp is

begin

v_7seg0 : v_7seg port map (segin =>segin, segout => segout);

end rtl;

共

陽

極

七

段

顯

示

將

component

放

入

package

主

程

式

不

用

再

寫

component

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity m_7seg is port

( segin : in std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of v_4disp is

begin

v_7seg0 : v_7seg port map (segin =>segin, segout => segout);

end rtl;

共

陽

極

七

段

顯

示

未

接

七

段

公

共

腳

com

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity m_7seg is port

( segin : in std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of v_4disp is

begin

v_7seg0 : v_7seg port map (segin =>segin, segout => segout);

qout <= "0001" ;

end rtl;

共

陽

極

七

段

顯

示

個

位

數

顯

示

0

|

F

十

六

進

制

數

字

接

七

段

公

共

腳

com

個位數常亮

其餘常滅

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity m_7seg is port

( segin : in std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of v_4disp is

begin

v_7seg0 : v_7seg port map (segin =>segin, segout => segout);

qout <= "0001" ;

end rtl;

共

陽

極

七

段

顯

示

個

位

數

顯

示

0

|

F

十

六

進

制

數

字

接

七

段

公

共

腳

com

注意!

七段個位數

固定常久顯示

未接限流電阻

可能燒毀七段

顯示器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_7seg is port

(ck : in std_logic;

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of m_7seg is

signal fd : std_logic_vector(24 downto 0);

begin

v_7seg0 : v_7seg port map (segin => fd(24 downto 21),segout => segout);

qout <= "0001" when fd(1 downto 0)="00" else "0000";

process(ck) begin

if rising_edge(ck) then

fd <= fd+1;

end if;

end process;

end rtl;

共

陽

極

七

段

顯

示

個

位

數

顯

示

0

|

F

十

六

進

制

數

字

顯

示

時

間

25%

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity v_4disp is port

(d_in : in std_logic_vector(15 downto 0);

sin : in std_logic_vector(1 downto 0);

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of v_4disp is

signal data : std_logic_vector(3 downto 0);

begin

v_7seg0 : v_7seg port map (segin => data,segout => segout);

with sin select

qout <= "1000" when "00" ,

"0100" when "01",

"0010" when "10",

"0001" when "11";

with sin select

data <= d_in(15 downto 12) when "00",

d_in(11 downto 8) when "01",

d_in(7 downto 4) when "10",

d_in(3 downto 0) when "11";

end rtl;

四

位

數

多

工

掃

描

v_4disp

輸

出

入

接

腳

數

29

腳

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity v_4disp is port

(d_in : in std_logic_vector(15 downto 0);

sin : in std_logic_vector(1 downto 0);

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of v_4disp is

signal data : std_logic_vector(3 downto 0);

begin

v_7seg0 : v_7seg port map (segin => data,segout => segout);

with sin select

qout <= "1000" when "00" ,

"0100" when "01",

"0010" when "10",

"0001" when others;

with sin select

data <= d_in(15 downto 12) when "00",

d_in(11 downto 8) when "01",

d_in(7 downto 4) when "10",

d_in(3 downto 0) when others ;

end rtl;

四

位

數

多

工

掃

描

v_4disp

輸

出

入

接

腳

數

29

腳

package

(my_pkg)

加入一個

component

計2個

component

v_7seg

v_4disp

library ieee

;

use ieee

.

std_logic_1164

.

all

;

package

my_pkg

is

component

v_7seg

port

(segin :

in std_logic_vector

(3

downto

0);

segout :

out std_logic_vector

(6

downto

0));

end component

;

component

v_4disp

port

(d_in :

in std_logic_vector

(15

downto

0);

sin :

in std_logic_vector

(1

downto

0);

segout :

out std_logic_vector

(6

downto

0);

qout :

out std_logic_vector

(3

downto

0));

end component

;

m_4disp

四

位

數

多

工

掃

描

顯

示

數

字

1234

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_4disp is port

(

clk : in std_logic;

qout : out std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0) );

end entity;

architecture rtl of m_4disp is

signal fd : std_logic_vector(1 downto 0);

begin

v_4disp0 : v_4disp port map (d_in=>(x"1234"),sin=>fd(1 downto 0),qout=>qout,segout=>segout);

process (clk) begin if rising_edge(clk) then fd<=fd+1; end if; end process; end rtl;

m_7seg

v_4disp

RTL view

v_7seg

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_4disp is port

(

clk : in std_logic;

qout : out std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0) );

end entity;

architecture rtl of m_4disp is

signal fd : std_logic_vector(20 downto 0);

signal

cnt :

std_logic_vector

(15

downto

0);

begin

v_4disp0 : v_4disp port map (d_in=>cnt,sin=>fd(1 downto 0),qout=>qout,segout=>segout);

process (clk) begin if rising_edge(clk) then fd<=fd+1; end if; end process;

process

(fd(20))

begin

if rising_edge

(fd(20))

then

cnt<=cnt+1;

end if

;

end process

;

m_4disp

四

位

數

多

工

掃

描

顯

示

上

數

計

數

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_4disp is port

(

clk : in std_logic;

qout : out std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0) );

end entity;

architecture rtl of m_4disp is

signal fd : std_logic_vector(20 downto 0);

signal

cnt :

std_logic_vector

(15

downto

0);

begin

v_4disp0 : v_4disp port map (d_in=>cnt,sin=>fd(1 downto 0),qout=>qout,segout=>segout);

process (clk) begin if rising_edge(clk) then fd<=fd+1; end if; end process;

process

(fd(20))

begin

if rising_edge

(fd(20))

then

cnt<=cnt+1;

end if

;

end process

;

m_4disp

四

位

數

多

工

掃

描

顯

示

上

數

計

數

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_4disp is port

(

clk : in std_logic;

qout : out std_logic_vector(3 downto 0);

segout : out std_logic_vector(6 downto 0) );

end entity;

architecture rtl of m_4disp is

signal fd : std_logic_vector(20 downto 0);

signal

cnt :

std_logic_vector

(15

downto

0);

begin

v_4disp0 : v_4disp port map (d_in=>cnt,sin=>fd(1 downto 0),qout=>qout,segout=>segout);

process (clk) begin if rising_edge(clk) then fd<=fd+1; end if; end process;

process

(fd(20))

begin

if rising_edge

(fd(20))

then

cnt<=cnt+1;

end if

;

end process

;

m_4disp

四

位

數

多

工

掃

描

顯

示

上

數

計

數

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key_ci is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic; pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : buffer std_logic);

end entity;

architecture rtl of key_ci is

signal Scnt : std_logic_vector(1 downto 0);

signal keyin: std_logic;

begin

keyin <= kin0 or kin4 or kin8; ken <= '1' when pcnt=6 else '0'; key <= kin8 & kin4 & Scnt;

with Scnt select

kout <= "0001“ when "00", "0010" when "01“, "0100“ when "10“, "1000" when "11";

process (pck,keyin) begin if keyin='0' then

pcnt <= "000"

elsif rising_edge (pck) then if pcnt /=7 then pcnt <= pcnt+1; end if; end if; end process; process (clk) begin if rising_edge (clk) then if keyin='0' then Scnt <= Scnt+1; end if; end if; end process; end rtl;

Key_ci

ken=1時按鍵有效(已防彈跳)

key為鍵值

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key_ci is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic; pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : buffer std_logic);

end entity;

architecture rtl of key_ci is

signal Scnt : std_logic_vector(1 downto 0);

signal keyin: std_logic;

begin

keyin <= kin0 or kin4 or kin8; ken <= '1' when pcnt=6 else '0'; key <= kin8 & kin4 & Scnt;

with Scnt select

kout <= "0001“ when "00", "0010" when "01“, "0100“ when "10“, "1000" when others;

process (pck,keyin) begin if keyin='0' then

pcnt <= "000"

elsif rising_edge (pck) then if pcnt /=7 then pcnt <= pcnt+1; end if; end if; end process; process (clk) begin if rising_edge (clk) then if keyin='0' then Scnt <= Scnt+1; end if; end if; end process; end rtl;

Key_ci

ken=1時按鍵有效(已防彈跳)

key為鍵值

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key_ci is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic; pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : buffer std_logic);

end entity;

architecture rtl of key_ci is

signal Scnt : std_logic_vector(1 downto 0);

signal keyin: std_logic;

begin

keyin <= kin0 or kin4 or kin8; ken <= '1' when pcnt=6 else '0'; key <= kin8 & kin4 & Scnt;

process (Scnt) begin case Scnt is when "00" => kout <= "0001"; when "01" => kout <= "0010"; when "10" => kout <= "0100"; when "11" => kout <= "1000"; end case; end process;

process (pck,keyin) begin if keyin='0' then

pcnt <= "000"

elsif rising_edge (pck) then if pcnt /=7 then pcnt <= pcnt+1; end if; end if; end process; process (clk) begin if rising_edge (clk) then if keyin='0' then Scnt <= Scnt+1; end if; end if; end process; end rtl;

Key_ci

ken=1時按鍵有效(已防彈跳)

key為鍵值

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key_ci is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic; pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : buffer std_logic);

end entity;

architecture rtl of key_ci is

signal Scnt : std_logic_vector(1 downto 0);

signal keyin: std_logic;

begin

keyin <= kin0 or kin4 or kin8; ken <= '1' when pcnt=6 else '0'; key <= kin8 & kin4 & Scnt;

process (Scnt) begin case Scnt is

when "00" => kout <= "0001";

when "01" => kout <= "0010";

when "10" => kout <= "0100";

when others => kout <= "1000";

end case;

end process;

process (pck,keyin) begin if keyin='0' then

pcnt <= "000"

elsif rising_edge (pck) then if pcnt /=7 then pcnt <= pcnt+1; end if; end if; end process; process (clk) begin if rising_edge (clk) then if keyin='0' then Scnt <= Scnt+1; end if; end if; end process; end rtl;

Key_ci

ken=1時按鍵有效(已防彈跳)

key為鍵值

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity m_key is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic;

kout : out std_logic_vector(3 downto 0);

seg7_code : out std_logic_vector(6 downto 0));

end entity;

architecture rtl of m_key is

signal key,segin : std_logic_vector(3 downto 0);

signal fd : std_logic_vector(10 downto 0);

signal ken : std_logic;

begin

key_ci0 : key_ci port map(clk=>clk, pck=>fd(10), kin0=>kin0,kin4=>kin4,kin8=>kin8,kout=>kout,key=>key,ken=>ken); v_7seg0 : v_7seg port map(segin=>segin,segout=>seg7_code);

segin <= key when ken='1';

process (clk) begin if rising_edge (clk) then fd <= fd+1; end if; end process; end rtl;

m_Key

(栓鎖)

按鍵，七段顯示

VHDL

共

陽

極

七

段

顯

示

七段解碼

a

b

c

d

e

f

g

A

B

C

D

Segin[3:0]

Segout[6:0]

燈

節

低

電

位

亮

port (segin : in std_logic_vector(3 downto 0); segout : out std_logic_vector (6 downto 0)); end entity;

architecture rtl of v_7seg is begin

with segin select

segout <= "1000000" when x"0", "1111001" when x"1", "0100100" when x"2", "0110000" when x"3", "0011001" when x"4", "0010010" when x"5", "0000010" when x"6", "1111000" when x"7", "0000000" when x“8", "0010000" when x"9", "0001000" when x"a", "0000011" when x"b", "1000110" when x"c", "0100001" when x"d", "0000110" when x"e", "0001110" when others; end rtl;

library ieee;

use ieee.std_logic_1164.all;

use work.my_pkg.all;

entity v_4disp is port

(d_in : in std_logic_vector(15 downto 0);

sin : in std_logic_vector(1 downto 0);

segout : out std_logic_vector(6 downto 0);

qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of v_4disp is

signal data : std_logic_vector(3 downto 0);

begin

v_7seg0 : v_7seg port map (segin => data,segout => segout);

with sin select

qout <= "1000" when "00" ,

"0100" when "01",

"0010" when "10",

"0001" when others;

with sin select

data <= d_in(15 downto 12) when "00",

d_in(11 downto 8) when "01",

d_in(7 downto 4) when "10",

d_in(3 downto 0) when others ;

end rtl;

四

位

數

多

工

掃

描

v_4disp

輸

出

入

接

腳

數

29

腳

library ieee

;

use ieee

.

std_logic_1164

.

all

;

use work

.my_pkg.

all

;

entity

v_2disp

is port

(d_in :

in std_logic_vector

(7

downto

0);

sin :

in std_logic

;

segout :

out std_logic_vector

(6

downto

0);

qout :

out std_logic_vector

(1

downto

0));

end entity

;

architecture

rtl

of

v_2disp

is

signal

data :

std_logic_vector

(3

downto

0);

begin

v_7seg0 : v_7seg

port map

(segin => data,segout => segout);

with

sin

select

qout <= "10"

when

‘0’ ,

"01"

when

others

;

with

sin

select

data <= d_in(7

downto

4)

when

‘0’,

d_in(3

downto

0)

when

others

;

end

rtl;

二

位

數

多

工

掃

描

v_4disp

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key_ci is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic; pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : buffer std_logic);

end entity;

architecture rtl of key_ci is

signal Scnt : std_logic_vector(1 downto 0);

signal keyin: std_logic;

begin

keyin <= kin0 or kin4 or kin8; ken <= '1' when pcnt=6 else '0'; key <= kin8 & kin4 & Scnt;

with Scnt select

kout <= "0001“ when "00", "0010" when "01“, "0100“ when "10“, "1000" when others;

process (pck,keyin) begin if keyin='0' then

pcnt <= "000"

elsif rising_edge (pck) then if pcnt /=7 then pcnt <= pcnt+1; end if; end if; end process; process (clk) begin if rising_edge (clk) then if keyin='0' then Scnt <= Scnt+1; end if; end if; end process; end rtl;

Key_ci

ken=1時按鍵有效(已防彈跳)

key為鍵值

package

(my_pkg)

4個

component

v_7seg

v_4disp

v_2disp

key_ci

use ieee.std_logic_1164.all;

package my_pkg is component v_7seg port

(segin : in std_logic_vector(3 downto 0); segout : out std_logic_vector(6 downto 0));

end component;

component v_4disp port

(d_in : in std_logic_vector(15 downto 0); sin : in std_logic_vector(1 downto 0); qout : out std_logic_vector(3 downto 0); segout : out std_logic_vector(6 downto 0));

end component;

component v_2disp port

(d_in : in std_logic_vector(7 downto 0); sin : in std_logic;

qout : out std_logic_vector(1 downto 0); segout : out std_logic_vector(6 downto 0));

end component;

component key_ci port

(clk,kin0,kin4,kin8,pck : in std_logic;

kout,key : out std_logic_vector(3 downto 0); ken : out std_logic);

end component;

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數，

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，

移位：(

異步載入

)(

順序載入

)

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

• 當按0~9鍵時，十位<=個位

load1

移位：(

異步載入

)(

順序載入

)

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

• 當按0~9鍵時，十位<=個位

load1

個位<=按鍵值

load2

移位：(

異步載入

)(

順序載入

)

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

• 當按0~9鍵時，十位<=個位

load1

個位<=按鍵值

load2

移位：(

異步載入

)(

順序載入

)

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

process

(pck)

begin

if rising_edge

(pck)

then

if

key<=9

then

load1<=ken;

end if;

load2<=load1;

end if

;

end process

;

load1,load2皆是cnt的敏感源；

敏感源不適合用組合邏輯產生，

用正反器防雜訊

• 當按0~9鍵時，十位<=個位

load1

個位<=按鍵值

load2

移位：(

異步載入

)(

順序載入

)

process

(pck)

begin

if rising_edge

(pck)

then

if

key<=9

then

load1<=ken;

end if;

load2<=load1;

if

key=x”b”

then

clr<=ken;

end if;

end if

;

end process

;

p ck

k en

lo ad1

lo ad2

clr

clr亦是cnt的敏感源；

敏感源不適合用組合邏輯產生，

用正反器防雜訊

process

(pck)

begin

if rising_edge

(pck)

then

if

key<=9

then

load1 <= ken;

end if

;

load2<=load1;

if

key=x”b”

then

clr <= ken;

end if

;

end if

;

end process

;

clr,load1,load2皆是cnt的敏感源；

敏感源不適合用組合邏輯產生，

用正反器防雜訊

p ck

k en

lo ad1

lo ad2

clr

• 當按0~9鍵時，

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數，

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

load1

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數，

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

load1

個位<=按鍵值

load2

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數，

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數，

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)(

ck2

)

再按一次b鍵，停止下數，

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)(

ck2

)

再按一次b鍵，停止下數， (

dec=0

)

再按一次b鍵，開始下數。

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)(

ck2

)

再按一次b鍵，停止下數， (

dec=0

)

再按一次b鍵，開始下數。 (

dec=1

)

下數時，下數至0時，停止下數

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)(

ck2

)

再按一次b鍵，停止下數， (

dec=0

)

再按一次b鍵，開始下數。 (

dec=1

)

下數時，下數至0時，停止下數 (

zero=1

,

dec=0

)

• 當按 a鍵時，顯示清除為0。

• 當按0~9鍵時，十位<=個位

個位<=按鍵值

移位：(

異步載入

)(

順序載入

)

• 當按b鍵時，開始下數， (

dec=1

)(

ck2

)

再按一次b鍵，停止下數， (

dec=0

)

再按一次b鍵，開始下數。 (

dec=1

)

下數時，下數至0時，停止下數 (

zero=1

,

dec=0

)

• 當按 a鍵時，顯示清除為0。 (

clr=1

)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity key_asy is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic;

kout : out std_logic_vector(3 downto 0); segout : out std_logic_vector(6 downto 0); qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of key_asy is

signal key : std_logic_vector(3 downto 0);

signal fd : std_logic_vector(12 downto 0);

signal ck2,pck,dec,ken,load1,load2: std_logic;

signal dec_en,clr,zero: std_logic;

signal cnt : std_logic_vector(7 downto 0):=x"00";

signal q : std_logic_vector(1 downto 0);

begin

key_ci0 : key_ci port map(clk=>clk,kin0=>kin0,kin4=>kin4,kin8=>kin8,pck=>pck,kout=>kout,key=>key,ken=>ken); v_2disp0 : v_2disp port map(d_in=>cnt,sin=>fd(0),qout=>q,segout=>segout);

qout<=(”00” & q);

dec_en <= ken when key=x“b” else ‘0’; --是否按b鍵，每按一次b鍵時ken為產生一個正脈波，寬度為pck週期

pck <= fd(15);

zero <= ‘1’when dig=x“0000” else ‘0’; --計數顯示是否為0

process

(ck2)

begin

if

clr='1'

then

cnt <= x"00";

elsif

load1=‘1’

then

cnt(7

downto

4) <= cnt(3

downto

0);

elsif

load2=‘1’

then

cnt(3

downto

0) <= key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=x"0"

then

cnt(3

downto

0) <= x"9";

cnt(7

downto

4) <= cnt(7

downto

4)-1;

else

cnt(3

downto

0) <= cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

當按 a鍵時，顯示清除為0 (

clr=1

)

CLK

clr

D

Q

lo ad

in

cnt[7 :4 ]

CLK

clr

D

Q

lo ad

in

cnt[3 :0 ]

- 1

0

1

dec

loa d1

loa d2

c k2

key

c lr

process

(ck2)

begin

if

clr='1'

then

cnt <= x"00";

elsif

load1=‘1’

then

cnt(7

downto

4) <= cnt(3

downto

0);

elsif

load2=‘1’

then

cnt(3

downto

0) <= key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=x"0"

then

cnt(3

downto

0) <= x"9";

cnt(7

downto

4) <= cnt(7

downto

4)-1;

else

cnt(3

downto

0) <= cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

當按 a鍵時，顯示清除為0 (

clr=1

)

CLK

clr

D

Q

lo ad

in

cnt[7 :4 ]

CLK

clr

D

Q

lo ad

in

cnt[3 :0 ]

- 1

0

1

dec

loa d1

loa d2

c k2

key

c lr

CLK

clr

D

Q

lo ad

in

cnt[7 :4 ]

CLK

clr

D

Q

lo ad

in

cnt[3 :0 ]

- 1

0

1

dec

loa d1

loa d2

c k2

key

c lr

process

(ck2)

begin

if

clr='1'

then

cnt <= x"00";

elsif

load1=‘1’

then

cnt(7

downto

4) <= cnt(3

downto

0);

elsif

load2=‘1’

then

cnt(3

downto

0) <= key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=x"0"

then

cnt(3

downto

0) <= x"9";

cnt(7

downto

4) <= cnt(7

downto

4)-1;

else

cnt(3

downto

0) <= cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

當按 a鍵時，顯示清除為0 (

clr=1

)

CLK

clr

D

Q

lo ad

in

cnt[7 :4 ]

CLK

clr

D

Q

lo ad

in

cnt[3 :0 ]

- 1

0

1

dec

loa d1

loa d2

c k2

key

c lr

process

(ck2)

begin

if

clr='1'

then

cnt <= x"00";

elsif

load1=‘1’

then

cnt(7

downto

4) <= cnt(3

downto

0);

elsif

load2=‘1’

then

cnt(3

downto

0) <= key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=x"0"

then

cnt(3

downto

0) <= x"9";

cnt(7

downto

4) <= cnt(7

downto

4)-1;

else

cnt(3

downto

0) <= cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

當按 a鍵時，顯示清除為0 (

clr=1

)

CLK

clr

D

Q

lo ad

in

cnt[7 :4 ]

CLK

clr

D

Q

lo ad

in

cnt[3 :0 ]

- 1

0

1

dec

loa d1

loa d2

c k2

key

c lr

當按 a鍵時，顯示清除為0 (

clr=1

)

process

(ck2,clr,load1,load2)

begin

if

clr='1'

then

cnt <= x"00";

elsif

load1=‘1’

then

cnt(7

downto

4) <= cnt(3

downto

0);

elsif

load2=‘1’

then

cnt(3

downto

0) <= key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=x"0"

then

cnt(3

downto

0) <= x"9";

cnt(7

downto

4) <= cnt(7

downto

4)-1;

else

cnt(3

downto

0) <= cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

p ck

k en

lo ad1

lo ad2

clr

process

(pck)

begin

if rising_edge

(pck)

then

if

key<=9

then

load1 <= ken;

end if

;

load2<=load1;

if

key=x”b”

then

clr <= ken;

end if

;

end if

;

end process

;

clr,load1,load2皆是cnt的敏感源；

敏感源不適合用組合邏輯產生，

用正反器防雜訊

process

(pck)

begin

if rising_edge

(pck)

then

if

key<=9

then

load1 <= ken;

end if

;

load2<=load1;

if

key=x”b”

then

clr <= ken;

end if

;

end if

;

end process

;

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

clr,ioad1,load2皆是cnt的敏感源；

敏感源不適合用組合邏輯產生，

用正反器防雜訊

process (pck) begin

if (load1='1' or zero=‘1’) then dec <= '0';

elsif falling_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

k en

鍵碼

=b

d ec_ en

p ck

減

1

按

b

一次反相一次

zero

ken2

CLK

D Q

clr

ena

d ec

load1

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

下數至0000時，

dec設為0(停止下數)

load1

process (pck) begin

if (load1='1' or zero=‘1’) then dec <= '0';

elsif falling_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

k en

鍵碼

=b

d ec_ en

p ck

減

1

按

b

一次反相一次

zero

ken2

CLK

D Q

clr

ena

d ec

load1

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

當按b鍵時，

load1

process (pck) begin

if (load1='1' or zero=‘1’) then dec <= '0';

elsif falling_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

k en

鍵碼

=b

d ec_ en

p ck

減

1

按

b

一次反相一次

zero

ken2

CLK

D Q

clr

ena

d ec

load1

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

當按b鍵時，

load1

process (pck) begin

if (load1='1' or zero=‘1’) then dec <= '0';

elsif falling_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

k en

鍵碼

=b

d ec_ en

p ck

減

1

按

b

一次反相一次

zero

ken2

CLK

D Q

clr

ena

d ec

load1

p ck

k en

lo ad1

lo ad2

d ec

反相

p ck

負緣

d ec_ en

ck2

正緣

p ck

負緣

當按b鍵時，

dec設為反相

(下數變為停止下數，

停止下數變為下數)

load1

process (pck) begin if rising_edge (pck) then if key<=9 then load1 <= ken; end if; load2 <= load1; if key=x”b” then clr <= ken; end if; end if; end process; process (clk) begin if rising_edge (clk) then fd <= fd+1; end if; end process; process (pck) begin

if (load1=‘1’ or zero='1‘) then dec <= '0';

elsif rising_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

按數字鍵

產生移位脈波

load1及load2

按數字鍵或下數至00時，

Dec設為0(停止下數)

當按b鍵時，

dec設為反相

(下數變為停止下數，

停止下數變為下數)

除頻電路

process (ck2,clr,load1,loaq2) begin if clr='1' then cnt <= x"00";

elsif load1=‘1')then

cnt(7 downto 4) <= cnt(3 downto 0);

elsif load2=‘1')then

cnt(3 downto 0) <= key;

elsif rising_edge (ck2) then if dec='1' then if cnt(3 downto 0)=x"0" then cnt(3 downto 0) <= x"9"; cnt(7 downto 4) <= cnt(7 downto 4)-1; else cnt(3 downto 0) <= cnt(3 downto 0)-1; end if; end if; end if; end process; end rtl;

process (pck) begin if rising_edge (pck) then if key<=9 then load1 <= ken; end if; load2 <= load1; if key=x”b” then clr <= ken; end if; end if; end process; process (clk) begin if rising_edge (clk) then fd <= fd+1; end if; end process; process (pck) begin

if (load1=‘1’ or zero='1‘) then dec <= '0';

elsif rising_edge (pck) then if dec_en='1' then

dec <= not dec;

end if; end if; end process;

按數字鍵

產生移位脈波

load1及load2

按數字鍵或下數至00時，

Dec設為0(停止下數)

當按b鍵時，

dec設為反相

(下數變為停止下數，

停止下數變為下數)

除頻電路

process (ck2,clr,load1,loaq2) begin if clr='1' then cnt <= x"00";

elsif load1=‘1')then

cnt(7 downto 4) <= cnt(3 downto 0);

elsif load2=‘1')then

cnt(3 downto 0) <= key;

elsif rising_edge (ck2) then if dec='1' then if cnt(3 downto 0)=x"0" then cnt(3 downto 0) <= x"9"; cnt(7 downto 4) <= cnt(7 downto 4)-1; else cnt(3 downto 0) <= cnt(3 downto 0)-1; end if; end if; end if; end process; end rtl;

library ieee

;

use ieee

.

std_logic_1164

.

all

;

use ieee

.

std_logic_unsigned

.

all

;

use work

.my_pkg.

all

;

entity

key43_asy

is

port

(clk,kin0,kin4,kin8 :

in std_logic

;

--5

kout :

out std_logic_vector

(3

downto

0);

--4,9

qout :

out std_logic_vector

(3

downto

0);

--4,13

segout :

out std_logic_vector

(6

downto

0);

--7,20

end entity

;

architecture

rtl

of

key43_asy

is

signal

key :

std_logic_vector

(3

downto

0);

signal

cnt :

std_logic_vector

(7

downto

0):=x"00";

signal

fd :

std_logic_vector

(21

downto

0):="0000000000000000000000";

signal

pck,ck2,ken,dec_en,zero :

std_logic

;

signal

clr,dec,load1,load2 :

std_logic

:='0';

Begin

key43_0 : key43 port map(clk=>clk,pck=>pck,kin0=>kin0,kin4=>kin4,kin8=>kin8,kout=>kout,key=>key,ken=>ken); v_2disp0 : v_2disp port map(d_in=>cnt,sin=>fd(0),qout=>q,segout=>segout);

qout<=("00" & q);

zero<='1' when cnt=0 else '0'; pck<=fd(15);ck2<=fd(20);

process (pck) begin

if rising_edge(pck) then

if key<=9 then load1<=ken; end if;

load2<=load1;

if key=x"b" then clr<=ken; end if; end if; end process; process (clk) begin if rising_edge(clk) then fd <= fd+1; end if; end process;

process (pck,load1,zero) begin

if (zero='1'or load1='1') then dec<='0'; elsif load1='1' then dec<='0';

elsif falling_edge (pck) then

if dec_en='1' then dec<=not dec; end if;

end if;

process

(ck2,clr,load1,load2)

begin

if

clr='1'

then

cnt<=(

others

=>'0');

elsif

load1='1'

then

cnt(7

downto

4)<=cnt(3

downto

0);

elsif

load2='1'

then

cnt(3

downto

0)<=key;

elsif rising_edge

(ck2)

then

if

dec='1'

then

if

cnt(3

downto

0)=0

then

cnt(3

downto

0)<=x"9";

cnt(7

downto

4)<=cnt(7

downto

4)-1;

else

cnt(3

downto

0)<=cnt(3

downto

0)-1;

end if

;

end if

;

end if

;

end process

;

end

rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.my_pkg.all;

entity key_asy is port

(clk : in std_logic;

kin0,kin4,kin8 : in std_logic;

kout : out std_logic_vector(3 downto 0); segout : out std_logic_vector(6 downto 0); qout : out std_logic_vector(3 downto 0));

end entity;

architecture rtl of key_asy is

signal key : std_logic_vector(3 downto 0);

signal fd : std_logic_vector(12 downto 0);

signal ck2,pck,ken,dec_en,zero : std_logic;

signal dec,clr,load1,load2 : std_logic :=‘0’;

signal cnt : std_logic_vector(7 downto 0):=x"00";

signal q: std_logic_vector(1 downto 0);

begin

key_ci0 : key_ci port map(clk=>clk,kin0=>kin0,kin4=>kin4,kin8=>kin8,pck=>pck,kout=>kout,key=>key,ken=>ken); v_2disp0 : v_2disp port map(d_in=>cnt,sin=>fd(0),qout=>qout,segout=>segout);

qout<=(“00” & q);

dec_en <= ken when key=x"b" else '0'; pck <= fd(15);ck2<=fd(20);

zero <= '1'when cnt=x"00" else '0';

process (pck) begin

ifrising(pck) then ken2 <= '1';

if key<=9 then load1 <= ken;

end if; load2<=load1;

if key=x”b” then clr <= ken;

end if;

end if;

end process;

process (clk) begin

if rising_edge (clk) then fd <= fd+1;

end if; end process;

process (pck) begin

if (zero='1' or load1=‘1’) then dec <= '0';

elsif falling_edge (pck) then if dec_en='1' then dec <= not dec;

end if;

end if;

end process;

process (ck2,clr,load1,loaq2) begin if clr='1' then cnt <= x"00";

elsif load1=‘1')then

cnt(7 downto 4) <= cnt(3 downto 0);

elsif load2=‘1')then cnt(3 downto 0) <= key;

elsif rising_edge (ck2) then if dec='1' then if cnt(3 downto 0)=x"0" then cnt(3 downto 0) <= x"9"; cnt(7 downto 4) <= cnt(7 downto 4)-1; else cnt(3 downto 0) <= cnt(3 downto 0)-1; end if; end if; end if; end process; end rtl;

同步載入

• 移位

• 同步載入(同時載入)

• 下數與移位用同一觸發源(ck2)

• 每一按鍵祇能載入一次

ken and key<=9

pck

ck2

ken_pr

ken1

ken_clr

ken_pr

ken1

ken_clr

ken_pr

ken1

ken_clr