Interfacial layer dependence on device property of high-kappa TiLaO Ge/Si N-type metal-oxide-semiconductor capacitors at small equivalent-oxide thickness

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Interfacial layer dependence on device property of high- TiLaO Ge/Si N -type

metal-oxide-semiconductor capacitors at small equivalent-oxide thickness

W. B. Chen and Albert Chin

Citation: Applied Physics Letters 95, 212105 (2009); doi: 10.1063/1.3265947

View online: http://dx.doi.org/10.1063/1.3265947

View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/95/21?ver=pdfcov Published by the AIP Publishing

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Interfacial layer dependence on device property of high-

␬

TiLaO Ge/Si

N-type metal-oxide-semiconductor capacitors at small equivalent-oxide

thickness

W. B. Chen and Albert China兲

Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan

共Received 14 October 2009; accepted 28 October 2009; published online 24 November 2009兲 We have investigated the device property dependence of high dielectric-constant共high-␬兲 TiLaO epitaxial-Ge/Si n-type metal-oxide-semiconductor共n-MOS兲 capacitors on different GeO2and SiO2

interfacial layers. Large capacitance density of 3.3 ␮F/cm2, small equivalent-oxide thickness 共EOT兲 of 0.81 nm and small C-V hysteresis of 19 mV are obtained simultaneously for MOS capacitor using ultrathin SiO₂ interfacial layer, while the device with ultrathin interfacial GeO₂ shows inferior performance of larger 1.1 nm EOT and poor C-V hysteresis of 93 mV. From cross-sectional transmission electron microscopy, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy analysis, the degraded device performance using GeO₂interfacial layer is due to the severe Ge outdiffusion, thinned interfacial GeO₂ and thicker gate dielectric after 550 ° C rapid-thermal anneal. © 2009 American Institute of Physics.关doi:10.1063/1.3265947兴

Germanium共Ge兲 has attracted much attention for metal-oxide-semiconductor field-effect transistor 共MOSFET兲1–14 application due to both higher electron and hole mobility than Silicon 共Si兲. However, the difficult challenges are the high leakage current of small energy band gap 共EG兲 Ge and

the poor interface property with high dielectric-constant共␬兲 material. To lower the leakage current, we pioneered the de-fect free Ge-on-insulator 共GOI or GeOI兲共Ref. 1兲 structure, and the leakage current decreases with decreasing the Ge body thickness.5 Nevertheless, the degraded interface prop-erty is still a tough challenge especially for the Ge n-type MOSFET 共n-MOSFET兲6–12 at a small equivalent oxide thickness共EOT兲. The interface property is highly dependent on high-␬dielectrics, where Al2O3共Ref.1兲 and La2O3共Refs.

8 and11兲 show lower interface trap density than HfO2. This

is related to the different metal-oxygen-Ge and defect formations11after a rapid-thermal anneal共RTA兲. To improve the interface, several passivation methods have been pro-posed such as plasma nitridation,4,8NH3treatment, SiH4

an-nealing, and interfacial GeO2 layer8–10,12–14 at larger EOT,

but small EOT less than 1 nm is needed for 32 nm node and beyond.

In this letter, we have applied the ultrathin GeO2 and

SiO₂ interfacial layers15 into high-␬ TiLaO 共Ref. 16兲 epitaxial-Ge/Si n-type MOS 共n-MOS兲 capacitors, where the ultrathin body Ge of 5 nm is directly grown on Si to reach low leakage current. The TiLaO gate dielectric has the merits of unique negative flatband voltage 共Vfb兲 from La2O3 共Ref.

17兲 and the much higher␬by adding TiO2.16Such negative

Vfbis needed for low threshold voltage 共Vt兲 MOSFET. The

control TaN/TiLaO/Ge/Si n-MOS capacitor without the ul-trathin GeO2or SiO2interfacial layer showed poor EOT and

large V_fbdegradation after a 550 ° C RTA, which is required to activate ion-implanted source-drain in the MOSFET. Such degradations are related to interface reaction and oxygen va-cancy formation18,19that are much improved by inserting the

ultrathin GeO2or SiO2 共Ref.15兲 interfacial layer. However,

the high-␬ TiLaO Ge/Si n-MOS capacitor with interfacial GeO₂ showed much poorer capacitance-voltage 共C-V兲 hys-teresis than that using SiO2at a smaller EOT less than 1 nm.

This is due to the Ge outdiffusion and intermixing of high-␬ TiLaO/GeO₂ as observed by cross-sectional transmission electron microscopy 共TEM兲 and secondary ion mass spec-troscopy共SIMS兲.

After standard cleaning, a 200 nm undoped Si buffer, 5 nm Ge, and 1.5 nm Si capping layer were epitaxial grown on 6 in. p-type Si substrate 共10 ⍀ cm兲 by ultrahigh-vacuum chemical-vapor deposition. After removing the native oxide of Si-capping layer, various thick GeO2 or SiO2 and 5 nm

high-␬ TiLaO 共Ref. 16兲 were deposited by physical vapor deposition and followed by postdeposition annealing at 400 ° C in oxygen ambient to improve gate dielectric quality. Here the ultrathin Si capping is used to prevent Ge oxidation and process loss, where no interfacial Si was found by cross-sectional TEM after device process. Then a 50 nm TaN was deposited and patterned to form the metal gate. The formed gate stack was applied by a 550 ° C RTA that is needed for Ge n-MOSFET fabrication. Finally, Aluminum was depos-ited on wafer backside to form the MOS capacitors. For comparison, control device without GeO₂or SiO₂interfacial layer was also made. The fabricated gate stack was examined by SIMS, TEM, x-ray photoelectron spectroscopy 共XPS兲, and C-V measurements to investigate the physical, chemical bonding, and electrical properties, respectively.

Figure 1 shows the measured C-V characteristics of high-␬ TiLaO Ge/Si n-MOS capacitors with or without the interfacial GeO2 or SiO2 layer. For device without the

in-serted GeO₂ or SiO₂layer, both the capacitance density and

Vfb were severely degraded. Such Vfb roll-off at high

tem-perature was previously reported due to the interface reaction between high-␬and semiconductor.19In contrast, the capaci-tor with GeO2 or SiO2 layer shows much improved Vfb

rolloff even after a 550 ° C RTA. Besides, the needed nega-tive Vfbof⫺0.48 V is obtained and important for low VtGe

n-MOSFET. However, the device with GeO2interfacial layer

a兲_{Also at Nano-Electronics Consortium of Taiwan, Taiwan, R.O.C.}

Elec-tronic mail: [email protected].

APPLIED PHYSICS LETTERS 95, 212105共2009兲

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shows poorer C-V hysteresis of 93 mV at 1.1 nm EOT than the much improved 19 mV hysteresis at smaller 0.81 nm EOT for device using SiO2 interfacial layer, by taking

ac-count of quantum-mechanical effect with parameters of Ge.7 The C-V hysteresis and negative Vfb value are among the

best reported data for Ge n-MOS capacitors at the smallest EOT and after a 550 ° C RTA,1–14to our best knowledge.

We have used TEM to study the better electrical perfor-mance for device using interfacial SiO2 layer. Figures 2共a兲

and2共b兲show the TEM images of TaN/TiLaO/GeO2/Ge/Si

n-MOS structure before and after a 550 ° C RTA. Sharp

GeO2 interfacial layer of 0.76 nm thickness was found for

as-deposited sample but becomes blurred after the 550 ° C

RTA. The high-␬layer is also thicker after the 550 ° C RTA, where intermixing of high-␬ TiLaO and GeO₂ is observed. The thicker high-␬layer explains the lower capacitance den-sity after a 550 ° C RTA. In strong contrast, sharp SiO2

in-terface shown in Fig. 2共c兲 is still preserved even after the 550 ° C RTA.

We have further used SIMS to study the large difference for devices with different interfacial GeO2and SiO2. Figures

3共a兲 and 3共b兲 show the measured SIMS profiles of TaN/ TiLaO on Ge/Si structure with interfacial GeO2 and SiO2

layers, respectively. Severe Ge outdiffusion was found for device structure with interfacial GeO₂ layer after a 550 ° C RTA, while much improved Ge outdiffusion was achieved

using ultrathin SiO2 interfacial layer even at a smaller 0.81

nm EOT.

The degraded interface property with ultrathin interfacial GeO2was also examined by XPS. Figure4shows the Ge 2p3

XPS spectra of TiLaO/GeO₂/Ge/Si n-MOS structure before and after the 550 ° C RTA. The as-deposited sample shows a strong Ge peak at 1217.4 eV, and a small higher energy side peak is attributed to Ge–O bonds of GeO2.20 However, this

Ge–O peak becomes much weaker for the sample after the 550 ° C RTA. This is consistent with the largely thinned GeO2 and intermixed TiLaO/GeO2 interface found from

cross-sectional TEM and the large Ge outdiffusion measured by SIMS. The thinner interfacial GeO2 after the high

tem-perature 550 ° C RTA may be related to the measured reac-tion at 758–589 K,21

GeO_2共s兲+ Ge_共s兲→ 2GeO_共g兲. 共1兲 In contrast, the interface reaction between ultrathin SiO2

layer and Ge is unfavorable due to the much higher bond enthalpy of SiO2共800 kJ/mol兲 than GeO2 共659 kJ/mol兲.22

In conclusion, we have studied the high-␬ TiLaO on Ge/Si MOS structure with GeO₂ and SiO₂ interfacial layers. Low EOT of 0.81 nm, small C-V hysteresis of 19 mV and needed negative Vfbare obtained using ultrathin SiO2

inter-facial layer. The device with ultrathin interinter-facial GeO2shows

inferior device performance of larger EOT and poor C-V hysteresis, which is due to the severe Ge outdiffusion through GeO2 from SIMS profile, thicker gate dielectric

from TEM observation and thinned interfacial GeO2 after a

550 ° C RTA from TEM and XPS analysis.

FIG. 1. 共Color online兲 C-V characteristics of TaN/TiLaO Ge/Si n-MOS capacitors with or without the inserted GeO2and SiO2interfacial layer and

after 450 or 550 ° C RTA. The device size is 100⫻100 ␮m2_.

FIG. 2. Cross-sectional TEM images of TaN/TiLaO/GeO2/Ge/Si n-MOS

capacitors 共a兲 before and 共b兲 after 550 ° C RTA. 共c兲 TaN/TiLaO/SiO2/Ge/Si n-MOS capacitors after 550 °C RTA.

FIG. 3. 共Color online兲 SIMS profile of TaN/TiLaO Ge/Si n-MOS structure with inserted共a兲 GeO2and共b兲 SiO2interfacial layer before and after 550 ° C

RTA.

FIG. 4. 共Color online兲 The Ge 2p3_{XPS spectra of TiLaO}_/GeO 2/Ge/Si

structure before and after 550 ° C RTA.

212105-2 W. B. Chen and A. Chin Appl. Phys. Lett. 95, 212105共2009兲

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This work was supported in part by National Nano Project NSC of Taiwan under Contract No. 97-2120-M-009-008.

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