Stress immunity enhancement of the SiN uniaxial strained n-channel metal-oxide-semiconductor field-effect-transistor by channel fluorine implantation

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Stress immunity enhancement of the SiN uniaxial strained n-channel

metal–oxide–semiconductor ﬁeld-effect-transistor by channel ﬂuorine implantation

Yung-Yu Chen

a,⇑

_{, Chih-Ren Hsieh}

b

_{, Fang-Yu Chiu}

b

a

Department of Electronic Engineering, Lunghwa University of Science and Technology, Guishan, Taoyuan 333, Taiwan b

Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history: Received 7 April 2011

Received in revised form 9 December 2011 Accepted 21 December 2011

Available online 24 January 2012

a b s t r a c t

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to investigate electrical characteristics and stress reliabilities of the n-channel metal– oxide–semiconductor field-effect-transistor (nMOSFET) with HfO2/SiON gate dielectric. Although fluorine incorporation had been used widely to improve device characteristics, however, nearly identical trans-conductance, subthreshold swing and drain current of the SiN CESL strained nMOSFET combining the CFI process clearly indicates that stress-induced electron mobility enhancement does not affect by the fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with fluorine incorporation obviously exhibits superior stress reliabilities due to stronger Si–F/Hf–F bonds formation. The channel hot electron stress and constant voltage stress induced threshold voltage shift can be significantly sup-pressed larger than 26% and 15%, respectively. The results clearly demonstrate that combining the SiN CESL strained nMOSFET with fluorinated gate dielectric using CFI process becomes a suitable technology to further enhance stress immunity.

1. Introduction

As complementary metal–oxide–semiconductor (CMOS) aggressive scaling, high drain current is essential for the high speed circuit operation, which requires high carrier mobility and large oxide capacitance. Therefore, strain technologies and high-permit-tivity (high-k) dielectrics have been successfully integrated with current CMOS technology, in order to increase the carrier mobility and the oxide capacitance, respectively. Hafnium oxide (HfO2) is

the most potential candidate owing to superior characteristics dur-ing investigation of the high-k dielectrics[1]. Unfortunately, bias temperature instability is another serious reliability issue of the metal–oxide–semiconductor ﬁeld-effect-transistors (MOSFETs) with HfO2dielectric due to high defect densities[2]. High defect

densities within the HfO2 dielectric would increase scattering

probability for the channel carriers and result in mobility degrada-tion and drain current reducdegrada-tion[3,4].

Recently, various uniaxial strain technologies have been pro-posed to improve carrier mobility[5,6]. Silicon nitride contact etch stop layer (SiN CESL) is the simplest process to improve carrier mobility among these uniaxial strain technologies, however, large amount of hydrogen during SiN layer deposition would diffuse to the gate stacks to form Si–H/Hf–H bonds and degrade the channel hot electron reliability[7,8].

Although fluorine passivation technology has been widely used to replace weak Si–H bonds within the high-k gate stack to im-prove stress reliabilities[9–11], however, the impact of combining the fluorine passivation effect with the SiN CESL strained n-channel MOSFET (nMOSFET) is seldom investigated yet. Moreover, fluorine implantation is also used for work function engineering in metal gate/high-k dielectric stacks [12]. Fluorine incorporation using channel fluorine implantation (CFI) process prior to the SiN CESL strained nMOSFET fabrication can create Si–F passivated surface to suppress interfacial re-oxidation during the gate stack deposi-tion, which is also beneficial for equivalent oxide thickness scaling [13]. Consequently, electrical characteristics and stress reliabilities of the SiN CESL uniaxial strained nMOSFET combining fluorinated HfO2/SiON (oxynitride) gate stack using CFI process have been

studied in this paper, which is expected to reduce threshold volt-age (VTH) shift during both constant voltage stress (CVS) and

chan-nel hot electron stress (CHES), while maintain high electron mobility simultaneously.

2. Experimental details

nMOSFETs were fabricated on 6-in. p-type (1 0 0) silicon wafer utilizing a conventional self-align process. Before 15 nm sacriﬁcial oxide stripping, several samples were split to the CFI process at 10 keV with 1 1012_cm 2_{dosage, followed by standard cleaning}

with a hydroﬂuoric acid-last process. Relatively low energy and light dosage is mainly to prevent signiﬁcant channel damage and

⇑ Corresponding author. Tel.: +886 2 82093211; fax: +886 2 82095165.

E-mail address:[email protected](Y.-Y. Chen).

Microelectronics Reliability 52 (2012) 995–998

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Microelectronics Reliability

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also to avoid eliminating the SiN CESL induced tensile strain in the channel. One nanometer interfacial SiON and 3.8 nm HfO2 was

formed by rapid thermal process at 800 °C in nitrous oxide (N2O)

ambient and metal organic chemical vapor deposition (CVD) at 500 °C in oxygen ambient, respectively, followed by annealing at 600 °C in nitrogen (N2) ambient for 30 s. A 200 nm poly-Si gate

was then deposited by the low-pressure CVD using silane (SiH4)

gas at 620 °C. After gate electrode patterning and subsequently dopant activation, 300 nm highly tensile strain SiN CESL and 100 nm TEOS passivation layer was deposited using the plasma-enhanced CVD at 300 °C with SiH4 and ammonia (NH3) or N2O,

respectively. Finally, contact hole etching and Al metallization were performed using standard CMOS process. Schematic cross-section of the SiN CESL strained nMOSFETs without and with ﬂuo-rine incorporation using CFI process is shown in Fig. 1, where hydrogen passivation and ﬂuorine passivation is indicated, respec-tively. Electrical properties and reliability characteristics of the SiN CESL strained nMOSFET with HfO2/SiON gate stack were measured

using the Hewlett-Packard (HP) 4156C semiconductor parameter analyzer. Furthermore, the binding energy of the hafnium and ﬂuo-rine atom was extracted from the X-ray photoelectron spectrome-ter (XPS).

3. Results and discussion

Fig. 2shows XPS spectra of the Hf4fsignal for the HfO2/SiON

gate stacks with and without CFI process. The binding energy was calibrated by the C1ssignal at 284.5 eV. The device with

ﬂuo-rinated gate stack obviously increases the binding energy larger than 0.5 eV for both Hf4f5/2and Hf4f7/2signal. Binding energy of

the Hf4f5/2signal increases from 17.64 eV to 18.16 eV, while

bind-ing energy of the Hf4f7/2 signal increases from 16.14 eV to

16.66 eV. Fluorine incorporation into HfO2/SiON gate stack is

fur-ther conﬁrmed due to the conspicuous signal at 685 eV, as shown

in the inset, which means ﬂuorine has been successfully bonded in HfO2.

Fig. 3a presents the transfer curve of the SiN CESL strained nMOSFETs. Initial VTH for the devices with and without ﬂuorine

incorporation is 1.03 and 1.02 V, respectively, which indicates that

(a)

Drain

300nm SiN

Si

Poly-Si

Hf

H

Si

H

Hf

H

Source

HfO

2

Hf

H

Si

H

SiON

(b)

Drain

Si

Poly-Si

Hf

F

Si

H

Hf

F

Source

HfO

2

Hf

F

Si

F

H

SiON

F

_F

F

300nm SiN

H

Fig. 1. Schematic cross-section of the SiN CESL strained nMOSFETs (a) without and (b) with ﬂuorine incorporation.

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 H 2 682 684 686 688 F _1S In te n sit y ( a rb . u n it)

Binding Energy (eV)

Hf

_4f

of the HfO

₂

Intensity (arb. unit)

Binding Energy (eV)

w/o fluorine ΔHf_{4f 5/2}=0.52eV

with fluorine ΔHf_{4f 7/2}=0.52eV

Fig. 2. XPS analysis of the Hf4felectronic spectra for the gate stacks with and

without ﬂuorine incorporation. F1ssignal of the ﬂuorinated gate stack using CFI

process is also shown in the inset.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 250 300 350

Transcondance (

μ

S)

(a) Transfer Curve

L/W=0.3/10μm, V_DS=0.05V

V

_GS

-V

_TH

(V)

0 50 100 150 200 250 300 w/o fluorine with fluorine

Drain Current (

μ

A)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 w/o fluorine with fluorine

(b) Saturation Drain Current

L/W=0.3/10μm

Drain Current (mA)

Drain Voltage (V)

V

_GS

-V

_TH

=1.5V

Fig. 3. (a) Transfer curve and (b) saturation drain current of the SiN CESL strained nMOSFETs with and without ﬂuorine incorporation.

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surface impurity concentration remains the same after ﬂuorine implantation. With ﬂuorine incorporation, maximum transconduc-tance (Gm) and subthreshold swing (SS) has been slightly improved

from 247.88 to 253.72

l

S and from 97 to 96 mV/dec, respectively. Output characteristics of the SiN CESL strained nMOSFETs with and without ﬂuorine incorporation are shown inFig. 3b. With ﬂuorine incorporation, saturation drain current (IDSsat) has been slightly

en-hanced from 1.81 to 1.83 mA.

Nearly identical Gm, SS and IDSsatof the SiN CESL strained

nMOS-FET with and without fluorine incorporation clearly indicates that improvement of electron mobility from the SiN CESL process does not affect by the CFI process. Moreover, negligible improvement of basic electrical characteristics by the CFI process also proves equiv-alent ‘‘as-fabricated’’ dielectric quality for the SiN CESL strained nMOSFETs with and without fluorine incorporation. For the device without fluorine incorporation, large amount of hydrogen during SiN layer deposition would diffuse to the gate stacks and the inter-face between gate stacks and Si substrate to form Hf–H and Si–H bonds, respectively, as shown inFig. 1a. On the other hand, CFI pro-cess is applied prior to the SiN CESL deposition and fluorine exhib-its much higher electronegativity than hydrogen (electronegativity of fluorine and hydrogen is 3.98 and 2.2, respectively[14]), it is hypothesized that negligible hydrogen-passivated bonds can be observed for the SiN CESL strained nMOSFET with fluorinated gate stack using CFI process. Consequently, most bulk and interfacial defects are passivated by the fluorine atoms, which create Hf–F and Si–F bonds in the fluorinated nMOSFET, respectively, as shown inFig. 1b. As a result, as-fabricated dielectric quality can be im-proved either by Si–H/Hf–H bonds for the device without fluorine incorporation or by Si–F/Hf–F bonds for the device with fluorine incorporation, and therefore results in nearly identical electrical characteristics.

Fig. 4compares the VTHshift of the SiN CESL strained nMOSFETs

with and without ﬂuorine incorporation during channel hot elec-tron stress (CHES) at maximum substrate current (Isub). Substrate

current during CHES is also shown in the inset. Incorporating ﬂuo-rine results in nearly identical substrate current, which indicates both generated hot electron concentration and stressed gate volt-age (VGS) are also identical for the nMOSFETs with and without

ﬂuorine incorporation. On the other hand, the CHES degradation is not identical, the SiN CESL strained nMOSFET with ﬂuorine incor-poration obviously reduces VTHshift larger than 26% after 1000 s

CHES. CFI process prior to gate stacks fabrication is easily to create robust Si–F bonds near the interface, which has much stronger

binding energy than Si–H bonds (binding energy of the Si–F bond (5.74 eV) is much higher than the Si–H bond (<3.11 eV) [15]). The SiN CESL strained nMOSFET with ﬂuorine incorporation exhib-its slightly faster VTHshift saturation, which also demonstrates

ro-bust fluorine passivation effect. Moreover, fluorine-incorporated nMOSFET has higher critical energy to create interface traps during CHES[16]. Therefore, the SiN CESL strained nMOSFET with fluori-nated gate stacks using CFI process is valuable to suppress the CHES-induced VTHshift.

Fig. 5shows the VTHshift of the SiN CESL strained nMOSFETs

with and without ﬂuorine incorporation during constant voltage stress (CVS) at VGS VTH= 3 V. The device with ﬂuorine

incorpora-tion obviously reduces VTHshift larger than 15% after 1000 s CVS.

Stress-induced leakage current (SILC) degradation during CVS is also shown in the inset. Measured gate current gradually decreases during CVS for the nMOSFETs, which can be ascribed to the elec-tron trapping. Since CVS-induced VTHshift is mostly related with

bulk traps rather than interface traps, combining the CFI process into the SiN CESL strained nMOSFET obviously enhances passiv-ation of oxygen vacancies to form robust Hf–F bonds (6.75 eV), and suppresses electron trapping and VTHshift[10,15]. As a result,

combining the CFI process with the SiN CESL strained nMOSFET is demonstrated to reduce VTHshift during both CVS and CHES, while

maintain high electron mobility simultaneously. Measured electri-cal parameters and electri-calculated improvement ratio of the SiN CESL strained nMOSFETs with and without ﬂuorine incorporation are summarized inTable 1. 0 200 400 600 800 1000 0 50 100 150 200 250 300 350 400 450 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6 S u b str at e cu rr en t μ_{( A)} Gate Voltage (V) w/o fluorine with fluorine

Threshold Voltage Shift (mV)

Stress Time (s)

V_DS=3V V_GS@max. I_Sub L/W=0.3/10μm

Fig. 4. CHES-induced VTHshift of the SiN CESL strained nMOSFETs with and without

ﬂuorine incorporation. Substrate current is also shown in the inset.

0 200 400 600 800 1000 0 30 60 90 120 150 180 210 0 200 400 600 800 1000 -35 -30 -25 -20 -15 -10 SILC=(I GS-IGS0)/IGS0 Degra d a tio n Ratio (%) Stress Time (s) w/o fluorine with fluorine m L/W=0.3/10μ V GS-VTH=3V

Threshold Voltage Shift (mV)

Stress Time (s)

Fig. 5. CVS-induced VTHshift of the SiN CESL strained nMOSFETs with and without

ﬂuorine incorporation. SILC characteristic is also shown in the inset.

Table 1

Measured electrical parameters and calculated improvement ratio of the SiN CESL strained nMOSFETs with and without ﬂuorine incorporation.

W/o ﬂuorine With ﬂuorine Improvement ratio (%) Maximum Gm 247.88lS 253.72lS 2.36 Subthreshold swing 97 mV/ dec 96 mV/ dec 1.03 Saturation drain current

(VGS VTH= 1.5 V, VDS= 2 V) 1.81 mA 1.83 mA 1.10 CHES-induced VTHShift (VDS= 3 V, VGS@ max. Isubat 1000 s) 399 mV 294 mV 26.32 CVS-induced VTHShift (VGS VTH= 3 V at 1000 s) 206 mV 175 mV 15.05

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4. Conclusions

Although SiN CESL strained nMOSFET has been known to dras-tically improve the electron mobility and basic electrical character-istics due to high channel tensile strain, the results clearly conclude that further combining CFI process with the SiN CESL strained device exhibits negligible improvement on Gm, SS and I DS-sat. Consequently, equivalent electron mobility and ‘‘as-fabricated’’

dielectric quality for the SiN CESL strained nMOSFETs with and without fluorine incorporation can be obtained by fluorine and hydrogen passivation, respectively. On the other hand, fluorine passivation by the CFI process is easily to form stronger Hf–F and Si–F bonds, which has superior stress immunity to against both CVS and CHES. Accordingly, CVS and CHES reliability characteris-tics for the SiN CESL strained nMOSFET can be further improved larger than 15% by the CFI process. Improved device reliabilities clearly indicate that SiN CESL uniaxial strained nMOSFET with fluo-rinated HfO2/SiON gate stack using CFI process becomes a feasible

technology for future CMOS applications. Acknowledgment

This work was supported by the National Science Council of the Republic of China under Grant NSC 100-2221-E-262-021-. References

[1] Kang L, Jeon Y, Onishi K, Lee BH, Qi W-J, Nieh R, Gopalan S, Lee JC. Single-layer

thin HfO2gate dielectric with n+-polysilicon gate. In: IEEE symp VLSI tech.

Honolulu, June 13–15, 2000. p. 44–5.

[2] Kim Y, Gebara G, Freiler M, Barnett J, Riley D, Chen J, et al. Conventional

n-channel MOSFET devices using single layer HfO2 and ZrO2as high-k gate

dielectrics with polysilicon gate electrode. In: IEEE IEDM tech dig, Washington; 2–5 December, 2001. p. 2021–4.

[3] Ota H, Hirano A, Watanabe Y, Yasuda N, Iwamoto K, Akiyama K, et al. Intrinsic origin of electron mobility reduction in high-k MOSFETs – from remote phonon to bottom interface dipole scattering. In: IEEE IEDM tech dig, Washington; 10– 12 December 2007. p. 65–8.

[4] Chau R, Datta S, Doczy M, Doyle B, Kavalieros J, Metz M. High-k/metal-gate stack and its MOSFET characteristics. IEEE Electron Dev Lett 2004;25:408–10. [5] Li M, Yeo KH, Yeoh YY, Suk SD, Cho KH, Kim DW, et al. Experimental investigation on superior PMOS performance of uniaxial strained 1 1 0 silicon nanowire channel by embedded SiGe source/drain. In: IEEE IEDM tech dig, Washington, 10–12 December 2007. p. 899–902.

[6] Wu W-C, Chao T-S, Chiu T-H, Wang J-C, Lai C-S, Ma M-W, et al. Positive bias temperature instability (PBTI) characteristics of

contact-etch-stop-layer-induced local-tensile-strained HfO2 nMOSFET. IEEE Electron Dev Lett

2008;29:1340–3.

[7] Lee KT, Kang CY, Park M-S, Lee BH, Park HK, Hwang HS, et al. A study of strain engineering using CESL stressor on reliability comparing effect of intrinsic mechanical stress. IEEE Electron Dev Lett 2009;30:760–2.

[8] Lu C-S, Lin H-C, Huang J-M, Lee Y-J. Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal–oxide– semiconductor ﬁeld-effect transistors with SiN capping. Appl Phys Lett 2007;90:122110.

[9] Tseng H-H, Tobin PJ, Kalpat S, Schaeffer JK, Ramon ME, Fonseca LRC, et al. Defect passivation with ﬂuorine and interface engineering for Hf-based high-k/ metal gate stack device reliability and performance enhancement. IEEE Trans Electron Dev 2007;54:3267–75.

[10] Hsieh C-R, Chen Y-Y, Lu K-W, Lin G, Lou J-C. Characteristics of ﬂuorinated high-k inter-poly dielectric. IEEE Electron Dev Lett 2010;31:1446–8.

[11] Seo K, Sreenivasan R, Mclntyre PC, Saraswat KC. Improvement in high-k (HfO2/

SiO2) reliability by incorporation of ﬂuorine. In: IEEE IEDM tech dig, San

Francisco, 5–7 December 2005. p. 417–20.

[12] Fet A, Haublein V, Bauer AJ, Ryssel H, Frey L. Fluorine implantation for effective work function control in p-type metal–oxide–semiconductor high-k gate

stacks. J Vacuum Sci Tech B: Microelectron Nanometer Struct

2011;29:01A905.

[13] Chen Y-Y, Hsieh C-R, Chiu F-Y. Constant voltage stress induced charge trapping

and detrapping characteristics of the Si3N4uniaxial strained n-channel metal–

oxide–semiconductor ﬁeld-effect-transistor with ﬂuorinated HfO2/SiON gate

stack. Appl Phys Lett 2011;98:033501.

[14] Pauling L. The nature of the chemical bond. IV. The energy of single bonds and the relative electronegativity of atoms. J Am Chem Soc 1932;54:3570–82. [15] CRC handbook of physics and chemistry. 84th ed. Boca Raton: CRC; 2003. [16] Kasai N, Wright PJ, Saraswat KC. Hot-carrier-degradation characteristics for

ﬂuorine-incorporated nMOSFET’s. IEEE Trans Electron Dev 1990;37:1426–31.