IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 6, JUNE 2002 333
Investigation of Inductively Coupled
Plasma Gate Oxide on Low Temperature
Polycrystalline-Silicon TFTs
Chang-Ho Tseng, Ting-Kuo Chang, Fang-Tsun Chu, Jia-Min Shieh, Bau-Tong Dai, Member, IEEE,
Huang-Chung Cheng, Member, IEEE, and Albert Chin, Senior Member, IEEE
Abstract—By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350 C to achieve excellent gate oxide integrity of low leakage current 5 10 8A cm2(at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5 1011 eV cm2. The superior performance poly-Si TFTs using such a thin ICP oxide were at-tained to achieve a high ON current of 110 A m at = 1 V and = 5 V and the high electron field effect mobility of 231 cm2 V s.
Index Terms—Breakdown field, gate oxide, inductively coupled plasma (ICP), leakage current, thin-film transistor (TFT).
I. INTRODUCTION
D
IRECT oxidation to obtain thin and reliable gate oxide is the future scaling trend of poly-Si thin-film transistors (TFTs) [1]. To achieve this goal, plasma oxidation is one of the potential candidates due to its low process temperatures and good reliability as compared with furnace-formed gate oxides [2]–[7]. Among various plasma deposition methods, inductively coupled plasma (ICP) oxidation is very attractive due to its re-mote plasma source that has smaller plasma damage to gate-oxide during oxidation. In addition, ICP also has advantages of high radical concentrations, low plasma sheath voltage, and the capability of good uniformity over large area that is im-portant for TFT manufacturing. Nevertheless, few studies of the ICP plasma oxide on the low temperature poly-Si TFTs were reported. In this letter, we report a thin 10 nm-thick gate oxide formed by low temperature ICP Ar/O oxidation. By opti-mizing the oxidation condition, excellent gate oxide integrity of high breakdown field, low leakage current and small interface trap density are obtained simultaneously. High performance low temperature poly-Si TFTs are also achieved by using the very thin 10-nm ICP gate oxide. These results suggest the good pos-sibility integrate ICP for next generation TFTs manufacturing with the thin gate oxide.Manuscript received February 11, 2002; revised April 2, 2002. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC-90-2215-E-009-068. The review of this paper was arranged by Editor T-J. King.
C.-H. Tseng, T.-K. Chang, F.-T. Chu, H.-C. Cheng, and A. Chin are with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
J.-M. Shieh and B.-T. Dai are with the National Nano Device Laboratories, Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier S 0741-3106(02)05350-8.
Fig. 1. The breakdown field of ICP oxide film as a function of O percentage in Ar/O gas mixtures. The total gas flow rate is 150 sccm. The breakdown field is determined at a current density of 1A=cm . The inserted figure is the J-E characteristics of gate oxide formed at optimized condition.
II. EXPERIMENTS
The TFTs were fabricated on 4-in thermally oxidized Si wafers. We have first deposited amorphous Si on thermally oxidized Si with 100 nm thickness and crystallized by KrF ex-cimer laser at 320 mJ/cm energy density and 400 C substrate heating [8], [9]. Then, 10 nm-thick gate oxide was formed by ICP oxidation with oxygen and argon mixtures. The Ar/O ICP oxidation was performed at 350 C substrate heating, 5 mtorr plasma pressure and 900 W RF power. To optimize the quality of gate-oxide, various O percentage diluted by Ar were investigated with a fixed total flow rate of 150 sccm. For the comparison, gate oxide formed by PECVD TEOS was also studied with a larger 100 nm thickness and a higher 400 C substrate heating. A 200 nm-thick poly-Si was deposited and patterned for gate electrode. A self-aligned P implantation was performed at a 5 10 cm dosage and 40 keV energy. Dopant activation was performed at 600 C furnace annealing at N ambient for 12 h after depositing a 400-nm oxide pas-sivation layer. Then, 500 nm Al was deposited and patterned as electrode after contact hole definition. Sintering was carried out at 400 C for 30 min. without using hydrogenation plasma to passivate grain boundary or interface.
334 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 6, JUNE 2002
Fig. 2. Quasi-frequency and high-frequency (100 KHz)C–V characteristics of gate oxide formed with 10% O in gas mixtures (a) before and (b) after 600 C furnace annealing for 6 h. The inserted figure shows the interface trap density dependence on O % in gas mixtures.
III. RESULTS ANDDISCUSSION
Fig. 1 shows the breakdown field of gate oxide formed by ICP at various Ar/O ratios. The gate-oxide shows a general trend of improving breakdown field as decreasing O content in plasma gas mixtures except the lowest one. It is well known that noble gas can enhance the dissociation of reaction gas in plasma and the density of oxide. A maximum breakdown field as high as 9.3 MV/cm is achieved by ICP oxidation under an optimum O concentration of 10% in gas mixtures with an oxidation rate of 6.3 Å/min. We also inserted the measured – characteristics of gate oxide formed in the optimized condition. Good gate-oxide quality is evidenced from the small leakage current of 5 A cm at electric field of 8 MV/cm followed on F–N tunneling at higher field. The small pre-F–N tunneling current suggests the low trap density inside the oxide for trap-assisted tunneling, which also suggests high quality oxide can be formed by ICP [10]–[12].
We further used capacitance–voltage ( – ) measurement to evaluate the gate oxide quality. Figs. 2(a) and 2(b) show the qua-sistatic and high frequency – characteristics of ICP oxide formed with 10% O in gas mixtures before and after 600 C post annealing for 6 h used for implantation activation. The
TABLE I
SUMMARY OFDEVICECHARACTERISTICS OFMOS CAPACITOR ANDPOLY-SI
TFTS. THEBREAKDOWNFIELD OFMOS CAPACITOR ISDEFINED AT1A=cm LEAKAGECURRENTDENSITY. THETHRESHOLDVOLTAGE WASDEFINED ATI
OF10NA2 W/LANDV OF1 V. THEI ANDI CURRENTS ARE
MEASURED ATV = 5 VANDV = 1 V. THEMAXIMUMFIELDEFFECT
MOBILITY WASMEASURED ATV = 0:1 V
Fig. 3. I =C and (V 0 V ) transfer characteristics of poly-Si TFTs with ICP Ar/O gate oxide and PECVD TEOS oxide.
obtained oxide charge density and interface trap density from – curves are summarized in Table I. The ICP oxide shows a small interface trap density of 2.6 10 eV cm for as-grown oxide; the annealing has a small effect on interface trap den-sity improvement. These results indicate good oxide interface can be achieved by ICP oxidation and exhibit as good interface quality as previously reported Kr/O plasma oxide [7]. How-ever, as shown in the insert figure, the interface trap density in-creases rapidly as increasing O content in gas mixtures that is consistent with the decreasing trend of breakdown field shown in Fig. 1. The achieved good gate oxide integrity [10]–[12] of low interface trap density, high breakdown electric field and the low leakage current of ICP Ar/O oxide are promising for fur-ther scaling down the gate oxide thickness in low temperature poly-Si TFTs [1]. It is noticed that the inversion capacitance in Fig. 2(a) is less than the value under accumulation. Similar re-sult is also reported in the literature [13] and is attributed to the effect of minority carrier generation rate. Because the oxygen plasma may damage the underneath Si and create traps, this may
TSENG et al.: INVESTIGATION OF INDUCTIVELY COUPLED PLASMA GATE-OXIDE 335
reduce the minority carrier generation rate and gives lower in-version capacitance.
Fig. 3 shows the and ( ) transfer character-istics of poly-Si TFTs with either 10 nm ICP Ar/O gate oxide or 100-nm PECVD TEOS oxide. The important device parame-ters are listed again in Table I for comparison. It notices that the oxide thickness is normalized even though the PECVD oxide re-quires large thickness to achieve good dielectric integrity. The TFT formed by ICP Ar/O oxide exhibits high ON current of 110 A m, low sub-threshold swing of 0.207 V/dec and high electron field effect mobility of 231 cm V s that demon-strate the excellent TFT device performance and are better than PECVD oxide formed TFT. The improved mobility by ICP ox-idation may be caused by the high density O plasma oxox-idation to eliminate the dangling bonds in the polycrystal grain [14]. The good TFT device performance using such a thin 10-nm ICP oxide indicates the high possibility to integrate ICP oxidation for future TFT manufacturing.
IV. CONCLUSIONS
We have investigated the ICP Ar/O oxide for TFT appli-cation. Good gate-oxide integrity of low-leakage current, high breakdown field and low interface trap density are obtained using 10-nm ICP Ar/O oxide. High performance poly-Si TFTs were also achieved by using ICP Ar/O oxide with low threshold voltage and high electron-field effect mobility. Such the high performance poly-Si TFTs are promising for the application of integrated circuits on LCD panel.
ACKNOWLEDGMENT
The authors would like to thank the SRC fo NCTU and NDL for their technical support.
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