中 華 大 學

中 華 大 學 碩士論文

互補式金氧半場效電晶體整合高介電係數介 電層氧化鋯鉿與金屬閘極製程技術之研究與

應用

The investigation and Application of High-k Dielectric HfZrO

and Metal Gate Process

CMOSFETs Technologies

系 所 別：電機工程學系碩士班

學號姓名：M09701051 林智偉 指導教授： 謝焸家 教授 荊鳳德 教授

中 華 民 國 九 十 九 年 六 月

i

摘 要

由於電晶體尺寸不斷微縮，閘極氧化層的厚度也必須隨之減少。 當通道長度小 於 0.1μm，閘極氧化層厚度小於 1.5nm 時，伴隨而來的高閘極漏電流卻使電晶體的 特性變差，並且令元件消耗的功率便大。因此，用高介電常數介電質取代傳統熱氧化 層是無可避免的。雖然高介電常數介電質能有效的減少閘極漏電流，但仍有一些相關

的問題必須解決。在這幾年，高介電常數薄膜氧化鉿(HfO2)由於其出色的熱穩定性和

高的介電係數，而被視為取代氧化矽做為場效電晶體的閘極氧化層來說的最佳材料，

氧化鉿的介電常數會伴隨著該雹膜厚度的減少到 15，並且導致電子遷移率(mobility) 變得越來越差，固定電荷方面的問題，並且導致臨界電壓的不穩定。由於介電係數的 變 化 跟 晶 體 結 構 的 改 變 有 著極 大 的 關 聯 ， 相 較於 氧 化 鉿 (HfO2) ， 以 氧 化 鉿 鋯

(HfxZr1-xO2)當作閘極介電層材料則擁有高電導，且改善電荷捕捉的現象使其降低，在

電性方面，也擁有較高的驅動電流並改善 n 型金屬氧化物半導體的 Vt，並可提升介

電值的品質和可靠度，如漏電流、磁滯、介面密度和優越的晶圓級厚度均勻性，在經 過一連串的負壓測試，如溫度或大偏壓的情況下仍然能夠擁有較長的壽命。在我們的 研究中，我們將金屬(Al、TaN)沉積在介電層之上，並製作了金氧半電融合電晶體。

為了瞭解其被應用為閘極介電層的特性，將會量測元件參數，閘極漏電流、遷移率和

電晶體特性，探討使用了氧化鉿鋯(HfxZr1-xO2)當作閘極介電層材料對於傳統高介電係

數介電層帶來的改善。而我們使用的製程方法，可將不同的金屬應用在金氧半電晶體 所使用的閘極介電層，使外它同時具有簡單，並且與現有超大型積體電路製程技術相 容的優點。

關鍵字:金屬閘極；高介電係數；閘極介電質；鉿為基底金氧半場效電晶體；氧化鋯，

金屬氧化物半導體技術。

ii

Abstract

With the continued scaling of transistor dimensions, the thickness of gate oxide has to be reduced. When the channel length is scaled below 0.1μm and SiO2 gate oxide thickness below 1.5 nm, the high gate leakage current degrades the performance of transistor and enlarges the power consumption of the devices. Therefore, the replacement of conventional thermal oxide with high- dielectrics is inevitable. Although utilizing high- dielectrics reduced the gate leakage current effectively, there are still some issues that we have to overcome. In the past few years, hafnium-based high- dielectrics have been identified as promising materials for SiON replacement due to their excellent thermal stabilities with Si substrate and their high dielectric constants. Howe ver, as HfO2 thickness is reduced, the

-value decreases to 15. Furthermore, HfO2 suffers from mobility degradation, fixed charge issues, threshold voltage instability, and a  variation dependence on crystal structure. Compare to HfO2, the new HfxZr1-xO2 gate dielectric showed: (1) higher transconductance. (2) less charge trapping, (3) higher drive current, (4) lower NMOS Vt, (5) reduced C-V hysteresis, (6) lower interface state density, (7) superior wafer- level thickness uniformity, and (8) longer PBTI lifetime. We gave developed an approach to this high-k dielectric, and deposited metal film: (1) Al, or (2) TaN on Si substrate using PVD followed by oxidation and annealing. The MOS transistors and capacitor devices with HfxZr1-xO2

dielectrics were fabricated. To investigate the characteristic of HfxZr1-xO2 used a gate dielectric, we measured the gate leakage current, mobility and transistor performance.

Therefore, using this approach, we can fabricate HfxZr1-xO2 high-dielectric that is suitable in MOSFETs application. More important, this approach is simple and fully

co mpat ib le wit h c urr e nt VLSI t ec hno lo gy. .

Index Terms:Metal gate; High-k; Gate dielectric; Hf-based MOSFETs; ZrO2.

MOS technology.

iii

Acknowledgement

First of all, I would like to thank my advisors Prof. Ing-Jar Hsieh and Prof. Albert Chin for their fruitful discussions and illuminative suggestions during the period of my working toward master degree. Their inspiration benefits me a lot on the creative ideas, effective schedule control and the integrity to the processing tasks. I am also grateful to ED633 group members for their enthusiastic assistance and cooperation.

Moreover, I am appreciative of the financial and equipment supports form National Science Council, National Nano Device Lab (NDL), and Semiconductor Center of NCTU.

I am also grateful to the those who ever assisted this work.

Finally, I deeply appreciate my family and my girl friend who always support me and give me endless encouragement and spiritual sustenance. Without them, I can’t finish this dissertation.

iv

Contants

Abstract (in Chinese) ……… ………… i

Abstract (in English) ……… ii

Acknowledgement ……… iii

Contents ……… iv

List of Figure ……… vi

List of Tables ……… x

CHAPTER 1 Introduction 1.1 Ba ck gro und a nd M ot uva t io n o f HfZrOx Die lec tr ic s… …… 1

1.2 Br ie f I ntrod uct io n o f High- κ Gate Die lectr ics……… 2

1.3 Brief Introduction of Metal Gate……… 5

1.4 Or ga ni za t io n o f This The s is……… ……… 6

CHAPTER 2 Basic Device Physics and manufacture technology 2.1 Fundamentals of the MOSFET……… 13

2.2 Manufacture technology and experimental tools……… 18

CHAPTER 3 Experimental steps 3.1 MOS capacitors with high-κ dielectrics……… 47

3.2 n-MOSFETs and p-MOSFETs with high-κ dielectrics……… 47

CHAPTER 4 Results and Discussion 4.1 C-V and J-V Characteristics of MIS Measured and Analysis……… 66

4.2 I-V Characteristics of HfZrOx p-MOSFET and n-MOSFET with Metal Gate Measured and Analysis……… 67

CHAPTER 5 Conclusions 5.1 Conclus ions ……… 73

5.2 Suggestions for Future Works……… 73

Reference 75

v

Vita 79

vi

List of Figures

Chapter 1

Fig 1.1 Temperature-composition phase diagram of HfO2-ZrO2.

Fig 1.2 Power consumption and gate leakage current density comparing to the potential reduction in leakage current by an alternative dielectric exhibiting the same equivalent thickness.

Fig 1.3 Current density vs. Capacitance density: The comparison between silicon dioxide and other high-κ materials.

Fig 1.4 Gate leakage reduction by high-k dielectric (B-Y Nguyen, 6^th TRC October 27-28, 2003 Motorola).

Fig 1.5 The energy band diagram of an NMOS device showing the depletion layer in the poly-Si gate (b) The gate depletion layer reduces the gate capacitance in the inversion regime (Cinv).

Fig 1.6 Work functions of several elemental metals in vacuum plotted on a scale ranging from the positions of the conduction band to the valence band of silicon.

Chapter 2

Fig 2.1 Structure of the n-MOS capacitor

Fig 2.2 Low- frequency and high- frequency C-V characteristics of the MOS capacitor with a p-type substrate.

Fig 2.3 Cross-section and circuit symbol of an n-type MOSFET.

Fig 2.4 I-V characteristics of an n-type MOSFET with VG = 5 V (top curve), 4 V, 3 V and 2 V (bottom curve).

Fig 2.5 Charges associated with the SiO2/Si system.

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Fig 2.6 High frequency MOS CV curves illustrating some of the nonidealities that can be present in actual experimental structures ( A, B and C illustrate the effects of interface states with different energy levels in the Si band gap).

Fig 2.7 Tunneling effects in an MOS capacitor structure: (a) F-N tunneling (b) direct tunneling.

Fig 2.8 Measured (dots) and simulated (solid lines) tunneling currents in thin-oxide polysilicon-gate MOS devices(after Lo et al., 1997).

Fig 2.9 Various ways in which dust particles can interfere with photomask patterns.[24].

Fig 2.10 Particle-size distribution curve for English (- - -) and metric (—) classes of clean rooms.[25].

Fig 2.11 Standard implementation of the RCA cleaning procedure.

Fig 2.12 Schematic cross section of a resistance- heated oxidation furnace.

Fig 2.13 Growth of silicon dioxide by thermal oxidation.

Fig 2.14 Basic mechanisms in wet chemical etching.

Fig 2.15 Orientation-dependent etching. (a) Through window patterns on <100>-oriented silicon; (b) through window patterns on <100>-oriented silicon.

Fig 2.16 Schematic of a medium ion implantor.

Fig 2.17 Annealing temperature versus dose for 90% activation of boron and phosphorus.

Fig 2.18 Rapid thermal annealing system that is optically heated.

Fig 2.19 Schematic diagram of chemical- vapor deposition reactors. (a)Hot-wall, reduced-pressure reactor. (b)Parallel-plate plasma deposition reactor.[34]

Fig 2.20 (a) Standard sputtering (b)long through sputtering (c)sputtering with a collimator.

Chapter 3

Fig 3.1 Step 1-RCA clean above the silicon substrate.

Fig 3.2 Step 2-HfZrOx deposition by PVD (Dual E-Gun Evaporation System) and

viii

PDA 500^oC , 550^oC , 600^oC with O2 and N2.

Fig 3.3 Step-3-Al deposition by PDA (Thermal Coater) with thickness 5000Å . Fig 3.4 Step-4-Photo Resist deposition and exposure.

Fig 3.5 Step-5-Develop by FHD-5.

Fig 3.6 Step-6 Etching Al by Al etch solution and remove PR by Acetone.

Fig 3.7 Step-7 cont. Step-2, metal mask set up on the dielectric and deposition TaN by PVD(Sputtering System).

Fig 3.8 Step-8 Remove metal mask.

Fig 3.9 Step-1 RCA clean above the silicon substrate.

Fig 3.10 Step-2 Thermal Oxidation with wet oxide growth(500nm) by Oxidation &

Diffusion Furnaces.

Fig 3.11 Step-3 Photo resist deposition and exposure with First mask.

Fig 3.12 Step-4 Develop by FHD-5 and hard bake for 3 minutes.

Fig 3.13 Step-5 Etching SiO2 on source and drain region by BOE.

Fig 3.14 Step-6 Remove PR by Acetone then execute Ion Implant on S/D region with boron(25KeV at 5 10¹⁵ cm^-2) or arsenic(25KeV at 5 10¹⁵ cm^-2), and activation in N2 at 900°C for 20 minutes.

Fig 3.15 Step-7 Photo resist deposition and exposure with Second mask.

Fig 3.16 Step-8 Develop by FHD-5 and hard bake for 3 minutes.

Fig 3.17 Step-9 Etching SiO2 on gate region by BOE and remove PR by Acetone.

Fig 3.18 Step-10 HfZrOx deposition(20nm) by PVD(Dual E-Gun Evaporation System) and PDA 550^OC in O2 and N2 for 10 min.

Fig 3.19 Step-11 Photo resist deposition and exposure by Third mask.

Fig 3.20 Step-12 Develop by FHD-5 and hard bake for 3minutes.

Fig 3.21 Step-13 Remove HfZrOx on source and drain region by BOE.

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Fig 3.22 Step-14 Remove PR by Acetone and deposition Al by PVD(Thermal Coater) for 500nm.

Fig 3.23 Step-15 Photo resist deposition and exposure by Fourth mask.

Fig 3.24 Step-16 Develop by FHD-5 and hard bake for 3minutes.

Fig 3.25 Step-17 Etching Al by Al etch solution and remove PR by Acetone.

Fig 3.26 Step-18 Remove PR by Acetone Source ,Gate ,and Drain Definition

Fig 3.27 Step-19 Cont. Step-13. Photo resist deposition and exposure by Fourth mask.

Fig 3.28 Step-20 Develop by FHD-5.

Fig 3.29 Step-21 Deposition TaN by PVD(Sputtering System) and remove PR by Acetone.

Fig 3.30 Step-21 Source, Drain, and Gate definition.

Fig 3.31 Gate- last device (4-step process).

Fig 3.32 Gate- first device (1-steo process).

Fig 3.33 Fig 3.33 Agilent 4284 Fig 3.34 Fig 3.34 Agilent 4156C

Chapter 4

Fig 4.1 The C-V characteristics of Al/HfZrOx/ p-Si Device with various PDA temperatures.

Fig 4.2 The J-V characteristics of Al/HfZrOx/p-Si n-MOS with various PDA temperatures.

Fig 4.3 The C-V characteristics of Al/HfZrOx/ n-Si Device with various PDA temperatures.

Fig 4.4 The J-V characteristics of Al/HfZrOx/n-Si n-MOS with various PDA temperatures.

Fig 4.5 The Id-Vd plot of Al gated HfZrOx nMOSFET with a 550°C-PDA condition.

x

Fig 4.6 The Id-Vg plot of Al gated HfZrOx nMOSFET with a 550°C-PDA condition.

Fig 4.7 The Id-Vd plot of Al gated HfZrOx pMOSFET with a 550°C-PDA condition.

List of Tables

Chapter 1

Table 1.1 Some oxide candidates and their material properties.

Table 1.2 Table 1-2 The International Technology Roadmap of ITRS for Semiconductor 2009.

Chapter 2

Table 2.1 Technologies Comparison..

1

Chapter 1

Introduction

1.1 Background and Motivation of HfZrO

Dielectric

Continue the scaling-down of MOS devices has to a constant reduction of the thickness of the gate dielectrics. According to the famous ―Moore’s Law‖, proposed by Gordon Moore in 1965, which states that the number of transistors on integrated circuits doubles every 18 months, pursuing better performance with lower cost is needed. For decades, the progress in the IC industry more or less follows this law. On the other word,

―Moore’s Law‖ is the basis for the overwhelmingly rapid growth of the computing power.

In order to achieve the goal, the scaling down of the device dimension is an inevitable tendency.

Based on the first order current-voltage approximation, the drive current I

D S for a MOSFET can be showed as below

 

2 1

t gs eff n g

dsat V V

L C W

I    ₍₁₎

inv

g t

C ₀ A ₍₂₎

Where C

ox is the gate oxide capacitance and mainly determined by the permittivity and the thickness of the gate insulator. μ

n is the mobility for the electrons or holes, W is the channel width, L

eff is the effective channel length, V

GS is the applied gate-to-source voltage, and V

th is the threshold voltage. All the parameters in the above formula can be properly

2

adjusted to further improve the device driving capability for fulfilling the specification expected.

A lot of research efforts have been focused recently on the investigation of high-κ gate dielectrics. The semiconductor industry has expended much effort to find a suitable high-κ material to replace SiON gate dielectrics. The dielectric constant (κ) of the dielectric film should be at least 12, preferably 25-30. The κ value of the candidate dielectrics tend to vary inversely with the band gap. A list of materials studied in the literature is given in Table 1.1.

In the past few years, Hf-based high-κ dielectrics have been thoroughly investigated to replace the conventional SiO2 to reduce gate leakage current. However, one of the key issues in high-κ gate stack is the high density of bulk traps, which degrade device mob ility and result in poor reliability [1]–[3]. Besides, it has been observed that bulk traps significantly enhance the gate induced drain leakage (GIDL) current in devices with high-κ dielectrics [4]. The HfO2 and ZrO2 have very similar properties and are completely miscible in the solid state [5] as shown in Fig 1.1. Moreover, ultrathin HfO2 only has a medium dielectric constant (κ of 20 or less), which limits its scalability. We recently reported on the development of HfxZr1−xO2 gate dielectric for advanced gate stack application [6]–[10]. The HfxZr1−xO2 has been shown to be a superior gate dielectric to HfO2 based on improved device performance and reliability. Addition of ZrO2 stabilizes the tetragonal phase and enhances the k value in HfxZr1−xO2devices.

1.2 Brief Introduction of High-κ Gate Dielectrics

1.2.1 Choice of High-κ Materials

High-κ gate materials can maintain the same EOT with thicker physical thickness, and is therefore expected drastically reduced direct-tunneling current. From Fig 1.2, the

3

increased physical thickness significant reduces the probability of tunneling across the insulator, and hence, reduces the amount of off- state leakage current density [11]. The relationship between dielectrics constant and thickness is followed:



 



 



high high ox

t

EOT t (3)

There are many potential candidates for replacing SiO2, such as HfO2, ZrO2, Al2O3, Ta2O5

and so on. Which one will emerge as the winner for replacing the silicon dioxide? Since over the past three decades, SiO2 has served as an ideal gate dielectric, its several advantages, such as being amorphous phase through the whole integration processing, high quality interface, and good thermal stability, can indeed serve as a good guide of choosing high-k material (Fig 1.3).

1.2.2 Ideal Gate Dielectric Requirements of Physical Properties

The material that can potentially replace silicon dioxide as gate dielectric in advanced CMOS technologies shall satisfy some requirements

 Good thermal stability in contact with Si, preventing the formation of a thick, low-κ SiOx interfacial layer and the formation of silicide layers;.

 Film morphology (amorphous) and stable process compatibility, In the VLSI process, the thermal budget is an important concern since high temperature changes dielectric phase. Once the gate dielectric material has transformed to polycrystalline from amorphous phase, the large grain boundaries would serve as leakage path, and induce large leakage current.

 Suitable high κ value (12~60), a suitable κ value is indispensable. Those with not enough high κ value could not satisfy to lower the leakage by increasing physical thickness. While those with too high a κ value, in general, would suffer from thermal stability issues and larger fringing field.

 Wide band gap with conduction band offset > 1eV, it is found that most of the high-κ

4

materials do not have wide enough band gap. In contact with silicon and gate electrode, the band gap is closely related to the barrier height for carrier transport. Too low a band gap will lead to intolerably high gate leakage (leakage current ~ exp(-ΔEc)) .

 Gate material compatibility, materials such as metal gates, and metals have been considered for better controllability and better performance.

In this thesis, we focus on the HfO2 and ZrO2 due to its high dielectric constant, large band gap and thermal stability in contact with Si substrate.

1.2.3 Ideal Gate Dielectric Requirements of Electrical Properties

(a) Low interface state density (D_it 510¹⁰/cm² eV^1), and SiO2-like mobility, the interface would affect the carrier mobility in the channel, and from (1.2), mobility degradation is related to poor current drivability. In high-κ, there are so many sources that would reduce mobility, such as fixed charge, remote phonon, interfacial dipoles, remote surface roughness, surface roughness and phase separation crystallization. And most of them can be avoided by imp roving process technology.

(b) Tinv<1nm,

(c) J10^3A/cm²@ VDD, (d) VFB and hysteresis < 20mV, (e) No C-V dispersion,

(f) Reliability issue.

To serve as a new gate dielectric, we must also take into consideration electrical reliabilities, such as stress- induced leakage current (SILC), time dependent dielectric breakdown (TDDB), hot carrier aging, bias temperature instability and charge trapping issues.

1.2.4 Roadmap of Gate Dielectric

5

Table 1-2 is the roadmap of 2009 ITRS (International Technology Roadmap for Semiconductor) for the high-performance logic technology. After 2009, the requirement of EOT even reduces to less than 1 nm. It would be a big challenge because the leakage current is too large to be acceptable for SiO2 under such a thin thickness (Fig. 1.4).

Replacing SiO2 by SiON could effectively reduce leakage current. Therefore, we need to aggressively seek a feasible high-k material to replace SiO2

1.3Brief Introduction of Metal Gate

In scaling the transistor gate length LG below 50nm, problems relate to poly-silicon (poly-Si) gate depletion and high gate resistance become very significant. As shown in Fig 1.5, the gate depletion layer increases the equivalent oxide thickness (EOT) and reduces the gate capacitance in the inversion regime (Cinv). This compromises device performance due to a lower inversion charge density or a lower effective gate voltage.

To reduce these problems, the active dopant density in the poly-Si gate material must be increased (Fig. 5(b)). This is nevertheless limited by the saturation active dopant density in p⁺ or n⁺ doped poly-Si [12]. In addition, increasing the dopant density in poly-Si worsens the dopant penetration problem [13]. There is therefore immense interest in replacing conventional poly-Si gates with metal gates [14-17]. A metal gate material not only eliminates the gate depletion (Fig. 5(b)) and boron penetration problems but also reduces the gate sheet resistance. Metals are also generally more compatible with alternative gate dielectric or high-permittivity (high-κ) gate dielectric materials than poly-Si.

1.3.1 Material selection

The metal work function is a very important consideration in the selection of metal gate materials for device integration because it directly affects the threshold voltage Vth (Equation 4) and performance of a transistor (Equation 5).

6

(4)

(5)

As a result, appropriate metal gate materials have to be chosen so that the threshold voltages for n- and p-channel transistors are complementary and sufficiently small to achieve high transistor drive currents for a given supply voltage. The required gate work functions for n- and p-channel transistors are close to the conduction and valence bands of silicon, respectively [14]. Fig. 1.6 shows the work function of several elemental metals in vacuum plotted on a scale ranging from the positions of the conduction band to the valence band of silicon. . In addition of the elemental metals, other metallic materials such as metal silicides [18, 19], metal nitrides [15-17], metal oxides metal alloys are also considered as potential metal gate candidates. The work function can be varied by changing the composition of the films. In this thesis, we use titanium nitride (TaN) or Aluminum as the gate electrodes, because of its high thermal stability and low resistivity.

1.4 Organization of this thesis

This thesis is organized into the following chapters:

In chapter 1, overview of CMOSFETs , how to choice high-κ materials and exposition about metal gate.

In chapter 2, some basis about semiconductor and field-effect transistor are briefly introduced. Besides, some manufacture technology and experimental tools is also included in this chapter.

7

In chapter 3, describe the step of MIS and C-MOSFET with high-k dielectric and metal gate fabrication process.

In chapter 4, show measuring tools and we discuss the characteristics of HfZrOx

insulator by Metal-Insulator-Semiconductor (MIS) capacitors and CMOSFET.

Finally, conclusions and future works as well as suggestion for further research are given in chapter 5.

8

Fig 1.1 Temperature-composition phase diagram of HfO2-ZrO2

Fig 1.2 Power consumption and gate leakage current density comparing to the potential reduction in leakage current by an alternative dielectric exhibiting the same equivalent thickness.

9

Fig 1.3 Current density vs. Capacitance density: The comparison between silicon dioxide and other high-κ materials.

Fig 1.4 Gate leakage reduction by high-k dielectric (B-Y Nguyen, 6^th TRC October 27-28, 2003 Motorola).

10

(a)

(b)

Fig 1.5 (a) The energy band diagram of an NMOS device showing the depletion

layer in the poly-Si gate (b) The gate depletion layer reduces the gate capacitance in the inversion regime (Cinv).

11

Fig 1.6 Work functions of several elemental metals in vacuum plotted on a scale ranging from the positions of the conduction band to the valence band of silicon.

Table 1-1 Some oxide candidates and their material properties.

12

Manufacturable solutions exist, and are being optimized Manufacturable solutions are k nown Interim solutions are k nown 

Manufacturable solutions are NOT known

Table 1-2 The International Technology Roadmap of ITRS for Semiconductor 2009.

Ye ar in Production 2009 2010 2011 2012 2013 2014 2015

DRAM 1/2 Pitch (nm) 50 44 40 36 31 27 24

MPU/ASIC 1/2 Pitch (nm) 54 45 38 32 27 24 21

Physical Lgate for High Pe rformance logic (nm)

29 27 24 22 20 18 17

EOT:Equivalent Oxide Thickness (nm)

Extended planar bulk 1 0.95 0.88 0.75 0.65 0.55 0.53

UTB FD 0.7 0.68 0.6

MG 0.77

V_t,sat: Saturation Threshold Voltage (mV)

Extended Planar Bulk 285 289 294 291 295 309 302

UTB FD 221 221 220

MG 206

Jg,limit: Maximum gate leak age current density (k A/cm²)

Extended Planar Bulk 0.65 0.83 0.9 1 1.1 1.2 1.3

UTB FD 1.1 1.2 1.3

DG 1.3

I_d,sat: NMOS Drive current (μA/μm)

Extended Planar Bulk 1210 1200 1190 1300 1450 1580 1680

UTB FD 1470 1520 1670

MG 1490

13

Chapter 2

Basic Device Physics and Process Technology

2.1 Fundamentals of the MOSFET

The fundamental physics of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is briefly described in this chapter. Because of its relatively small size, thousands of devices can be fabricated in a single integrated circuit. The MOSFET is used extensively in digital circuit applications. It is the core of integrated circuit design at the present time.

2.1.1 C-V characteristics of the MOS device

The MOS capacitor consists of a Metal-Oxide-Semiconductor structure as illustrated in Fig. 2.1. Shown is the semiconductor substrate with a thin oxide layer and a top metal contact. A second metal layer forms an ohmic contact to the back of the semiconductor and is called the bulk contact. The structure shown has a p-type substrate. We will refer to this as an n-type MOS capacitor since the inversion layer contains electrons.

The MOS capacitor structure is the heart of the MOSFTET. A great deal of information about the MOS device and the oxide-semiconductor interface can be obtained from the capacitance versus voltage (C-V) characteristics of the device. The capacitance of a device is defined as

(6)

where dQ is the magnitude of the differential change in charge on one plate as a function of the differential change in voltage dV across the capacitor. The capacitance is a

14

small-signal or ac parameter and is measured by superimposing a small ac voltage on an applied dc gate voltage. The capacitance, then, is measured as a function of the applied dc gate voltage.

There are three operating conditions of interest in the MOS capacitor: accumulation, depletion and inversion. Fig 2.2 shows the ideal C-V characteristics of the MOS capacitor with a p-type substrate. The threshold voltage (Vth) is given as Equation (4). The point on the curve that corresponds to the flat-band condition is of interest. The flat-band condition occurs between the accumulation and depletion conditions. The capacitance at flat-band (CFB) is given by

(7)

where LD = (εsVth/qNa)1/2 is the Debye length. The low- frequency and high- frequency limits of the C-V characteristics are also shown in Fig 2.1. In general, high frequency corresponds to a value on the order of 1 MHz and low frequency corresponds to values in the range of 5 to 100 Hz.

2.1.2 MOSFET I-V characteristics

The n-type MOSFET consists of a source and a drain, two highly conducting n-type semiconductor regions, which are isolated from the p-type substrate by reversed-biased p-n diodes. A metal or poly-crystalline gate covers the region between source and drain. The gate is separated from the semiconductor by the gate oxide. The basic structure of an n-type MOSFET and the corresponding circuit symbol are shown in Fig 2.3.

As can be seen in the figure, the source and drain regions are identical. It is the applied voltages, which determine which n-type region provides the electrons and becomes the source, while the other n-type region receives the electrons and becomes the drain. The

15

voltages applied to the drain and gate electrode as well as to the substrate, by means of a back contact, are referred to the source potential, as also indicated Fig 2.3.

The voltage applied to the gate controls the flow of electrons from the source to the drain. A positive voltage applied to the gate attracts electrons to the interface between the gate dielectric and the semiconductor. These electrons form a conducting channel called the inversion layer. No gate current is required to maintain the inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is that the applied gate voltage controls the current between drain and source. The typical I-V characteristics of a MOSFET are shown in Fig. 2.4.

2.1.3 Defects in the Si/SiO₂ system

Silicon dioxide forms critical components of silicon devices, serves as insulation layers. The silicon dioxide and oxide-silicon interface are never completely electrically neutral. There can be mobile ionic charges, electrons, or holes trapped in the oxide layer.

There can also be fabrication-process-induced fixed oxide charges near the oxide-silicon interface. Since every device has some regions that are covered by silicon dioxide, the electrical characteristics of a device are very sensitive to the density and properties of the charges inside its oxide regions and at its silicon-oxide interface.

The nomenclature for describing the charges associated with the silicon dioxide in real devices is standardized in 1978 [20]. The net charge per unit area is donated by Q.

Thus, Qm denotes the mobile charge per unit area, Qot denotes the oxide trapped charge per unit area, Qf denotes the fixed oxide charge per unit area, Qit denotes the interface trapped charge per unit area. The names and location of these charges are illustrated in Fig 2.5.

These charges cause shifts and distortions in C-V curves because they require gate charge QG to balance them. Fig 2.6 illustrates these effects on the ―ideal‖ high frequency

16

CV curve. Qf is a fixed positive charge that is present in the oxide, near the SiO2/Si interface. This shows up as a lateral shift in CV curve, with the magnitude of the shift simply given by qQf / Cox.

If mobile charge (Qm) or oxide trapped charge (Qot) are present, they produce a similar effect to Qf. That is, they cause a lateral shift in the C-V curve. The only difference is that these charges are usually not located directly at the SiO2/Si interface and so the magnitude of the shift they cause is reduced in proportion to their distance away from the interface.

The ―distorted‖ C-V curve shown in Fig 2.6 illustrates what happens when interface traps Qit are present. These traps can have energy levels through out the forbidden band.

As applied gate voltage causes the semiconductor surface to move from accumulation to depletion to inversion, sweeping out a C-V curve, EF at the

semiconductor surface will move from one band edge to the other. As a result, the Qit traps will fill and empty as EF moves through their energy levels. As this happens, the

C-V curve will distort from its ideal shape. The form of the distortion depends on the density and energy levels of the Qit traps.

2.1.4 Tunneling effects

Consider an MOS capacitor as discussed in chapter 2.1. When a large positive bias is applied to the gate electrode, electrons in the strongly inverted surface can tunnel into or through the oxide layer and hence give rise to a gate current. Two kinds of tunneling effects are described as below:

 Fowler-Nordheim tunneling

Fowler-Nordheim (FN) tunneling occurs when electrons tunnel into the conduction band of the oxide layer [20]. Fig 2.7(a) illustrates F-N tunneling of

17

electrons from the silicon surface inversion layer. For the simple case where the effects of finite temperature and image- force barrier lowering are ignored the tunneling current density is given by

(8)

where constants A and B are given by

,

(9)

h is the Planck constant, ħ is the reduced Planck constant, q is the electronic charge, Eox is the oxide field at the tunneling interface, mox is the effective mass in the oxide and φ is the potential barrier height.

Equation (8) shows that F-N tunneling current is characterized by a straight line in a plot of log( J/Eox²) versus 1/ Eox. At an oxide field of 8 MV/cm, the measured F-N tunneling current density is about 5E-7 A/cm², which is very small. Thus, for normal device operation, this tunneling current is negligible.

 Direct tunneling

If the oxide layer is very thin, < 4 nm, then, instead of tunneling into the conduction band of the SiO2 layer, electrons from the inverted silicon surface can tunnel directly through the forbidden energy gap of the SiO2 layer. This is illustrated in Fig 2.7(b). The direct tunneling current (JDT) can be described with the following model reported by Schuegraf and Hu [22]:

(10)

where Vox is the oxide voltage. Both A and B in Equation (10) have the same expressions as in Equation (9), i.e., they have the same dependence on the barrier

18

height (φ) and the effective mass (mox). To obtain the barrier height and effective mass in the direct tunneling regime, a best fitting to the experimental data with equation (10) is carried out. The range of the fitting is chosen from 0.5 to 1.0 V. In this range, the direct tunneling is the dominant tunneling mechanism [23]. The direct-tunneling current can be very large for thin oxide layers. Fig 2.8 is a plot of the measured and simulated thin-oxide tunneling current versus voltage in polysilicon-gate MOSFETs (Lo et al., 1997).

2.2 Manufacture technology and experimental tools

2.2.1 The Clean Room

An IC fabrication facility requires a clean p rocessing room, especially in the area used for lithography. The need for such a clean room arises because dust particles in the air can settle on semiconductor wafers and lithographic masks and can cause defects in the devices, which result in circuit failure. For example, a dust particle on a semiconductor surface can disrupt the single-crystal growth of an epitaxial film, causing the formation of dislocations.

A dust particle incorporated into the gate oxide can result in enhanced conductivity and cause device failure due to low breakdown voltage. The situation is even more critical in the lithographic area. When dust particles adhere to the surface of a photomask, they behave as opaque patterns on the mask, and these patterns will be transferred to the underlying layer along with the circuit patterns on the mask. Fig 2.9 shows three dust particles on a photomask.[24] Particle 1 may result in the formation of a pinhole in the underlying layer. Particle 2 is located near a pattern edge and may cause a constriction of current flow in a metal runner. Particle 3 can lead to a short circuit between the two conducting regions and render the circuit useless.

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In a clean room, the total number of dust particles per unit volume must be tightly controlled along with the temperature and humidity. Fig 2.10 shows the particle-size distribution curves for various classes of clean rooms. We have two systems to define the classes of clean room.[25] For the English system, the numerical designation of the class is taken from the maximum allowable number of particles 0.5μm and larger, per cubic foot.

For the metric system, the class is taken from the logarithm (base 10) of the maximum allowable number of particles 0.5 ㎛ and larger, per cubic meter. For example, a class 100 clean room (English system) has a dust count of 100 particles/ft³ with particle diameters of 0.5 ㎛ and larger, whereas a class M 3.5 clean room (metric system) has a dust count of 103.5 or about 3500 particles/㎥ with particle diameters of 0.5 ㎛ or large. Since 100 particles/ft³= 3500 particles/㎥, a class 100 in English system corresponds to a class M 3.5 in the metric system.

Since the number of dust particles increases as particle size decreases, a more stringent control of the clean room environment is required when the minimum feature lengths of ICs are reduced to the deep-submicron range. For most IC fabrication areas, a class 100 clean room is required, that is, the dust count must be about four orders of magnitude lower than that of ordinary room air. However, for the lithography area, a class 10 clean room or one with a lower dust count is required.

2.2.2Wafer Cleaning

Wafer cleaning is usually accomplished today either using immersion of cassettes of wafers into cleaning baths or through chemical sprays.

The standard implementation of the RCA cleaning procedure is shown in Fig 2.11.

Options include the addition of ultrasonic agitation to the SC-1 or SC-2 solutions, using DI water for the rinses, the addition of a 100:1 H2O/HF step between the SC-1 and SC-2

20

solutions (with DI water rinses before and after the HF step), or the addition of a 100:1 H2O/HF step at the end of the cleaning procedure (followed by another DI water rinse).

The additional 100:1 H2O/HF steps are designed to remove the c hemical oxide layers that are grown during the RCA cleaning steps. Removing these oxides remains a controversial option. The advantage is that any impurities contained in the oxide are stripped by the 100:1 H2O/HF step. However this step leaves the silicon surface hydrogen terminated which is not particularly stable, which makes it more susceptible to absorbing additional contaminants during subsequent processing.

2.2.3 Thermal Oxidation

Semiconductors can be oxidized by various methods. These include thermal oxidation, electrochemical anodization, and plasma reaction. Among these methods, thermal oxidation is by far the most important for silicon devices. It is the key process in modem silicon integrated-circuit technology. For gallium arsenide, howeve r, thermal oxidation results in generally nonstoichiometric films. The oxides provide poor electrical insulation and semiconductor surface protection. Consequently, these oxides used concentrate on silicon technology.

The basic thermal oxidation setup is show in Fig 2.12. The reactor consists of a resistance-heated furnace, a cylindrical fused-quartz tube containing the silicon wafers held vertically in a slotted quartz boat, and a source of either pure dry oxygen or pure water vapor. The loading end of the furnace tube protudes into a vertical flow hood where a filtered flow of air is maintained. Flow is directed as shown by the arrow in Fig 2.12. The hood reduces dust and particulate matters in the air surrounding the wafers and minimizes contamination during wafer loading. The oxidation temperature is generally in the range of 900°-1200°C and the typical gas flow rate is about 1 liter/min. The oxidation system uses

21

microprocessors to regulate the gas flow sequence, to control the automatic insertion and removal of silicon wafers, to ramp the temperature up (i.e., to increase the furnace temperature linearly) from a low temperature to the oxidation temperature so that the wafers will not warp due to sudden temperature change, to maintain the oxidation temperature to within ± 1°C, and to ramp the temperature down when oxidation is completed.

 Kinetics of Growth

The following chemical reactions describe the thermal oxidation of silicon in oxygen or water vapor:

solid O2 gas SiO2solid

Si   (10)

solid 2H2O gas SiO2solid 2H2 gas

Si    (11)

The silicon-silicon dioxide interface moves into the silicon during the oxidation process.

This creates a fresh interface region is show in Fig 2.13

2.2.4 Optical lithography technology

Lithography is the process of transferring patterns of geometric shapes on a mask to a thin layer of radiation-sensitive material (called resist) covering the surface of a semiconductor wafer.’ These patterns define the various regions in an integrated circuit such as the implantation regions. The contact windows, and the bonding-pad areas.

 Exposure tools

The pattern transfer process is accomplished by using a lithographic exposure tool.

The performance of an exposure tool is determined by three parameters: resolution, registration, and throughput. Reo1ution is the minimum feature dimension that can be transferred with high fidelity to a resist film on a semiconductor wafer. Registration is a

22

measure of how accurately patterns on successive masks can he aligned (or overlaid) with respect to previously defined patterns on the wafer Throughput is the number of wafers that can be exposed per hour for a given mask level.

There are basically two optical exposure methods: shadow printing and projection printing[26][27]. Shadow printing may have the mask and wafer in direct contact with one another as in contact printing, or in close proximity as in proximity printing.

 Mask

Masks used for IC manufacturing are usually reduction reticles. The first step in mask making is to use a computer-aided design (CAD) system in which designers can completely describe the circuit patterns electrically. The digital data produced by the CAD system then drives a pattern generator, which is an electron-beam lithographic system that transfers the patterns directly to electron-sensitized mask. The mask consists of a fused silica substrate covered with a chrominum layer. The circuit pattern is first transferred to the electron-sensitized layer (electron resist), which is transferred once more into the underlying chrominum layer for the finished mask.

The standard-size mask substrate is a fused silica plate 15×15cm square, 0.6cm thick.

The size is needed to accommodate the lens field sizes for 4：1 or 5：1 optical exposure tools, whereas the thickness is required to minimize pattern placement erro rs due to substrate distortion. The fused silica plate is needed for its low coefficient of thermal expansion, its high transmission at shorter wavelengths, and its mechanical strength.

One of the major concerns about masks is the defect density. Mask defe cts can be introduced during the manufacture of the mask or during subsequent lithographic processes.

Even a small mask-defect density has a profound effect on the final IC yield.

 Photoresist

The photoresist is a radiation-sensitive compound. Photoresists can he classified as

23

positive and negative, depending on how they respond to radiation. For positive resists, the exposed regions become more soluble and thus more easily removed in the development process. The net result is that the patterns formed (also called images) in the positive resist are the same as those on the mask. For negative resists, the exposed regions become less soluble, and the patterns formed in the negative resist are the reverse of the mask patterns.

Positive photoresists consist of three components: a photosensitive compound, a base resin, and an organic solvent. Prior to exposure, the photosensitive compound is insoluble in the developer solution. After exposure, the photosensitive compound absorbs radiation in the exposed pattern areas, changes its chemical structure, and becomes soluble in the developer solution. After development, the exposed areas are removed.

Negative photoresists are polymers combined with a photosensitive compound. After exposure, the photosensitive compound absorbs the optical energy and converts it into chemical energy to initiate a polymer linking reaction. This reaction causes cross linking of the polymer molecules. The cross-linked polymer has a higher molecular weight and becomes insoluble in the developer solution. After development, the unexposed areas are removed. One major drawback of a negative photoresist is that in the development process, the whole resist mass swells by absorbing developer solvent. This swelling action limits the resolution of negative photoresists.

For deep UV lithography (e.g., 248 and 193 nm), we cannot use conventional photoresists because these resists require a high-dose exposure in deep UV, which will cause lens damage and lower throughput. The chemical-amplified resist (CAR) has been developed for the deep UV process. CAR consists of a photo-acid generator. A resin polymer, and a solvent. CAR is very sensitive to deep UV radiation and the exposed anti unexposed regions differ greatly in their solubility in the developer solution.

 Pattern Transfer

24

The wafer is placed in a clean room, which, typically, is illuminated with yellow light, since photoresists are not sensitive to wavelengths greater than 0.5 ㎛ . To ensure satisfactory adhesion of the resist the surface must be changed from hydrophilic to hydrophobic. This change can be made by the application of an adhesion promoter, which can provide a chemically compatible surfce for the resist. The most common adhesion promoter for silicon ICs is hexa- methylene-di-siloxane (HMDS). After the application of this adhesion layer, the wafer is held on a vacuum spindle, and 2-3 cc of liquidous resist is applied to the center of wafer. The wafer is then rapidly accelerated up to a constant rotational speed, which is maintained for about 30 seconds. Spin speed is generally in the range of 1000 - 10,000 rpm to coat a uniform film about 0.5 to 1 ㎛ thick. The thickness of photoresist is correlated with its viscosity.

After the spinning step, the wafer is given a soft bake (typically at 90°~120°C for 60-120 seconds) to remove the solvent from the photoresist film and to increase resist adhesion to the wafer. The wafer is aligned with respect to the mask in an optical lithographic system, and the resist is exposed to UV light. The photoresist development is usually done by flooding the wafer with the developer solution. The wafer is then rinsed and dried. After development, a postbaking at ~100°-180°C may be required to increase the adhesion of the resist to the substrate. The wafer is then put in an ambient that etches the exposed insulation layer but does not attack the resist. Finally, the resist is stripped, leaving behind an insulator pattern that is the same as the opaque image on the mask.

2.2.5 Wet Chemical Etching

Wet chemical etching is used extensively in semiconductor processing. Starting from the sawed semiconductor wafers, chemical etchants are used for lapping and polishing to give an optically flat, damage- free surface. Prior to thermal oxidation or epitaxial growth,

25

the semiconductor wafers are chemically cleaned to remove contamination that results from handling and storing. Wet chemical etchings are especially suitable for blanket etches (i.e., over the whole wafer surface) of polysilicon, oxide, nitride, metals, and Ⅲ-Ⅴ compounds.

The mechanisms for wet chemical etching involve three essential steps, as illustrated in Fig.2.14: the reactants are transported by diffusion to the reacting surface, chemical reactions occur at the surface, and the products from the surface are removed by d iffusion.

Both agitation and the temperature of the etchant solution will influence the etch rate, which is the amount of film removed by etching per unit time. In IC processing, most wet chemical etchings proceed by immersing the wafers in a chemical solution or by spraying the wafers with the etchant solution. For immersion etching, the wafer is immersed in the etch solution, and mechanical agitation is usually required to ensure etch uniformity and a consistent etch rate. Spray etching has gradually replaced immersion etching because it greatly increases the etch rate and uniformity by constantly supplying fresh etchant to the wafer surface.

For semiconductor production lines, highly uniform etch rates are important. Etch rates must be uniform across a wafer, from wafer to wafer, from run to run, and for any variations in feature sizes and pattern densities. Etch rate uniformity is given by:

rate 100%

etch minimum rate

etch maximum

rate) etch minimum -

rate etch (maximum y(%)

unifformit rate

Etch 

  (12)

 Silicon Etching

For semiconductor materials, wet chemical etching usually proceeds by oxidation, followed by the dissolution of the oxide by a chemical reaction. For silicon, the most commonly used etchants are mixtures of nitric acid (HNO3) and hydrofluoric acid (HF) in water or acetic acid (CH3COOH). Nitric acid oxidizes silicon to form a SiO2 layer[28]. The

26

oxidation reaction is

2 2

2

3 SiO 2H O 4NO

4HNO

Si    (13)

Hydrofluoric acid is used to dissolve the SiO2 layer. The reaction is:

O 2H SiF H 6HF

SiO₂  _{2 6} ₂ (14)

Water can be used as a diluent for this etchant. However, acetic acid is preferred because it reduces the dissolution of the nitric acid.

Some etchants dissolve a given crystal plane of single-crystal silicon much faster than another plane; this results in orientation-dependent etching.[29] For a silicon lattice, the (111)-plane has more available bonds per unit area than the (110)-and (100)-planes;

therefore, the etch rate is expected to be slower for the (111)-plane. A commonly used orientation-dependent etch for silicon consists of a mixture of KOH in water and isopropyl alcohol.

Orientation-dependent etching of <100>-oriented silicon through a patterned silicon dioxide mask creates precise V-shaped grooves,[30] the edges being (111)-planes at an angle of 54.7° from the (111)-surface, as shown at the left of Fig 2.15 (a). If the window in the mask is sufficiently large or if the etching time is short, a U-shaped groove will be formed, as shown at the right of Fig 2.15(a). The width of the bottom surface is given by



W -2 cot 54.7

W_{b 0}  ⁽¹⁵⁾

, 2 - W

W_b  ₀  (16)

Where W0 is the width of the window on the wafer surface and l is the etched depth.

If <100>-oriented silicon is used, essentially straight-walled grooves with sides of (111)-planes can be formed, as shown in Fig 2.15(b). We can use the large orientation

27

dependence in the etch rates to fabricate device structures with submicron feature lengths.

 Silicon Dioxide Etching

The wet etching of silicon dioxide is commonly achieved in a dilute solution of HF with or without the addition of ammonium fluoride (NH4F). Adding NH4F is referred to as a buffered HF solution (BHF), also called buffered-oxide-etch (BOE). The addition of NH4F to HF controls the pH value and replenishes the depletion of the fluoride ions, thus maintaining stable etching performance. The etch rate of SiO2 etching depends on etchant solution, etchant concentration, agitation, and temperature. In additional, density; porosity;

microstructure, and the presence of impurities in the oxide also influence the etch rate. For example, a high concentration of phosphorus in the oxide results in a rapid increase in the etch rate, and a loosely structured chemical- vapor deposition (CVD) or sputtered oxide exhibits a faster etch rate than thermally grown oxide.

Silicon dioxide can also be etched in vapor-phase HF. Vapor-phase-HF oxide-etch technology has a potential for submicron feature etching because the process can be well controlled.

 Silicon Nitride and Polysilicon Etching

Silicon nitride films are etchable at room temperature in concentrated HF or buffered HF and in a boiling H3PO4 solution. Selective etching of nitride to oxide is done with 85%

H3PO4 at 180°C because this solution attacks silicon dioxide very slowly. The etch rate is typically 10 nm/min for silicon nitride, but less than 1 nm/mm for silicon dioxide.

However photoresist adhesion problems are encountered when etching nitride w ith boiling H3PO4 solution. Better patterning can be achieved by depositing a thin oxide layer on top of the nitride film before resist coating. The resist pattern is transferred to the oxide layer, which then acts as a mask for subsequent nitride etching. Etching polysilicon is similar to etching single-crystal silicon. However, the etch rate is considerably faster because of grain

28

boundaries. The etch solution is usually modified to ensure that it does not attack the underlying gate oxide. Dopant concentrations and temperature may affect the etch rate of polysilicon.

 Aluminum Etching

Aluminum and aluminum alloy films are generally etched in heated solutions of phosphoric acid, nitric acid, acetic acid, and Dl water. The typical etchant is a solution of 73% H3PO4, 4% HNO3, 3.5% CH3COOH, and 19.5% DI water at 30°C-80°C. The wet etching of aluminum proceeds as follows: HNO₃ oxidizes aluminum, and H₃PO₄ then dissolves the oxidized aluminum. The etch rate depends on etchant concentration, temperature, agitation of the wafers, and impurities or alloys in the aluminum film. For example, the etch rate is reduced when copper is added to the aluminum.

Wet etching of insulating and metal films is usually done with the similar chemicals that dissolve these materials in bulk form and involve their conversion into soluble salts or complexes. Generally, film materials will be etched more rapidly than their bulk terparts.

Also, the etch rates are higher for films that have a poor microstructure, built- in stress, or departure from stoichiometry, or that have been irradiated. Some useful etchants for insulating.

 Gallium Arsenide Etching

A wide variety of etches has been investigated for gallium arsenide; however, few of them are truly isotropic. [31] This is because the surface activities of the (111)-Ga and (111)-As faces are very different. Most etches give a polished surface on the arsenic face, but the gallium face tends to show crystallographic defects and etches more slowly. The most commonly used etchants are the H₂SO₄-H₂O₂-H₂O and H₃PO₄-H₂O₂-H₂O systems.

For an etchant with an 8：1：1 volume ratio of H2SO4：H2O2：H2O, the etch rate is 0.8 ㎛ /min for the <111>-Ga face and 15 ㎛/min for all other faces. For an etchant with 3：1：50

29

volume ratio of H3PO4：:H2O2：H2O, the etch rate is 0.4 ㎛/min for (111)-Ga face and 0.8

㎛ for all other faces.

2.2.6 Range of Implanted Ions

Ion implantation is the introduction of energetic, charged particles into a substrate such as silicon. Implantation energies are between 1 keV and 1 MeV, resulting in ion distributions with average depths ranging from 10 nm to 10 ㎛. Ion doses vary from 10¹² ions/cm² for threshold voltage adjustment to 10¹⁸ions/cm² for the formation of buried insulating layer. Note that the dose is expressed as the number of ions implanted into 1cm² of the semiconductor surface area. The main advantages of ion implantation are its more precise control and reproducibility of impurity dopings and its lower processing temperature compared with those of the diffusion process.

Figure 2.16 shows schematically a medium-energy ion implantor. The ion source has a heated filament to break up source gas such as BF3 or AsH3 into charged ions (Bo^ or As). An extraction voltage, around 40 kV, causes the charged ions to move out of the ion-source chamber into a mass analyzer. The magnetic field of the analyzer is chosen such that only ions with the desired mass-to-charge ratio can travel through it without being filtered. The selected ions then enter the acceleration tube, where they are accelerated to the implantation energy as they move from high voltage to ground. Apertures ensure that the ion beam is well collimated. The pressure in the implantor is kept below 10^-4

minimize ion scattering by gas molecules. The ion beam is then scanned over the wafer surface using electrostatic deflection plates and is implanted into the semiconductor substrate.

The energetic ions lose their energies through collision with electrons and nuclei in the substrate and finally come to rest at some depth within the lattice. The average depth