Abstract—In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multi-gate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher
ONcurrent, a lower leakage current, and a lower threshold voltage
( th) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high
ON/OFFratio, a low th, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics. Index Terms—Metal-induced lateral-crystallization (MILC), multigate, nanowire, thin-film transistor (TFT).
I. INTRODUCTION
H
IGH-PERFORMANCE thin-film transistors (TFTs) fabricated on a polysilicon film formed by metal-induced lateral crystallization (MILC) using Ni have attracted much interest because of their potential use in three-dimensional circuit technology [1], liquid crystal display (LCD) drivers, and system-on-panel (SOP) applications [2]. It is a low-cost batch process that yields superior polysilicon (poly-Si) films. How-ever, the applications of Ni-MILC poly-Si TFTs remain limited, because the grain boundaries of poly-Si in the channel regionManuscript received May 6, 2005; revised October 12, 2005. This work was supported in part by the National Science Council of the Republic of China, Taiwan, under Contracts NSC-94-2215-E009-063, NSC-94-2215-E009-031, and NSC-94-2120-M-110-005 and by the MOEA Technology Development for Academia Project 94-EC-17–A–07-S1–046. This work was performed at the National Nano Device Laboratory. The review of this paper was arranged by Guest Editor M. Tabe.
Y.-C. Wu, C.-W. Chou, C.-H. Tu, and C.-Y. Chang are with the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
T.-C. Chang is with Department of Physics and Institute of Electro-Optical Engineering, Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung 804, Taiwan R.O.C. (e-mail: tcchang@mail. phys.nsysu.edu.tw).
P.-T. Liu is with the Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
Y.-C. Wu is with Organic Light Emitting Diode Division, AU Optronics Cor-poration, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TNANO.2006.869948
TABLE I
DEVICEDIMENSIONS OFALLPROPOSEDNi-MILC POLY-Si TFTs. ALL
DEVICESHAVE THESAMEACTIVECHANNELTHICKNESS OF50 nm
ANDGATETEOS-OXIDETHICKNESS OF50 nm
substantially degrade performance. The electrical characteristics of the TFTs can be improved by reducing the number of defects in the poly-Si grain boundaries in the channel, and poly-Si TFTs with several multichannel have been reported to effectively reduce grain boundary defects [3], [4]. The Ni-MILC poly-Si TFT suffers from severe leakage current because of Ni contam-ination during MILC annealing [2], [5], [6], which is directly related to the lateral electrical field in the drain depletion region in the off-state. This is another major limitation of Ni-MILC poly-Si TFT applications. According to previous reports, the poly-Si TFT’s adopted multigate structure can effectively reduce leakage current, thus addressing this leakage issue [7].
This study develops a single-gate structure with a single channel, a single-gate structure with ten nanowire channels, and three different multigate numbers with ten nanowire chan-nels in the Ni-MILC poly-Si TFT to study their performance. The device simulation results are also performed to investigate the relationship between the electrical field and leakage current of multigate-structure TFTs.
II. DEVICESTURCTURE, SIMULATION,ANDFABRICAION
In this study, a series of Ni-MILC poly-Si TFTs were fab-ricated as listed in Table I: one with a single-gate length of 5 m and a single-channel width of 1 m (G1S1), one with a single-gate length of 5 m and ten strips of 84-nm wire chan-nels (G1M10), one with two gate, each gate having a length of 2.5 m and ten strips of 84-nm wire channels (G2M10), one with three gates, each gate having a length of 1.7 m and ten strips of 84-nm wire channels (G3M10), one with four gate, each gate having a length of 1.25 m and ten strips of 84-nm
Fig. 1. (a) Schematic plot of a G2M10 Ni-MILC poly-Si TFT with source, drain, nanowire channels, an Ni-MILC seeding window, and a dual-gate structure. (b) Top-view plot of the G2M10 Ni-MILC poly-Si TFT. (c) Cross-sectional view of the Ni-MILC poly-Si TFT, which was a conventional top-gate, self-aligned offset MOSFET structure.
wire channels (G4M10). Fig. 1(a) presents the schematic plot of the G2M10 Ni-MILC poly-Si TFT with source, drain, nanowire channels, an Ni-MILC seeding window, and a dual-gate struc-ture. Fig. 1(b) presents the top view of the G2M10 Ni-MILC poly-Si TFT. Fig. 1(c) presents the cross-sectional view of the Ni-MILC poly-Si TFT, with a conventional top dual-gate, self-aligned offset MOSFET structure with critical device dimensions. As the anomalous off-current (leakage current) in the poly-Si TFTs is related to the lateral electrical field in the channel, Fig. 2(a) presents the simulation results obtained using an ISE TCAD 2-D device simulator DESSIS of the lateral electrical field of the single-gate (G1) and dual-gate (G2) TFTs with the same device dimension and bias condition. The peak lateral electrical field of the dual-gate TFT is lower than that of the single-gate TFT, indicating that the dual-gate (G2) structure effectively reduces the leakage current of poly-Si TFTs. Fig. 2(b) presents versus different gate-number TFT structures. The is decreasing with increasing gate number.
The 6-in p-type single-crystal silicon wafers were coated with 400-nm-thick SiO as the starting materials. An undoped 50-nm-thick amorphous-Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550 C. Then, the active islands, including source, drain, and ten nanowire channels were patterned by electron beam lithography (EBL)
Fig. 2. (a) Off-state electrical field simulation results of single-gate and dual-gate poly-Si TFT by ISE TCAD v. 7 (a 2-D device simulator). (b) The peak lateral electrical file(E ) versus different gate-number TFT structures.
and transferred by reactive ion etching (RIE). After defining the active region, the 50-nm-thick tetra-ethyl-ortho-silicate oxide (TEOS-SiO ) was deposited by LPCVD as the gate insulator. Then, 150-nm-thick undoped poly-Si films were deposited immediately on the gate oxide by LPCVD. The poly-Si layers were patterned by EBL and transferred by RIE to define the gate electrode. After gate formation, a 100-nm-thick TEOS-SiO layer as passivation layer was deposited by LPCVD. The poly-Si gate sidewall TEOS-SiO was formed as a self-aligned offset spacer with a width of 0.1 m, as shown in Fig. 1(b). Then, the MILC seeding window and contact holes were patterned by EBL and transferred by RIE in the same mask process. Then, a thin 10-nm-thick nickel (Ni) layer was deposited by physical vapor deposition (PVD). The MILC crystallization was carried out at 550 C for 48 h in an N ambient. After annealing, the unreacted nickel on passivative TEOS-SiO was removed by an H SO solution at 120 C for 10 min. Phosphorus ions at a dose of 5 10 cm were implanted through the passivative
Fig. 3. (a) SEM photograph of the active pattern with the source, drain, ten nanowire channels, and dual-gate structure. (b) SEM photograph of the magnified area of multiple nanowire channels. Each nanowire has a width of 84 nm. (c) SEM photograph of the Ni-MILC poly-Si grain structure. The average poly-Si lateral grain size is approximately 250 nm. The inset optical microscopy photograph depicts an MILC with length of 30m.
TEOS-SiO to form the n gate, source/drain regions, and the self-aligned offset region in the same process step, as shown in Fig. 1(b). Then, the dopants were activated by rapid thermal annealing (RTA) at 850 C for 30 s. The 300-nm-thick aluminum (Al) layer was deposited by physical vapor deposition (PVD) and patterned for source, drain, and gate metal pads. In this study, no other H or NH plasma passivation was performed. This allowed the intrinsic behavior of the devices to be compared and studied.
III. RESULTS ANDDISCUSSION
Fig. 3(a) shows a scanning electron microscopy (SEM) pho-tograph of the G2M10 Ni-MILC TFT active pattern with the source, the drain, ten nanowire channels, and dual-gate struc-ture. Each dual-gate length is 2.5 m. Fig. 3(b) shows SEM
pho-Fig. 4. (a) Comparison ofI 0 V transfer characteristics of all proposed Ni-MILC poly-Si TFTs with the same device length (L ) of 5 m. (b) Transfer curve of G4M10 TFT with linear and saturation regions. The inset SEM photograph shows the G4M10 TFT active region.
tographs of the magnified area of multiple nanowire channels. The width of each nanowire is 84 nm. Fig. 3(c) shows SEM pho-tographs of the Ni-MILC poly-Si grain structure. The average poly-Si lateral grain size is approximately 250 nm. The inset op-tical microscopy photograph depicts an MILC length of 30 m, which is longer than 16 m [see Fig. 1(a)] to ensure that the whole active channel was crystallized by the MILC process.
Fig. 4(a) compares typical transfer curves of all proposed Ni-MILC poly-Si TFTs. First, comparing the single-gate, the single-channel (G1S1), and the ten-nanowire-channel (G1M10) TFTs reveals that the G1M10 has a higherONcurrent, a lower leakage current, and a lower threshold voltage than the G1S1 TFT. These data indicate that the multiple-nanowire-channel TFTs have fewer defects at the grain boundaries. For the G1M10 TFT, during the MILC process, its nanowire width of 84 nm strongly limited the growth of poly-Si grains in the -direction [see Fig. 1(a)] than did the single-channel G1S1 TFT. Therefore, the poly-Si grains tended to grow laterally in the -direction, becoming large to reduce the grain boundary defects. In our previous report [8], the poly-Si grain enhancement effect was
Fig. 5. Comparison ofI 0V output characteristics of all proposed Ni-MILC poly-Si TFTs with the same device length(L ) of 5 m.
significant as the channel width was less than the poly-Si grain size. However, both G1S1 and G1M10 exhibit severe leakage current and large subthreshold swing (SS). Second, comparing the single-gate (G1M10) and multigate (G2M10, G3M10, and G4M10) TFTs with the same ten-nanowire-channel Ni-MILC poly-Si TFTs reveals that the electrical performance is signif-icantly improved as the multigate number increases Fig. 4(b) presents the transfer curve of G4M10 TFT with linear and satura-tion regions. The inset SEM photograph shows the G4M10 TFT active region. The G4M10 outperforms the other TFTs, having a low leakage current, a highON/OFFratio 10 , a low , a steep SS, and near-free drain-induced barrier lowering (DIBL). Fig. 5 compares the output curves of all proposed Ni-MILC poly-Si TFTs with the same gate length of 5 m. The kink effect associated with multigate (i.e., G2M10, G3M10, and G4M10) TFTs is suppressed relative to those of the other TFTs (i.e., G1S1 and G1M10). Accordingly, the multigate structure effec-tively reduces the lateral electrical field [see Fig. 2(b)], thus reducing the impaction ionization in the active channel of the Ni-MILC poly-Si TFTs.
Fig. 6 presents the leakage current and ON/OFFratio versus different structure of the Ni-MILC TFTs. The leakage current is defined as the drain current at V and V, and theON/OFFratio is defined as the maximum drain current value
of at V. For a single-gate TFT, nanowire
channels (G1M10) can be applied to yield a low leakage current by reducing the number of defects at the poly-Si grain boundaries below the number in a single-channel TFT (G1S1). Additionally, comparing single-gate (G1M10) and multigate (i.e., G2M10, G3M10, and G4M10) TFTs with the same ten-nanowire-channel Ni-MILC poly-Si TFTs reveals that the leakage current de-creases and theON/OFFratio increases as with the number of multigate increasing. The G4M10 TFT has the lowest leakage current of 5.12 10 A and the highestON/OFFratio of 1.81 10 . These findings reveal that the multigate structure can re-duce the peak lateral electrical field in the drain depletion region. Therefore, the leakage current that arises from the field emission of carriers through the poly-Si grain traps and the number of defects associated with Ni contamination was reduced. This
Fig. 6. Leakage current andON/OFFratio versus all proposed TFTs, operated in the saturation regime (V = 5 V).
Fig. 7. Threshold voltage and subthreshold swing versus all proposed TFTs, operated in the saturation regime (V = 5 V).
finding is consistent with the simulated value of the lateral electrical field of multigate TFTs in Fig. 2(b).
Fig. 7 plots the and SS versus the structure of the TFTs. is defined as the gate voltage to yield a normalized drain current
equal to 10 A at 5 V. Comparing the G1S1 and G1M0 TFTs reveals that the ten-nanowire-channel structure has a lower , indicating that the ten-nanowire-channel struc-ture has fewer defects at the poly-Si grain boundaries than the single-channel structure. Moreover, the multigate structure is as-sociated with an even lower , and the G4M10 has the lowest of 0.41 V. The results reveal that the multigate structure exhibits channel-length-shortening effect for easy turn-on of the TFT. The effective channel length decreases as the number
of multigate increases ( , where is the
number of multigate and is the overlap of the source/drain dopant region and the gate. The SS specifies the capacity of the transistor to switch. These results reveal that the SS declines as the number of multigate increases, and the G4M10 has the lowest SS of 0.44 V/dec. For the same channel, the length-short-ening effect is responsible for the lowering the SS.
Fig. 8 plots a series of G1M10 TFT transfer curves after var-ious hot-carrier stress conditions with 1000 second. Until the extreme hot-carrier stress conditions of V and
Fig. 8. Series of G1M10 TFT transfer curves after different hot-carrier stress condition with a 1000-s duration.
Fig. 9. Maximum transconductanceG degradation versus dc hot-carrier time with all ten-nanowire-channel TFTs, extracted in the saturation regime (V = 5 V).
22.5 V are reached; only the transfer curve of G1M10 TFT shows degradation. The results indicate that the ten-nanowire-channel structure of the Ni-MILC TFT supports excellent hot-carrier immunity and potential use in high-voltage applications. The similar hot-carrier stress results are also found in other multigate Ni-MILC TFTs with ten nanowire channels. Fig. 9 plots the maximum transconductance degradation with dc hot-carrier time of all ten-nanowire TFTs. These results re-veal that the all Ni-MILC TFTs with ten nanowires have sim-ilar degradation. However, the G4M10 still has lighter degradation than other TFTs due to its lowest lateral electrical field. Fig. 10 plots the ON/OFFratio degradation with dc hot-carrier time of all ten-nanowire TFTs. These results reveal that the degradation ofON/OFFratio improves with the gate number increasing. Again, the multigate structure can reduce the peak lateral electrical field, which is responsible for this degrada-tion of theON/OFF-ratio improvement. In brief, combining the
Fig. 10. ON/OFFratio versus dc hot-carrier time with all ten-nanowire-channel TFTs, extracted in the saturation regime (V = 5 V).
multigate structure and ten nanowire channels can effectively enhance the entire performance of Ni-MILC TFTs. Obviously, the device performance can be further improved by declining the gate length before the short-channel effect occurrence. How-ever, according to this study, the multigate number is properly within 2 to 4 because, the more gate number increases, the more additional parasitic resistance will be generated between each gate. The additional parasitic resistance will reduce the device performance.
IV. CONCLUSION
Experimental results show that applying ten nanowire chan-nels enhances the performance of Ni-MILC poly-Si TFTs because the nanowire shape increases the poly-Si lateral length to reduce the number of defects at the poly-Si grain boundaries. Moreover, combining the multigate structure can effectively reduce the lateral electrical field while further enhancing the TFT performance, including a lower leakage current, a higher ON/OFFratio, a lower , and a lower SS than for a single-gate TFT. In output characteristics, the multigate with a ten-nanowire TFT can reduce the kink effect. These novel multichannel and multigate Ni-MILC poly-Si TFTs involve no additional processes, making them highly suitable for high-per-formance MILC poly-Si TFT applications.
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gree at the National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
From 1998 to 2002, he was an Assistant Re-searcher with the National Nano-device Laboratory, where he was engaged in the research of single-elec-tron transistors and elecsingle-elec-tron-beam lithography technology. His current research includes fabrication, simulation, and charac-terization of submicrometer low temperature polycrystalline silicon thin-film transistors and novel nanoscale devices.
Ting-Chang Chang received the B.S. degree in
physics from the National Taiwan Normal Univer-sity, Taipei, Taiwan, R.O.C., in 1986, the M.S. degree in physics from the National Taiwan University, Taipei, in 1989, and the Ph.D. degree from the National Chiao Tung University, Hsinchu, Taiwan, in 1994.
He is a Chair Professor with the Department of Physics, National Sun Yat-Sen University, Kaoh-siung, Taiwan, R.O.C. He has made pioneering contributions to semiconductor device technology, ULSI memory devices, and thin-film-transistor liquid-crystal displays. Since 1999, he has authored or coauthored 76 papers and has had 23 U.S. and 51 Taiwan patents granted. In addition, he proposed the project of In-dustry–Academy Cooperation with the United Micoelectronics Corporation to research nano-porous low-k materials for ULSI application and has made great progress. Recently, he has been interested in the study of nonvolatile memory devices and nanodot technology.
Prof. Chang was the recipient of the “Award of Industry–Academy Coopera-tion” from the Ministry of Education in 2002.
Po-Tsun Liu received the Ph.D. degree from the
In-stitute of Electronics, National Chiao Tung Univer-sity (NCTU), Hsinchu, Taiwan, R.O.C., in 2000.
He joined the National Nano Device Laboratory (NDL), Taiwan, as an Associate Researcher in Jan-uary 2000 and became the leader of the Department of Electro-optics and Bio-technology in March 2004. He has made a great deal of pioneering contributions to low-permittivity (low-k) dielectrics, copper inter-connects, and thin-film-transistor technologies. In his research on low-k dielectrics, he utilized a plasma treatment technique for the first time to improve electrical characteristics of low-k materials. In addition, he and his collaborators developed a novel tech-nology to pattern low-k materials directly by using electron-beam lithography and X-ray radiation technology, instead of the typically used photoresist coating and etching processes. He joined the faculty of NCTU as an Associate Pro-fessor with the Department of Photonics and Display Institute in October in 2004. His main research focuses on flat-panel-display technologies, specializing in thin-film transistors, advanced nanoscale semiconductor device technology, nonvolatile memory devices, and nanofabrication technologies. In the last five years, he has authored or coauthored 60 papers, 27 international conference pa-pers, and been granted 46 U.S. and Taiwan patents.
Dr. Liu is a member of the Society for Information Display. Because of the prominent contributions, he was listed in Marquis’ Who’s Who in the World (20th edition, 2003).
Yuan-Chun Wu was born in Tao-yuan, Taiwan,
R.O.C. He received the B.S degree in physics from National Sun Yat-Sen Univeristy, Kaohsiung, Taiwan, R.O.C., in 2002, and the M.S. degree in electrical engineering from National Chiao Tung University, Hsnichu, Taiwan, R.O.C., in 2004. His thesis focused on metal-induced lateral-crystalliza-tion thin-film transistors.
He is currently a Senior Engineer with the Organic Light Emitting Diode Division, AU Optronics Cor-poration, Hsinchu.
Chun-Hao Tu received the B.S degree in physics
from National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., in 2000, and is currently working toward the Ph.D. degree at National Chiao Tung University, Hsnichu, Taiwan, R.O.C.
His research interests include fabrication and char-acterization of amorphous silicon thin-film transis-tors (TFTs), low temperature polycrystalline silicon TFTs, and nonvolatile memory.
Chun-Yen Chang (M’88–F’05) was born in
Feng-Shan, Taiwan, R.O.C. He received the B.S. degree in electrical engineering from National Cheng Kung University (NCKU), Taiwan, in 1960, the M.S. degree in tunneling in semiconductor-su-perconductor junctions and the Ph.D. degree in carrier transport across metal–semiconductor barrier, both from National Chiao-Tung University (NCTU) Hsinchu, Taiwan, in 1969.
In 1969, he became a Full Professor at NCKU. From 1977 to 1987, he established a strong electrical engineering and computer science program at NCKU where GaAs, Si, and poly-Si researches were established in Taiwan for the first time. Since 1987, he served consecutively as Dean of Research (1987–1990), Dean of Engineering (1990–1994), and Dean of Electrical Engineering and Computer Science (1994–1995) at NCKU. Simultaneously, he was serving as the Founding President of National Nano Device Laboratories (NDL), Hsinchu, from 1990 to 1997. From 1997 to 1998, he served as Director of the Microelectronics and Information System Research Center (MIRC), NCTU. In August 1998, he was appointed as the President of NCTU. As the National Chair Professor and President of NCTU, his vision is to lead the university for excellence in engineering, humanity, art, science, management and bio-technology.
Dr. Chang received the IEEE Third Millennium Medal in 2000. He is a Member of Academia Sinica and a Foreign Associate of the National Academy of Engineering.
