Improved high-temperature leakage in high-density MIM capacitors by using a TiLaO dielectric and an Ir electrode

IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 12, DECEMBER 2007 1095

Improved High-Temperature Leakage in

High-Density MIM Capacitors by Using a

TiLaO Dielectric and an Ir Electrode

C. H. Cheng, H. C. Pan, H. J. Yang, C. N. Hsiao, C. P. Chou,

S. P. McAlister, Senior Member, IEEE, and Albert Chin, Senior Member, IEEE

Abstract—We have fabricated high-κ TaN/Ir/TiLaO/TaN metal–insulator–metal capacitors. A low leakage current of 6.6× 10−7A/cm2_{was obtained at 125}◦_{C for 24-fF/µm}2_density

capacitors. The excellent device performance is due to the combined effects of the high-κ TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.

Index Terms—High-κ, Ir, metal–insulator–metal (MIM), TiLaO.

I. INTRODUCTION

T

capacitors [1]–[16]. To achieve this, the MIM devices have evolved by using higher κ dielectrics such as SiN [3], [4], Al2O3[6], [7], Ta2O5 [5], HfO2[8]–[10], Nb2O5[11], TiTaO

[12], [13], and SrTiO3(STO) [14]–[16]. Unfortunately,

increas-ing the κ value usually decreases the conduction band offset (∆EC)with respect to the metal electrode. For STO [17], ∆EC can even be slightly negative. A low ∆EC leads to unwanted leakage current for a MIM device at high temperatures [16], where such increase in the operational temperature is unavoid-able due to the increased circuit density and higher power dissipation. Although STO shows higher κ values and good de-vice characteristics, a higher process temperature > 450◦C for nanocrystal formation and thicker thickness to reduce leakage are necessary. This exceeds the maximum temperature (400◦C) permitted for backend integration [14]–[16].

Here, we report low thermal leakage TiLaO MIM capacitors using a high work-function Ir electrode, which are processed at 400◦C. We measured leakage currents of 1× 10−7 and 6.6× 10−7 A/cm2 _{at 1 V at 25}◦_{C and 125} ◦_{C, respectively; these}

Manuscript received August 16, 2007; revised September 26, 2007. This work was supported in part by NSC 95-2221-E-009-275 of Taiwan. The review of this letter was arranged by Editor A. Wang.

C. H. Cheng and C. P. Chou are with the Department of Mechanical Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

H. C. Pan and C. N. Hsiao are with the Instrument Technology Research Center, National Applied Research Laboratories, Hsinchu, Taiwan, R.O.C.

H. J. Yang and A. Chin are with the Department of Electronics Engineer-ing, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]).

S. P. McAlister is with the National Research Council of Canada, Ottawa, ON K1A 0R6, Canada.

Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2007.909612

currents are lower than those in the previously reported TiTaO and 400◦C-processed STO capacitors.

II. EXPERIMENTALPROCEDURE

The high-κ TiLaO MIM capacitors were fabricated on standard Si wafers. To permit VLSI backend integration, the process began with depositing a 2-µm-thick SiO2 isolation

layer on the Si substrates. Then, a 50-nm TaN was deposited on a 200-nm Ta layer by sputtering and used as the lower capacitor electrode. The TaN surface was then given a plasma treatment to increase the oxidation resistance before the high-κ deposition and postdeposition annealing (PDA) [5], [6]. A 15-nm-thick TixLa1−xO (x∼ 0.67) film was deposited by PVD, followed by

a 400-◦C PDA in an oxygen ambient to reduce the defects and the leakage current [3] (the TiLaO thickness was later measured by cross-sectional transmission electron microscopy). Finally, 20-nm Ir and/or 50-nm TaN were deposited and patterned to form the top electrode. A large capacitor size of 100 µm× 100 µm was chosen to avoid any variations in dimensions arising from lithography. The devices were characterized by C–V and J –V measurements.

III. RESULTS ANDDISCUSSION

In Fig. 1, we show the C–V , J –V , and thermal-stability char-acteristics of TaN/TiLaO/TaN and TaN/Ir/TiLaO/TaN devices. A comparison with other data is summarized in Table I. A high capacitance density of 24–24.5 fF/µm2was measured for the TiLaO MIM devices, which gives a high-κ value of ∼45 for the TiLaO dielectric. A leakage current of 2.2× 10−6 A/cm2

at−1 V was measured for the TaN/TiLaO/TaN MIM capacitor close to that of an Ir/TiTaO/TaN device (Table I) with a slightly lower capacitance density. Since the work function of the TaN on TiLaO is ∼0.7 V lower than that of Ir on TiTaO, the comparable leakage current indicates that the TiLaO is a better choice for MIM capacitors than TiTaO. This is confirmed by the five times lower leakage current of 1× 10−7 A/cm2 _in

the TaN/Ir/TiLaO/TaN device compared with the Ir/TiTaO/TaN capacitor. This improved leakage current, at a comparable capacitance density, is due to the higher ∆EC between metal and high-κ interface, which lowers the leakage current expo-nentially. A similar lower leakage current was also reported by adding higher ∆ECAl2O3into HfO2MIM capacitor [9]. The

1096 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 12, DECEMBER 2007

Fig. 1. (a) C–V , (b) J –V , and (c) thermal-stability characteristics of TaN/TiLaO/TaN and TaN/Ir/TiLaO/TaN MIM capacitors measured at various frequencies, at 25◦C and 125◦C. The thermal-stability test was performance at 400◦C for 20 min in an ambient N2.

small changes of J –V and C–V , after 400-◦C N2 annealing,

indicate that the thermal stability is acceptable. Note that good thermal stability was reported for metal-gate/high-κ pMOS for Ir on HfAlON at Rapid Thermal Anneal (RTA) temperatures up to 900◦C [17].

A larger ∆ECat the metal/high-κ interface is very important at 125 ◦C, which is a temperature required for both DRAM and nonvolatile memory [18]. This is shown in the compar-ison with STO: The leakage current (at−1 V) of a 400 ◦ C-formed Ni/STO/TaN capacitor increased from 2× 10−7to 5×

TABLE I

COMPARISON OFMIM CAPACITORSWITHVARIOUS

DIELECTRICS ANDMETALELECTRODES

Fig. 2. Measured and simulated J –E1/2 of an Ir/TiLaO/TaN capacitor. A TaN/TiLaO/TaN device is shown, for comparison, in the inset.

10−6 A/cm2_{, from 25}◦_{C to 125}◦_{C (Table I), whereas in the}

TaN/Ir/TiLaO/TaN capacitor, it only increased from 1× 10−7 to 6.6× 10−7 A/cm2_{. Although the work function of the Ir}

electrode (5.27 eV) is slightly higher than Ni (5.1 eV), the improved 125-◦C leakage current can be attributed to the large ∆EC. We note that La2O3has the highest ∆EC with respect to Si (2.3 eV) compared with HfO2 (1.5 eV), ZrO2 (1.4 eV),

Ta2O5(0.3 eV), and STO (−0.1 eV) [19].

To investigate the current conduction mechanism we plot, in Fig. 2, ln(J ) versus E1/2 for the TaN/Ir/TiLaO/TaN MIM capacitors J ∝ exp
γE1/2_{− Vb} kT  (1) γ =
e3 ηπε0K∞ 1/2 . (2)

Here, K_∞ is the high-frequency dielectric constant (= n2_).

CHENG et al.: LEAKAGE IN MIM CAPACITORS BY USING A TiLaO DIELECTRIC AND AN Ir ELECTRODE 1097

Fig. 3. J/T2_–E1/2_{plots of TaN/TiLaO/TaN and TaN/Ir/TiLaO/TaN MIM}

capacitors.

and η is 1 or 4 for Schottky emission (SE) or Frenkel–Poole (FP) conduction, respectively. The data fitting suggests that the current conduction mechanism of the TaN/Ir/TiLaO/TaN device changes from SE at low electric fields to FP at higher fields. In contrast, the TaN/TiLaO/TaN devices fit an SE description at both low and high fields.

The SE barrier height (Vb) at 125 ◦C was determined from J/T2_–E1/2 _{plots (Fig. 3). Values for V}

b were 0.57 and 1.35 eV for TiLaO devices at 125 ◦C with TaN and Ir top electrodes, respectively. The large Vb difference explains the reduced leakage current and the weaker temperature depen-dence in the TaN/Ir/TiLaO/TaN devices. Thus, a low leakage current at high temperature can be obtained in MIM capacitors by combining a high-κ dielectric, having a high ∆EC, with a high work-function metal electrode.

IV. CONCLUSION

A high capacitance density and low leakage current at 125◦C have been achieved in Ir/TiLaO/TaN MIM capacitors. The device-processing temperature of 400 ◦C would enable them to be integrated into the VLSI backend technology and be used in multiple functions associated with system-on-a-chip.

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