Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor field-effect-transistors

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Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor

ﬁeld-effect-transistors

Ching-Sen Lu

a

, Horng-Chih Lin

a,b,*

, Tiao-Yuan Huang

a

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan, ROC b_{National Nano Device Laboratories, 26 Prosperity Road I, Science-based Industrial Park, Hsinchu 300, Taiwan, ROC}

a r t i c l e

i n f o

Article history: Received 15 May 2008 Accepted 7 June 2008 Available online 22 July 2008

Review of this manuscript was arranged by A. Iliadis, C. Richter, and A. Zaslavsky Keywords:

SiN capping Tensile stress

Precursor ﬂow conditions Hot-carrier stress

a b s t r a c t

Although the incorporation of a SiN capping layer could dramatically enhance device performance, the accompanying hydrogen species contained in the capping layer may aggravate hot-carrier reliability. In order to alleviate this shortcoming, we vary the precursor flow conditions and deposition temperature of SiN film during plasma-enhanced chemical vapor deposition (PECVD) and study their impacts on the device performance and reliability. We found that SiN film with higher nitrogen content depicts larger tensile stress and therefore better mobility. More importantly, the resistance to hot-carrier degradation is also improved by increasing N2gas flow rate and deposition temperature because of less hydrogen dif-fusion from the capping layer.

1. Introduction

Channel strain engineering such as embedded SiC source/drain (S/D)[1,2]and highly tensile SiN capping layer[1–9]for n-channel metal-oxide-semiconductor ﬁeld-effect-transistors (NMOSFETs) mobility enhancement has been pursued aggressively in scaled

complementary metal-oxide-semiconductor (CMOS) devices.

Among these methods, SiN capping technique has received much attention because it is easily implemented in modern ULSI technol-ogy. In addition, depending on the SiN deposition conditions, stress level ranging from highly tensile to highly compressive is adjust-able, enabling the dual-SiN stressor technology for CMOS manufac-turing[5].

Although SiN capping can dramatically enhance the device per-formance, the abundant hydrogen species generated during the SiN deposition process may diffuse into the channel region, resulting in serious hot-carrier reliability issue[6]. Recently, the insertion of an ultra-thin buffer layer between the SiN capping layer and the underlying poly-Si gate electrode was demonstrated to effectively suppress the hydrogen diffusion and restore the reliability without compromising the device performance[7,8]. In this work, another effective approach to directly adjust the composition of SiN ﬁlm by varying the precursor gas ﬂow rate and deposition temperature is

explored. Our results indicate that it is indeed possible to optimize the SiN deposition so the device reliability aggravation is alleviated without compromising the device performance enhancement by the channel strain.

2. Device fabrication

NMOSFETs characterized in this study were with 3 nm-thick thermal oxide grown in a vertical furnace, and 150 nm-thick poly-crystalline–silicon (poly–Si) layer as the gate electrode. After S/D doping and self-aligned spacer formation step, a 300 nm-thick SiN capping layer was deposited by plasma-enhanced chemical va-por deposition (PECVD), as shown inFig. 1. In this work, we eval-uated devices with ﬁve different types of SiN ﬁlm using SiH4/

NH3/N2 gas mixtures at 300 °C and 400 °C (denoted as SiN-1,

SiN-2, SiN-3, SiN-1(400 °C), and SiN-3(400 °C)). The detailed gas ﬂow rates are listed inTable 1, and the major parameter adjusted is the N2gas ﬂow rate. Deposition pressure and radio frequency (rf)

power were ﬁxed at 1 Torr and 100 W, respectively. In addition to SiN-capped samples, the control devices with 300 nm-thick PECVD oxide capping were also fabricated as the control (denoted as SiO2

split). After contact hole formation and metallization processes, the processing steps were completed with a forming gas anneal at 400 °C and 30 min.

Current–voltage characteristics of devices with channel width (W) of 10

l

m and channel length (L) ranging from 0.4

l

m to

10

l

m were measured using an Agilent 4156 system.

*Corresponding author. Address: Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan, ROC. Tel.: +886 3 571 2121x54193; fax: +886 3 572 4361.

E-mail address:[email protected](H.-C. Lin).

Contents lists available atScienceDirect

Solid-State Electronics

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tance–Voltage (C–V) characteristics for devices with W/L = 50/ 50

l

m were performed using Agilent 4284 system.

3. Material analysis

X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared spectrometer (FTIR) were employed to investigate the material properties of the deposited SiN films, and the major re-sults are given inFigs.2 and 3, respectively. From XPS analysis (Fig. 2), we confirmed that SiN-3 and SiN-3(400 °C) samples have similar N content that is higher than the other samples. Obviously the use of higher N2flow rate in the deposition process is

respon-sible for the phenomenon. In addition, from the analysis of FTIR measurement, an increase in N2ﬂow rate[10]and deposition

tem-perature[11]tends to weaken the signal of Si–H bonds, as shown inFig. 3. Later we will show that this ﬁnding has important

impli-cation for increasing the immunity of devices to hot-carrier degradation.

The stress measurements were performed using a Tencor FLX-2320 system. This system evaluates the stress by measuring the change in curvature of the silicon substrate before and after the deposition of a blanket SiN layer with a thickness of 300 nm. We conﬁrmed that the stress is tensile in nature with a magnitude of around 127, 344, 556, 96, and 576 MPa for SiN-1, SiN-2, SiN-3, SiN-1(400 °C), and SiN-3(400 °C) splits, respectively, as listed in Ta-ble 1. It can be seen that the tensile stress increases with increasing N2ﬂow rate, as shown inFig. 4, while only mildly affected by the

two deposition temperatures studied in this work. 4. Device characteristics

Next, the electrical characteristics were performed using an

Agi-lent 4156 system. Fig. 5 compares transconductance (Gm)

enhancement for all splits with W/L = 10/0.4

l

m. It can be seen that SiN-3 and SiN-3(400 °C) splits depict identical Gm that is the largest among all samples, while the SiN-1 and SiN-1(400 °C) splits show comparable Gm to the SiO2split. Similar enhancement

trend in drive current is also observed, as shown inFig. 6. These

0 2 4 6 8 SiN-3 Si2p Si 2s N1s

Binding Energy (eV)

0 100 200 300 400 500 0 2 4 6 8 SiN-3(400 o_C) Si2p Si 2s N1s 0 2 4 6 8 SiN-1 Si 2p Si2s N1s Counts/s (x10 4)

Fig. 2. Results of XPS analysis: SiN-3 and SiN-3(400 °C) samples depict similar N content which is higher than the other samples, owing to the use of higher N2ﬂow rate during the deposition.

Wavenumber (cm-1) 500 1000 1500 2000 2500 3000 3500 4000 Absorbance -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Si-N Si-H N-H

SiN-1

SiN-3

SiN-3(400

o

C)

Fig. 3. Results of FTIR analysis: SiN-1 sample contains more Si–H bonds than the other samples. Increase in N2ﬂow rate and deposition temperature tends to weaken the signal of Si–H bonds.

N₂ Flow Rate

10 100 1000 10000

Tensile Stress (MPa)

100 200 300 400 500 600 300o o C 400 C

Fig. 4. Stress level of the deposited ﬁlms as a function of the N2ﬂow rate during deposition. Gate Source Drain Oxide Passivation Split T=300 nm

Fig. 1. Schematic structure of fabricated devices with different types of passivation. The passivation thickness is ﬁxed at 300 nm.

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electrical results are consistent with the results of ﬁlm stress mea-surement listed inTable 1.

Fig. 7shows the percentage increase of Gm for all SiN-capping samples compared with the controls as a function of channel length. Each datum point represents the mean measurement value from six devices. We can see that Gm enhancement ratio increases with decreasing channel length, a feature of uniaxial strain caused by SiN capping[9]. The C–V characteristics of these samples are shown inFig. 8. It can be observed that the C–V curves coincide altogether, indicating that the above-mentioned results are indeed not caused by the difference in gate-oxide thickness.

V_G-V_th (V) -0.5 0.0 0.5 1.0 1.5 Transconductance ( μ S) 0 100 200 300 400 SiO2 SiN-1 SiN-2 SiN-3 SiN-1(400oC) SiN-3(400oC) W/L=10/0.4μm

Fig. 5. Transconductance (Gm) versus (VG–Vth) for all splits with W/L = 10/0.4lm. The SiN-3 and SiN-3(400 °C) splits depict identical Gm which is the largest among all samples, owing to the largest tensile stress level.

Drain Voltage (V)

0.0 0.5 1.0 1.5 2.0

Drain Current (mA)

0 1 2 3 4 5 6 SiO2 SiN-1 SiN-2 SiN-3 SiN-1(400oC) SiN-3(400oC) V_G - V_th = 0.4V V_G - V_th = 1.2V V_G - V_th= 2V

W/L=10/0.4μm

Fig. 6. Output characteristics of NMOSFETs for all splits. The enhancement trend in driving current is similar to Gm increase.

Table 1

Precursor ﬂow rates, deposition temperature, and measured tensile stress level for SiN ﬁlms SiH4 (sccm) NH3 (sccm) N2 (sccm) Temp. (°C) Stress (MPa) SiN-1 50 6 50 300 127 SiN-2 50 6 100 300 344 SiN-3 50 6 1000 300 556 SiN-1(400 °C) 50 6 50 400 96 SiN-3(400 °C) 50 6 1000 400 576 Channel Length (_μm) 1 10 Δ Gm max /Gm max (%) 0 5 10 15 20 SiN-1 SiN-2 SiN-3 SiN-1(400oC) SiN-3(400oC)

Fig. 7. The percentage increase of Gm for all SiN-capping samples, compared with the SiO2controls, as a function of channel length. Each datum point represents the mean measurement value from six devices.

Gate Voltage (V) -2 -1 0 1 Capacitance ( μ F/cm 2) 0.2 0.4 0.6 0.8 1.0 1.2 SiO2 SiN-1 SiN-2 SiN-3 SiN-1(400oC) SiN-3(400oC)

W/L=50/50

μm

Tox,inv ~ 3.18nm

Fig. 8. Capacitance–Voltage (C–V) characteristics for all splits. The C–V curves coincide altogether, indicating that the above-mentioned results are indeed not caused by the difference in oxide thickness.

V_G-V_th (V)

-0.5 0.0 0.5 1.0 1.5

Drain Current (A)

10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2

SiO

2

SiN-1

SiN-2

SiN-3

SiN-1(400

o

C)

SiN-3(400

o

C)

W/L=10/0.4

μm

_{Vds = 1.5V} Vds = 0.05V

Fig. 9. Subthreshold characteristics of NMOSFETs for all splits with W/L = 10/ 0.4lm.

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The subthreshold characteristics and extracted subthreshold swing (S.S.) are shown inFigs.9 and 10, respectively. We can see that subthreshold swing of all SiN-capping splits depicts similar value and is slightly lower than that of SiO2control. Subthreshold

swing of an MOSFET at room temperature can be expressed as[12]

S:S: ¼ 60 1 þCdþ Cit Cox

ðmV=decÞ;

where Coxis the gate capacitance, Cdis the depletion capacitance,

and Citis interface state capacitance. The PECVD SiN ﬁlm contains

a large amount of hydrogen due to the use of hydrogen-containing precursors (SiH4and NH3)[10,13]. These hydrogen species may

dif-fuse into the SiO2/Si interface and passivate the dangling bonds,

resulting in a decrease in Cit[10,14]and a reduction in S.S.

5. Hot-carrier stress

Finally, we turn our attention on hot-carrier characteristics. De-vices with W/L = 10/0.5

l

m were stressed at VDS= 4.6 V and VGat

maximum substrate current. Threshold voltage shift (DVth) and

interface state generation (DNit) as a function of stress time for

all splits are shown inFig. 11a and b, respectively. It can be seen that SiN-1 split depicts the worst degradation in terms of the

larg-estDVthandDNit, while SiN-1(400 °C) split apparently fares much

better. By contrast, SiN-3 and SiN-3(400 °C) splits show much improvement in the immunity to hot-carrier damage as compared with the other SiN samples. Note that the difference between SiN-3 and SiN-3(400 °C) is much smaller than that between SiN-1 and SiN-2. Since the SiN-3 split has the least hydrogen content, this im-plies that the effect of deposition temperature becomes weaker as the SiN contains less hydrogen.

From the FTIR results shown inFig. 3, we speculate that the amount of Si–H bonds contained in the SiN film is mainly respon-sible for the hot-carrier immunity of the SiN samples. Note that the bond strength of nominal Si–H bonds (i.e., 314 kJ/mole) is much weaker than that of N–H bonds (i.e., 389 kJ/mol)[15,16]. It is thus reasonable to assume that the hydrogen pertaining to the former bonds is much easier to dissociate and release from the SiN film. As a consequence, the high amount of Si–H bonds in the SiN-1 split (Fig. 3) would release extra H species to the device and form new Si–H bonds at the Si/channel interface [10,14]. The breaking of Si–H bonds at the Si/channel interface during stressing is believed to be one of the major root causes responsible for the hot-carrier degradation[6–8,17]. These passivated Si–H bonds act as precur-sors to hot-carrier degradation[18,19]and are more easily broken during subsequent stressing[17]. Therefore, SiN film containing abundant hydrogen species would aggravate hot-carrier reliability. Since SiN-1 film contains the highest amount of Si–H bonds, the worsening of hot-carrier reliability occurs most significantly in the SiN-1 split, even though its strain level is not high. Increase in both N2flow rate[10]and deposition temperature[11]could

re-duce the amount of Si–H bonds, as evidenced in FTIR analysis. Therefore, SiN-3(400 °C) shows the best hot-carrier reliability among all SiN capping samples, even though its stress level and the resultant device performance enhancement is the highest (Figs. 5–7). However, the difference between SiN-3(400 °C) and SiN-3 is small. This indicates that, as the amount of Si–H bonds contained in the SiN layer is reduced, the deposition temperature plays a less important role on affecting the device performance as well as the hot-carrier degradation.

Channel strain engineering using highly tensile SiN capping has been popularly applied to modern technology to enhance the driv-ing current of NMOS[1–9]. Based on the results presented in the present study, the N content and the Si–H bonds contained in the capping layer must be carefully controlled. Special attention should be paid to the NMOS devices in the input/output (I/O) re-gions which have more concerns on hot-carrier reliability, since

SiO2 SiN-1 SiN-2 SiN-3

SiN-1(400C)SiN-3(400C)

Subthreshold Swing (mV/dec)

64 66 68 70 72 74 76 78 80

W/L=10/0.4

μm

Fig. 10. Subthreshold swing of NMOSFETs for all splits with W/L = 10/0.4lm.

Stress Time (sec)

1 10 100 1000 Δ Vth (mV) 0 50 100 150 200 250 300 SiO2 SiN-1 SiN-2 SiN-3 SiN-1(400o C) SiN-3(400oC) W/L=10/0.5μm VDS = 4.6V, VG@Isub,max

Stress Time (sec)

1 10 100 1000 Δ Nit (10 10 cm -2 ) 0 10 20 30 40 50 60 SiO2 SiN-1 SiN-2 SiN-3 SiN-1(400oC) SiN-3(400o C) W/L=10/0.5μm VDS=4.6V, VG@Isub,max

a

_b

Fig. 11. (a) Threshold voltage shift (DVth), and (b) interface state generation (DNit) as a function of stress time for all splits. Devices are stressed at VDS= 4.6 V, and VGat maximum substrate current. DVthis deﬁned as Vth(t)–Vth(0) for transistors with W/L = 10/0.5lm.

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they typically are subjecting to a working voltage higher than the core devices.

6. Conclusions

In this work, we have fabricated strained channel NMOSFETs with ﬁve types of SiN capping layer by varying the N2ﬂow rate

and temperature during deposition. Both the tensile stress level and the device performance enhancement are found to increase with increasing N2ﬂow rate, especially in short-channel devices.

On the other hand, we found that the device immunity to hot-car-rier degradation is mainly affected by the hydrogen content, rather than the stress level. Therefore, SiN film with high tensile stress but low hydrogen content is ideally suitable for NMOSFETs, and nitro-gen-rich film can fulfill the requirement.

Acknowledgments

We would like to thank Kai-Hsiang Chan and the technical staff of National Nano Device Laboratories (NDL) for assistance in device fabrication. This work was supported in part by National Science Council of the Republic of China under Contract No. NSC 96-2221-E-009-207.

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