Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

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Modeling the ﬂoating-body eﬀects of fully depleted,

partially depleted, and body-grounded SOI MOSFETs

Mansun Chan

a,*

, Pin Su

b

, Hui Wan

c

, Chung-Hsun Lin

c

, Samuel K.-H. Fung

d

,

Ali M. Niknejad

c

, Chenming Hu

c

, Ping K. Ko

a

Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong

b_{Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC} c_{Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, USA}

d_{Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, ROC}

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

This paper describes a unified framework to model the floating-body effects of various SOI MOSFET operation modes, including body-contacted mode, partially depleted mode and fully depleted mode. As the operation mode is dimension and bias dependent, different modes can co-exist in a single SOI technology. A smooth transit from one type of operation mode to another is thus essential and has been included in the model. In addition, the floating-body effects can couple to a number of other SOI specific phenomena such as heating assisted impact ionization, gate tunneling induced dynamic behavior, and operation mode dependent small signal output resistance. A methodology to model the overall SOI MOSFET behavior due to the combination of multiple floating-body related effects will also be described. 2004 Published by Elsevier Ltd.

Keywords: SOI; SOI devices; Circuit simulation; Device model; SPICE; BSIMSOI

1. Introduction

As mainstream bulk CMOS technology scales to sub-100 nm, it becomes more challenging to keep up with the continuous reduction of device dimensions as predicted by the Moore’s Law. Silicon-on-insulator (SOI) tech-nology has emerged as an alternative to bulk CMOS technology to address the performance requirements for sub-100 nm devices. It has been demonstrated that SOI CMOS and its derivatives such as double-gate MOS-FETs can provide better performance with lower power consumption, making it very attractive for DRAM and microprocessor applications [1]. A major barrier to fully exploit the performance provided by SOI technology is

the immature design tool for designing circuit applica-tions. An important link between SOI technology and application design is a SPICE friendly compact SOI MOSFET model. A lot of eﬀorts have been devoted to SOI modeling and a number of compact models have been made available in the public domain [2–4]. Among them, BSIMSOI developed by Pin Su [4] at UC Berkeley has been chosen by the Compact Modeling Council [5] to be the industrial standard model adopted by major technology provide such as IBM. The selection is not totally based on model accuracy, but the ﬂexible archi-tecture that makes it easy to be adopted during process development even before device data is available [6].

While SOI MOSFETs have a lot of common features in terms of structure and behavior with mainstream bulk CMOS devices, they also have many subtle dif-ferences that require particular attention. In particular, the ﬂoating-body eﬀect is the key to understand the unique behavior in SOI MOSFETs. In this paper, the

*

Corresponding author. Tel.: 2358-8842; fax: +852-2358-1485.

E-mail address:[email protected](M. Chan).

0038-1101/$ - see front matter 2004 Published by Elsevier Ltd. doi:10.1016/j.sse.2003.12.012

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methodology used in BSIMSOI to model the floating-body effect is described. To be concise, only the features unique to SOI devices will be presented, and we assume the readers to be familiar with to the formulation of MOSFET model, which can be found in other publica-tion such as [7]. The paper first describes the different device structures available in SOI technology including body-contacted (BC) SOI MOSFET, partially depleted (PD) SOI MOSFET and fully depleted (FD) SOI MOSFETs and how the floating effects in these struc-tures are modeled. While the ‘‘structural’’ classification is conceptually simple, the different device types are actually categorized by operation modes rather than physical device structures. And different operation modes can co-exist in a single technology when dimen-sions and bias are varied. As a result, a unified floating-body model with smooth transition between different modes of operation is desired. As SOI technology is supposed to be meaningful only in small dimensions and low supply voltages, a number of device phenomena that are ignored in conventional MOSFETs can become significant and couple to the floating-body effects. This includes self-heating assisted impact ionization, gate current induced dynamic effects and frequency depen-dent performance parameters. A methodology to model these behaviors together with the floating-body effects will also be described.

2. Modeling floating-body effect in different SOI MOS-FETs

2.1. Body-contacted MOSFET

BC MOSFETs is widely used in critical analog cir-cuits like phase-lock loop. There are a number of ways

to provide body contact, but the most common one resemble the structure shown in Fig. 1. Unlike the sub-strate contact in bulk device, the body contact in SOI MOSFETs has a high resistance distributed along the width of the device due to the short channel length and thin body [8,9] as shown in the ﬁgure. The body resis-tance (RB) can be calculated by RB¼ Rbody W =L, where

Rbody is the resistivity per unit silicon ﬁlm thickness of

the body. While there have been proposal to use an effective resistance to approximate the body resistance, the approach cannot produce the gradual turn-on of the kink effect [10]. To fully account for the distributed effect of the body resistance, a wide SOI MOSFET has to be broken down into a number of smaller transistors in parallel as shown in Fig. 1(b) [11]. From a modeling perspective, a mechanism is required to contact the body terminal and turn-off related narrow width effect when decomposing the transistor into narrower ones. This option has been made available in BSIMSOI.

In addition to distributed-body resistance, the extra device area used to provide body contact creates an extra capacitive current path from drain to the body. This results in an enhanced frequency dependent out-put resistance (Rout) as shown in Fig. 2. For MOSFETs

without ﬂoating-body eﬀects, the drain-to-body and body-to-source capacitances behave like a short cir-cuit at high frequency and provide a second conductive path connect the drain-to-source through the body resistance. Hence, a decrease in Routis expected at high

frequency. However, the frequency drop appears at around 1 kHz, which is much lower than that required to turn-on the second conduction path through the substrate. A diﬀerent mechanism is responsible for this observation.

The decrease of Routis attributed to the inﬂuence of

ﬂoating-body eﬀect, which can be explained by the small

Fig. 1. (a) Common layout of a four-terminal side-body SOI MOSFET and (b) method to simulate distributed eﬀect of body resis-tance. An accessible B node is provided in BSIMSOI to facilitate the simulation.

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signal equivalent circuit shown in Fig. 3 [12]. The body potential is supposed to be connected to ground by the body contact, but it cannot be completely grounded due to the distributed-body resistance RB. When a small

signal drain voltage vdis applied, the body potential vbis

modulated, which in term causes VT to ﬂuctuate. It

provides a mechanism for the drain voltage to modulate VTwhich shows up in the Routcharacteristics. The small

signal model given in Fig. 3 can be used to track the ﬂuctuation of vbas a result of vdvariation which is then

fed back to the calculation of VT. At low frequency, this

drain coupling effect is insignificant when the body resistor RBcan still provide an effective discharging path

for the capacitive current from the drain. So, the value of RBwill aﬀect the frequency at which Routdegradation

appears. The model has been extensively veriﬁed by measurement data from many devices with diﬀerent dimensions and under various bias conditions.

2.2. Partially depleted SOI MOSFET

While a BC SOI MOSFET can produce bulk MOS-FET like I–V characteristics that we are familiar with, the use of substrate contact consumes extra area, and is generally not desirable in circuit applications. PD MOSFETs with floating body are still the most popular technology used in manufacturing ICs in company like IBM. The accurate modeling of PD MOSFETs again has to do with the modeling the impact of floating body on the device behaviors. In BSIMSOI, an equivalent circuit as shown in Fig. 4 is used to calculate the float-ing-body voltage under the influence of various body currents.

In DC operation, the impact ionization current (Iii)

[13] at the drain ﬂows to the body and forward biases the source-to-body diode so that the diode current is equal to the Iii. Thus the ﬂoating-body potential is dictated by

the I–V characteristic of the source to body diode. The diode voltage between the body and source increases the body voltage (VB), which in turn cause a reduction in

threshold voltage VT. The change in VTcauses a sudden

increase in drain current when the impact ionization becomes signiﬁcant. It results in the famous kink eﬀect in the drain current versus VDcurve as shown in Fig. 5.

This eﬀect can be modeled eﬀectively by monitoring the degree of forward bias of the body-to-source junction as a function of Iii, which is a strong function of VD. The

diode model has to include a number of non-uniform lateral doping eﬀects due to the use of halo (pocket implant) in most of the industrial process. The calcu-lated VBS is used to modify VT using the body eﬀect

Fig. 2. Characteristics of output resistance (Rout) versus

fre-quency at diﬀerent drain voltage. Routis normalized to by its

DC value to observe the frequency dependence.

+ -+ -v_b vd C_D C_B _R B i_ii

Fig. 3. Small signal equivalent circuit for the ﬂoating body. CD

is dominated by the capacitance between the drain and body contact. CBrepresents the equivalent capacitance from body to

AC ground. RB is the body resistance and Iii is the impact

ionization current. Drain Source Body V_B Frontgate Backgate I_gb I_ii I_gidl I_bd dQ_d dt dQ_bg dt dQ_fg dt dQ_s dt I_bjt I_bs

Fig. 4. Circuit representation of the ﬂoating-body potential calculation under the inﬂuence of various DC and charging currents: Igb––oxide tunneling current; Iii––impact ionization

current; Igidl––gate induced drain leakage; Ibjt––bipolar current;

Ibs––recombination current; Ibd––junction leakage. Qg, Qbg, Qd

and Qs represent the frontgate charge, back charge, drain

charge and source charge respectively. Qdand Qrmsmainly arise

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equation VT¼ VT0þ cð

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2/_B VBS

p

pffiffiffiffiffiffiffiffi2/_BÞ, which will then be used to calculate the drain current.

During time domain simulation, transient charge and capacitive coupling between all the terminals have to be accounted for in the calculation of the body potential. VBSis determined by the initial body charge as well as the

displacement current resulting from capacitive coupling of the body node to other terminals. For example, when the gate is switched from low to high, it causes an initial increase in the body voltage beyond the equilibrium value. The body voltage will then settle to the equilib-rium value governed by a time constant determined by the combined eﬀects of carrier generation/recombination rate, gate-induced-drain-leakage, impact ionization current, gate tunneling current, and body-to-source diode current. Various body leakage and displacement currents that determine the ﬂoating-body potential are included in the body voltage model shown in Fig. 4. From the equivalent circuit, a nodal equation at the body node can be written as:

dQg dt þdQbg dt þ dQd dt þ dQs dt

þðIiiþIgidlþIbsþIbdÞþIgb¼ 0

ð1Þ The SPICE solution to the diﬀerential equation at the body node depends not only on the present terminal voltages, but also the initial conditions of the body charge (past history). The behaviors of the body po-tential with respect to VG and VD switching from the

model and 2-D device simulation are compared and the

results are shown in Fig. 6 with an input ramp much fast that the RC time constant o the subcircuit given in Fig. 4. The model can predict the correct behavior of the body potential as a function of both VDand VG

switch-ing.

2.3. Fully depleted SOI MOSFET

In order to suppress short channel effects, the silicon film thickness has to be scaled together with the channel length in advanced device structure. As the silicon thickness becomes thinner than the depletion depth of the body, it operates in the FD mode and the observed floating-body effect decreases. FD mode is not too much different from PD mode except (1) the threshold voltage becomes silicon film thickness and back-gate bias dependent [14]; (2) backgate can be more effectively coupled to the frontgate [15]; (3) close to ideal sub-threshold swing of 60 mV/dec at room temperature [16];

Fig. 5. I–V characteristics of a PD SOI MOSFET with excess current due to the kink effects when the body is floating. The lines indicate the fitting from BSIMSOI with the floating-body effects included.

Fig. 6. The body potential predicted by BSIMPD in (a) fast gate voltage ramp and (b) fast drain voltage ramp compared with result from 2-D device simulation.

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and (4) reduction of kink effect [17]. All these effects can be handled in a unified way using the body-to-source barrier-lowering concept.

The main operational diﬀerence between PD mode and FD mode operation is the body-to-source potential barrier at the backgate. In the PD mode at equilibrium, it is the same as the built-in potential of the body-to-source diode as shown in Fig. 7. When the ﬁlm thickness is reduced and the device starts to operate in the FD mode, the potential barrier between the source and body at the backside is lowered by DVbi as shown in Fig. 7,

which is equivalent to the source-to-body diode in the PD mode is forward biased. This lowering also depends on the backgate bias. Using this DVbi, the threshold

voltage lowering with reference to the PD MOSFET case can be modeled. In practice, the VTused in compact

model is usually extracted rather than calculated and thus is absolute value is not very important in a practical modeling framework. The more important eﬀect is the modulation of DVbi under diﬀerent terminal biases that

aﬀect the device output characteristics. The diode char-acteristic between the body and source is determined by DVbi as shown in Fig. 8, where DVbi¼ 0 correspond to

the PD case. DVbi as a function of silicon ﬁlm thickness

and back gate bias, which can be expressed as DVbið/SÞ ¼ CSi CSiþ Cbox /_S qNch 2eSi t2 Siþ DVDIBL þ geðLeffÞ Cbox CSiþ Cbox ðVbgs VfbbÞ ð2Þ _{where /}

S is the surface band bending that can be

approximated by /S¼ /_ON Cox Coxþ Cð _Si1þCox1Þ 1ðVT VGSÞ for VGS< VT /_ON for VGSP VT ( ð3Þ /_ONin generally can be represented by 2/_B. DVDIBLand

ge are correction terms due to

drain-induced-barrier-lowering and short channel eﬀects. In BSIMSOI, they are given by DVDIBL¼ Dvbd0 exp Dvbd1 Leff 2l þ 2 exp Dvbd1 Leff 2l Vbi ð 2/BÞ ð4Þ

g_effðLeffÞ ¼ K1b K2b exp

Dk2b Leff 2l þ 2 exp Dk2b Leff 2l ð5Þ

The values of the parameters can be referred from the BSIMSOI manual [18]. The ﬁrst term in the equation represents the frontgate coupling. Nch is the eﬀective

channel doping, which may vary with channel length due to non-uniform lateral doping. The second term of

Fig. 7. Body-to-source band diagram at the back side indicat-ing the lowerindicat-ing of built-in potential relative to the value cal-culated from the body/source PN junction. FD devices has a lower barrier (larger DVbi) to begin with and more stable under

the inﬂuence of external currents.

Fig. 8. The source-to-body diode characteristics as a function of DVbi from a generic SOI NMOSFET with diﬀerent channel

doping of 1· 1017_cm3_{with diﬀerent ﬁlm thickness to give the}

corresponding DVbi. FD device can accommodate larger current

(IBS) before a change in VBSis necessary due to its higher initial

DVbi. As VBSin FD devices varies at a smaller range than in the

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the equation represents the backgate coupling. The minimum value of DVbiis ﬁxed at zero, as it is physically

impossible to go negative.

From the expression, FD devices with thin silicon ﬁlm thickness give higher DVbi. As a result, higher impact

ionization current from the drain (Ibs) can be

accom-modated before it causes a change in VBS as shown in

Fig. 8. The reduced sensitivity of VBS to impact

ioniza-tion current gives a reduced ﬂoating-body eﬀect. According to Fig. 8, DVbi can be used to indicate the

degree of full depletion of a SOI MOSFET. For FD devices with small DVbi, ﬂoating body induced

phe-nomena like the kink eﬀects can still be observed.

2.4. Transition for PD and FD including dynamic depletion

State-of-the-art SOI technology requires FD devices with extremely thin silicon ﬁlm thickness to suppress SCE. At the same time, devices with multiple VT’s are

often used to optimize the tradeoﬀ between speed and standby power. It is then possible or even preferred to have devices with diﬀerent TSi in a process. When

com-bined with the use of pocket implants, it is generally observed that FD and PD devices co-exist in the same technology. Furthermore, the same devices can behave as either PD or FD depends on bias conditions. As observed from the transistor characteristics shown in Fig. 9, the device can operate at PD mode (with sub-threshold swing of 102 mV/dec) or FD mode (with subthreshold swing of 67 mV/dec) depends on the

backgate bias. A dynamic transition with the gate volt-age can also be observed, which is referred as dynamic depletion (DD) [19]. It occurs because at a low gate voltage, the depletion width from front oxide interface to the silicon ﬁlm is small and the device operates at the PD mode. When the gate voltage increases, the depletion region extends to the back gate and eventually becomes FD [20].

The three modes of operation (FD, PD and DD) can be captured in a uniﬁed way by modeling the body-to-source built-in potential lowering using the concept of DVbi. First, DVbi is calculated and using Eq. (2) with

known TSi, toxand gate voltages. Then, assumes the ﬁlm

thickness is inﬁnite in PD model and calculates the corresponding VBSwhen the device is operating in PD

mode using the equivalent circuit given in Fig. 4. DVbiis

then compared with the VBSin PD. If this VBSbecomes

smaller than DVbi, then the body-to-source barrier

low-ering is mainly caused by DVbiand the FD characteristics

of the device dominates. If some mechanism, such as impact ionization at high VDS, gives a higher VBS, the FD

mode with the calculated DVbi can no longer

accom-modate the currents from the body-to-source as shown in Fig. 8. In this case, the body potential is modulated by the VBSin the PD mode rather than maintaining a

con-stant value at DVbi. Therefore, an eﬀective body potential

can be formulated by selecting the smaller VBSand DVbi

as shown in Fig. 10 to monitor the body potential. The eﬀective VBS concept provides a uniﬁed approach to

model the characteristics of floating-body effects due to fluctuation of body potential in PD, FD and DD devices.

Fig. 9. The PD/FD transition under diﬀerent backgate biases for a MOSFET with 60 nm silicon ﬁlm thickness and 10 nm of tox. Correctness in calculating the DVbi can accurately predict

the observed eﬀect.

Fig. 10. The body potential in the uniﬁed model approaches. VBSis ﬁrst solved as in PD model, which return to DVbifor ideal

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3. Advanced models for ﬂoating-body eﬀects in deep-submicron SOI MOSFETs

In the state-of-the-art SOI process, a number of newly observed behaviors cannot be explained using some commonly known theories. New physics have to be included before these observations can be explained. All these observations, however, are still directly or indirectly linked to the ﬂoating-body eﬀect and they are explained below.

3.1. Thermal related eﬀects

The kink effect has been regarded as the signature of PD SOI MOSFET, and it has been attributed to impact ionization induced substrate current. With the reduction of power supply voltage to below 1 V according to the technology scaling roadmap, the impact ionization the-ory predicts that the kink effect will be eliminated be-cause the carrier acceleration energy becomes less than the bandgap energy of silicon, which is around 1.1 V. However, the kink effect can still be observed in SOI MOSFETs operating at a drain voltage below 1 V. It requires a correction to the existing substrate current model.

The observed kink eﬀect can be explained by the lattice temperature assisted subbandgap impact ioniza-tion [21]. In SOI MOSFET, this eﬀect is enhanced due to self-heating. The Arrhenius plot given in Fig. 11 shows the relationship between impaction ionization current (normalized by ID) and the reciprocal of temperature.

The required activation energy to cause impact ioniza-tion under a given drain voltage is given by Ea¼ Eg qVD, and this Ea has to be supplied by the

lattice temperature. The smaller the Ea, the larger the

impact ionization current at a given temperature. Thus, the thermally assisted impact ionization model at qVD< Eg is given by: Isub ID / exp ðEg qVDÞ kT ð6Þ

where Isubis the substrate current. The model has been

veriﬁed by a lot of experimental data and the results are also plotted in Fig. 11, indicating the correct dependents of impact ionization current with respect to temperature. The thermal driven sub-Eg impact ionization model

predicts a linear dependent between lnðIsubÞ and VD. On

the other hand, the traditional theory predicts that lnðIsubÞ depends on 1=VD when the impact ionization is

electric-ﬁeld driven. In some immediate VD, a smooth

transition from thermal driven impaction to electric-ﬁeld driven impact ionization is required. In BSIMSOI, this is modeled by Isub ID / exp VD b₀þ b1VDþ b2VD2 ð7Þ

where b0, b1, b2 are ﬁtting parameters. At low

temper-ature region, we observed the experimentally determined activation energy is smaller than the theoretical predic-tion, which indicates other energy gain mechanisms are involved in the process. One of these mechanisms is

Fig. 11. Measured Isub=IDversus reciprocal temperature at (a) VGS¼ 0:4 V and (b) VGS¼ 0:8 V of a SOI NMOSFET. The uncorrected

curves are the total measured substrate current while the corrected curves have the temperature dependent junction leakage currents subtracted to display the intrinsic characteristics of the impact ionization current.

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electron–electron scattering that provide an additional source for carrier heating as proposed in [22–24]. This phenomenon is more prominent when the channel electron concentration is high at large VGS. It agrees with

the observation that the deviation between experimental data and model prediction at low temperature becomes larger when the gate voltage is increased from 0.4 to 0.8 V as shown in Fig. 11.

3.2. Impact of gate tunneling current on ﬂoating-body eﬀect

In bulk MOSFET, the gate tunneling current adds an additional component to the DC currents that in most cases, can be handled by simple superposition of all currents. In a SOI MOSFET, the gate tunneling current contributes a conduction path to the floating body and modulates the body-to-source voltage [25]. As a result, it affects the intrinsic value of the drain-to-source current. The effect have to be modeled by adding the impacts of various gate leakage currents to the floating-body

po-tential, which have been included in the equivalent cir-cuit given in Fig. 4. This body voltage is used to calculate VBS in PD operation, or the equivalent body

voltage in the uniﬁed PD/FD model.

To investigate the impact of the gate tunneling cur-rent on the behavior of a SOI MOSFET, the turn-on responses by a step gate voltage input are simulated with and without the gate tunneling model activated. The results are shown in Fig. 12. Without gate tunneling, body charge decreases due to carrier recombination once inversion layer is formed and shield the gate-to-body coupling. With oxide tunneling, the gate current con-tinues charging the body even after the formation of the inversion layer. The body potential continues to increase until the forward diode current from the body-to-source becomes equal to the gate current. The time to reach this equilibrium depends on the forward bias characteristics of the body-to-source diode. In this particular simula-tion, the time constant (tp) for PMOSFET to reach

steady state is longer than that of NMOSFET (tn) due to

smaller recombination current at the junction and net

Fig. 12. Impact of gate tunneling (IgMod¼ 1) on the transient behavior of (a) NMOSFET; (b) PMOSFET; and (c) body current. Simulation results without body current (IgMod¼ 0) are also included for comparison. Simulation parameters are VDD¼ 1:5 V,

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charge injection to the source. Thus, the induced for-ward body potential for PMOSFET (dVbp) is larger than

of the NMOSFET (dVbn).

3.3. Modeling output resistance SOI MOSFET at high frequency

At high frequency, it is observed that FD devices have a higher output resistance than PD devices and the drain voltage has a strong influence at the output resistance [26]. The observation can be explained by the schematic shown in Fig. 13. At high frequency, the drain-to-body and source-to-body capacitor behavior like a short circuit and create another current path from the drain-to-source. However, the resistance from the drain-to-source is under the influence of the terminal bias and mode of operations. In particular, the body resistance become very large and can be regarded as infinite in FD mode.

Besides the additional current path, a more impor-tant eﬀect is the modulation of body-to-source potential though this new current path. A good representation of the physical structure is the addition of a series RC branch in parallel to CDin Fig. 13.

4. Conclusion

In this paper, a framework to model the floating-body effect of SOI MOSFETs has been described in detail. The approach has been used to formulate the BSIMSOI model, which is the current industrial stan-dard SOI MOSFET model. The behavior of SOI MOSFETs, in a large part, is governed by the floating-body effect. The accurate modeling of the floating-floating-body effect is essential to capture a number of unique char-acteristics of SOI MOSFETs.

Acknowledgements

This work was supported by SRC under contract #2000-NJ-795, the DARPA under Air Force contract #F19628-00-C-0002 and Research Grant Council of Hong Kong under NSFC_HKUST27.

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