Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices

Process-variation- and random-dopants-induced threshold voltage fluctuations

in nanoscale planar MOSFET and bulk FinFET devices

Yiming Li

_{, Chih-Hong Hwang, Hui-Wen Cheng}

Department of Communication Engineering, National Chiao Tung University, P.O. Box 25-178, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history:

Received 29 September 2007 Accepted 17 February 2008 Available online 5 March 2008

Keywords:

Threshold voltage fluctuation Random dopant

Process-variation Gate-length deviation Line-edge roughness Modeling and simulation

a b s t r a c t

Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (Vth) fluctua-tion is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the depen-dency of process-variation and random-dopant-induced Vth fluctuation on the gate oxide thickness scaling in 16 nm metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated. Fluctua-tions of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO2for the 1.2 and 0.8 nm EOTs, Al2O3for the 0.4 nm EOT and HfO2for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of Vthfluctuations with the gate oxide thickness scaling (using high-j dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device’s scaling and have potential in the nanoelectronics application.

Ó 2008 Elsevier B.V. All rights reserved.

1. Introduction

As the dimension of complementary metal–oxide–semiconduc-tor (CMOS) devices shrunk into sub-90 nm scale, threshold voltage (Vth) fluctuations resulting from such as the short channel effect

and random dopant are pronounced[1–15]. The random-dopant-induced fluctuation is mainly from the random nature of ion implantation. The gate-length deviation and line-edge roughness could be attributed to the short channel effect. Fluctuation is get-ting worse due to serious short channel effect when the dimension of device is further scaled. Consequently, it affects the design win-dow, yield, noise margin, stability, and reliability of ultra large-scale integration circuits. The tolerance of fluctuation has to be controlled even strictly with increases in the number of transistors as technology advances. The use of thin gate oxide is one of effec-tive ways to suppress the process-variation- and random-dopant-induced Vthfluctuation[6]. Our recent work has demonstrated that

the Vthfluctuation of a 15 nm planar metal–oxide–semiconductor

field effect transistor (MOSFET) device could be suppressed by 20%, as the gate oxide scales is scaled down from 1.2 nm to 0.8 nm[6]. However, ongoing scaling of gate oxide thickness may raise problems of process controllability, leakage current, and

reli-ability. The use of a high-j dielectric is a key to enhance the perfor-mance of such devices[16–18]. For devices with vertical channel structures, such as fin-typed FETs (FinFETs), immunity against fluc-tuation is also fascinating, because they possess better channel controllability[7,19–22]. Study of the effectiveness of fluctuation suppression and the mechanism against fluctuations according to these two approaches will be an interesting and benefit the nan-odevice technology.

In this paper, the dependency of process-variation- and ran-dom-dopant-induced threshold voltage fluctuation on the gate oxide thickness scaling in 16 nm nano-MOSFETs is examined. To-gether with statistically generated process-variation-induced gate lengths and the large-scale doping profiles, the Vthfluctuation for

each studied devices is computed by solving a set of three-dimen-sional (3D) quantum correction transport equations[23–25]. We notice that the device’s threshold voltage and the mobility of the explored planar device (the case of 1.2 nm EOT) are calibrated with the measured data[6]. Fluctuations of the studied planar MOSFETs with equivalent oxide thicknesses (EOT) ranging from 1.2 nm to 0.2 nm, where Al2O3 is for the 0.4 nm EOT and HfO2 is for the

0.2 nm EOT are then compared with the results for 16 nm bulk Fin-FETs[7,19–22]. The 16-nm-gate planar MOSFET with the 0.2 nm EOT is demonstrated to offer similar immunity against fluctuation as the 16 nm-gate bulk FinFET device with the 1.2 nm EOT. Additionally, its found the immunity of the planar MOSFET against

0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.02.013

* Corresponding author. Tel.: +886 3 571 2121x52974; fax: +886 3 5726639. E-mail address:[email protected](Y. Li).

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Microelectronic Engineering

fluctuation is limited by structural limitations while the multiple-gate FET, such as FinFETs, can overcome challenges with device scaling and is favorable in the era of nanoelectronics.

This article is organized as follows. In Section2, we describe the analyzing technique. In Section3, we present and discuss the re-sults. Mechanism of process-variation- and random-dopant-in-duced fluctuation are shown and discussed. Finally, we draw conclusions and suggest future work.

2. Simulation methodology

The threshold voltage fluctuation is assumed to be contributed from the random-dopant and short channel effect. Effects of gate-length deviation (Lg), and the line-edge roughness (LER) are

re-sulted from process-variation and belong to the short channel ef-fects The random-dopant and short channel effect are independent sources of fluctuation, and the standard deviation of the total threshold voltage, Vth,total, can be expressed by the

follow-ing relation r2_V th;total¼ r 2 Vth;RDþ r 2 Vth;Lg=LER; ð1Þ

where rVth;RDis the random-dopant-induced fluctuation, rVth;Lg=LER is

fluctuations caused by the gate-length deviation and line-edge roughness.

Fig. 1 presents the structures of the studied devices, where

Fig. 1a and b are the planar MOSFETs and the bulk FinFETs. The EOT of planar MOSFET ranges from 1.2 nm to 0.2 nm and the EOT of bulk FinFET is fixed at 1.2 nm. The used dielectric materials are summarized inTable 1, where SiO2 is used for a gate oxide

thickness of 1.2 nm and 0.8 nm, Al2O3is for a gate oxide thickness

of 0.4 nm, and HfO2 is for a gate oxide thickness of 0.2 nm. The

nominal channel doping concentration of the devices herein is 1.48  1018cm3_{. The devices have a 16 nm gate and a}

workfunc-tion of 4.4 eV.

To elucidate the effect of random fluctuations of the number and location of discrete dopants in the device channel, 758 doping islands are initially generated in an (80 nm)3cube, in which the equivalent doping concentration is 1.48  1018_cm3_{, as shown in}

Fig. 2a. The (80 nm)3_{cube is then partitioned into 125 sub-cubes}

of volume (16 nm)3_{. The number of dopants may vary from zero}

to 14, and the average number is six, as shown inFig. 2b–d, respec-tively. These 125 sub-cubes are then equivalently mapped into the channel region of the device for discrete dopant simulation, as shown inFig. 2e and f. All statistically generated discrete dopants are incorporated into the large-scale 3D device simulation using the parallel computing system[26–28]. Characteristic of each de-vice is obtained by solving a set of Poisson equation, electron-hole current continuity equations, and density-gradient equation[23– 25]. This approach enables us to calculate the fluctuations of elec-trical characteristics that induced by the randomness of the num-ber and position of dopants in the channel region to be investigated. This statistically sound full-scale 3D ‘‘atomistic” de-vice simulation technique considers the computational cost and accuracy simultaneously.

Furthermore, we apply the statistical approach to evaluate the effect of process-variation-induced Vthfluctuation, rVth;Lg=LER [29].

The magnitude of the gate-length deviation and the line-edge roughness are extracted from the projections of the ITRS 2005 for different technology nodes[30]. A look-up table of the threshold voltage vs. gate length is established, as shown inFig. 3. It enables us to evaluate the threshold voltage with respect to the deviation of gate-length deviation and line-edge roughness, which following

Source Drain Silicon oxide Lg Top-Gate Source Drain Silicon Lateral-Gate Top-Gate

a

b

Fig. 1. An illustration of the studied: (a) planar MOSFET and (b) bulk FinFET.

Table 1

The used dielectric materials in this study, SiO2is used for the cases of the 1.2 and

0.8 nm EOTs, Al2O3is for the case of the 0.4 nm EOT and HfO2is for the case of the

0.2 nm EOT

Material Dielectric constant This work (nm)

SiO2 3.9 EOT = 1.2/0.8 Al2O3 8–11.5 EOT = 0.4 HfO2 25–30 EOT = 0.2 16nm 16nm Dopants in (16nm3) Cube 0 5 10 15 Histogram (number) 0 5 10 15 20 25 80nm 8 0n m

1.48 10

_cm

_{758 dopants in}

(80nm)

_cube

0 dopants in

a (16nm)

cube

14 dopants

in a (16nm)

cube

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 2. (a) Discrete dopants randomly distributed in (80 nm)3

cube with an average concentration of 1.48  1018

cm3

and then partitioned into 125 sub-cubes of (1-6 nm)3

, where the numbers of dopant in sub-cubes may vary from zero to 14, as shown in (b), (c), and (d). These sub-cubes are then equivalently mapped into ch-annel region of studied devices, (e) and (f), for dopant position/number-sensitive simulation. It means that for each explored device there are 125 cases of the 3D device simulation have to be performed.

the roadmap of ITRS that 3rLg= 0.9 nm and 3rLER = 1.2 nm for the

22 nm node and 3rLg= 0.7 nm and 3rLER = 0.8 nm for the 16 nm

technology node, as the inset table ofFig. 3. Thus, we can calculate the standard deviation of threshold voltage resulting from the deviation of gate length and the roughness of line-edge. The accu-racy of the simulation is verified by comparing the simulated fluc-tuation results and the measured data of experimentally fabricated 20 nm devices[6]. The threshold voltages of the studied devices are adjusted to 140 mV. The threshold voltage is derived from a current criterion of 107 _{(W/L) (A), where the W and L are the}

width and length of device, respectively.

3. Results and discussion

Fig. 4plots the gate capacitance (Cg) as a function of the EOT,

where the solid line shows the planar MOSFETs with various EOT and the square symbol indicates the bulk FinFET device with 1.2 nm EOT. The planar MOSFET with 0.4 nm EOT, where Al2O3is

used for gate dielectric, exhibits a similar gate capacitance with the bulk FinFET device with 1.2 nm EOT. Since the value of gate capacitance is one of the indexes for the channel controllability of device, the bulk FinFET device with 1.2 nm EOT is expected to have similar immunity against process-variation induced fluctua-tion with the planar MOSFET with 0.4 nm EOT. This assumpfluctua-tion is then verified in Fig. 5, which presents the

process-variation-induced Vthfluctuation, rVth;Lg=LER, of the planar MOSFETs and bulk

FinFETs. The use of thin gate oxide and high-j dielectric material is effective in suppression of process-variation-induced Vth

fluctu-ation. As expected the process-variation-induced Vthfluctuation of

the planar MOSFET with 0.4 nm EOT is very similar that of the bulk FinFET device with 1.2 nm EOT. From the viewpoint of process-variation-induced fluctuation, the bulk FinFET device with 1.2 nm EOT exhibits a similar immunity against process-variation-induced fluctuation with the planar MOSFET with 0.4 nm EOT. How-ever, will the trend still valid in the random-dopant-induced fluctuation?

Fig. 6shows the random-dopant-induced Vthfluctuation, rVth;RD,

of the studied devices. The random-dopant-induced Vthfluctuation

decreases significantly as the EOT is scaled down. However, even thought the planar MOSFET with 0.4 nm EOT has a similar gate capacitance with bulk-FinFET with 1.2 nm EOT, the immunity against random-dopant-induced fluctuation of these two devices is rather different. The bulk FinFET device shows a better immunity against fluctuation than expected. It exhibits a similar Vth

fluctua-tion as the planar MOSFET device with 0.2 nm EOT, where HfO2is

used for gate dielectric.

To further investigate the reason why bulk FinFET can provide a better immunity against random-dopant-induced fluctuation, the potential distributions extracted 1 nm below the top gate of chan-nel are examined, where the applied gate voltage (VG) is 1 V and

the applied drain voltage (VD) is 0 V. The potential barriers, shown

inFig. 7b–f, are induced by the corresponding dopants at positions:

Gate Length (nm) 10 20 30 40 Vth (V) 0.05 0.10 0.15 0.20 0.25 0.30 Planar (EOT=1.2nm) Planar (EOT=0.8nm) Planar (EOT=0.4nm) Bulk FinFET (EOT=1.2nm) Planar (EOT=0.2nm) Lg Δ Vth Δ LER Lg Vth, /

σ

σ

Short channel effect

0.8 1.2 LER, 3 sigma (nm) 0.7 0.9 Lg, 3 sigma (nm) 16 22 Gate length (nm) 0.8 1.2 LER, 3 sigma (nm) 0.7 0.9 Lg, 3 sigma (nm) 16 22 Gate length (nm)

Fig. 3. The threshold voltage roll-off of the studied devices, where the variation follows the projection of ITRS 2005 roadmap. These results are used to estimate the Vth fluctuation resulting from the gate-length deviation and the line-edge

roughness. EOT (nm) 0.2 0.4 0.6 0.8 1.0 1.2 Cg (fF) 0.00 0.01 0.02 0.03 0.04 0.05 16nm Bulk FinFET with EOT=1.2nm 16nm Planar MOSFET

with various EOT

0.0203 0.02

Fig. 4. The gate capacitance (Cg) as a function of the EOT, where the solid line shows

the planar MOSFETs with various EOT and the square symbol indicates the bulk FinFET device with 1.2 nm EOT.

EOT (nm) 0.2 0.4 0.6 0.8 1.0 1.2 6 8 10 12 14 16 18 20 16nm Bulk FinFET with EOT=1.2nm

16nm Planar MOSFET with various EOT Vt,Lg/LER (mV) σ 11.93 12.15

Fig. 5. The process-variation-induced threshold voltage fluctuation for the studied devices. EOT (nm) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 30 40 50 60 Vt,RD (mV) 16nm Bulk FinFET with EOT=1.2nm 16nm Planar MOSFET with

various EOT

28.31 29.89

σ

Fig. 6. The random-dopant-induced threshold voltage fluctuation for the studied devices.

A, B, and C, respectively, as shown inFig. 7a. The potential barrier is largest at C, because two discrete dopants are located close to each other there. For planar MOSFETs with different EOTs, the sizes of the potential barriers are suppressed as the equivalent gate oxide thickness is reduced. The results for planar MOSFETs, as displayed inFig. 7b–e are then compared with that of a bulk FinFET device, as shown inFig. 7f, indicating that the potential barriers of bulk Fin-FET are smaller than those of planar MOSFin-FETs, especially at posi-tion A. The potential barrier induced by corresponding dopant in A is significantly reduced in bulk FinFET device because the chan-nel potential is effectively controlled by the top- and lateral-gates of the device at position A. The difference between the gate struc-tures shows the difference between the mechanisms against fluc-tuations of the planar and bulk FinFET devices.

Fig. 8shows the lateral side potential distributions of the stud-ied devices.Fig. 8b and c show the potential contours of the nom-inal (continuous channel doping concentration: 1.48  1018_cm3₎

and discrete dopant fluctuated cases of bulk FinFETs with 1.2 nm EOT.Fig. 8d–h show the nominal and discrete dopant fluctuated cases of planar MOSFETs with EOT scaling. For the discrete dopant fluctuated bulk FinFET device inFig. 8c, although the potential dis-tribution is disturbed by a dopant that is located on lateral side of the channel, the overall potential distribution in the case of

fluctu-ation is still quite similar to that in the nominal case. However, for MOSFET, as shown inFig. 8e, the overall potential distribution is distorted significantly. The distortion is mitigated as the equivalent gate oxide thickness is scaled down, as shown inFig. 8f–h. This re-sult reconfirms the effect of the lateral gate in bulk FinFET devices in suppressing potential fluctuations.

Fig. 9plots the top and lateral views of the on-state current den-sity (VG= 1 V; VD= 1 V) of planar and bulk FinFET devices with

1.2 nm EOT. All cross-sectional plots are from 1 nm below the top and lateral side of channel surface. The top views of the chan-nel, as presented inFig. 9b and e, reveal that bulk FinFET device provides a larger and more uniform current distribution than the planar MOSFET due to the smaller fluctuation of potential. The lat-eral views of channel, as shown inFig. 9c and d; f and g, show that the current conducting paths of planar MOSFETs are easily dis-turbed by discrete dopants. In the bulk FinFET device, even current conducting paths are retarded in parts of channel surface; the tri-gate structure of bulk FinFETs provides more alternative con-ducting paths that prevent a significant fluctuation of conduction current. Thus, benefiting from the superiority of the vertical chan-nel structure, the bulk FinFET device suppresses potential fluctua-tions and maintains a more stable conduction current than the planar MOSFET.

Fig. 10 plots the on-/off- state current characteristics of the studied devices. For devices with similar on-state current (Ion),

the maximum difference of off-state current (Ioff) is declined from

approximately 2000 nA/um–800 nA/um as the EOT is scaled from 1.2 nm to 0.2 nm. Comparing the results for planar MOSFETs with those of bulk FinFETs, even though the planar device with 0.4 nm and 0.2 nm EOT has a better on-off state characteristic, the bulk FinFET device exhibits a smaller current fluctuation (about 600 nA/um). The bulk FinFET device can provide a more uniform potential distribution and a more stable current flow than that of the planar MOSFET. The additional structural improvement of bulk

Fig. 7. Top-gate potential contours of the planar MOSFETs with various EOT (b) EOT = 1.2 nm, (c) EOT = 0.8 nm, (d) EOT = 0.4 nm, (e) EOT = 0.2 nm) and (f) bulk F-inFETs with 1.2 nm EOT. The distributions of potential barriers are induced by the corresponding dopants location (i.e., A, B and C). The corresponding distribution of discrete dopants is shown in (a) and all the plots are extracted 1 nm below the gate oxide.

Fig. 8. Lateral-gate off-state potential contours for the studied planar MOSFET and bulk FinFET devices, where (b) and (c) show the nominal (continuously doped) and discrete dopant fluctuated cases of bulk FinFETs. The nominal and discrete dopant fluctuated cases of planar MOSFETs with different EOTs are shown in (d)–(h).

FinFET devices enhances the immunity of device against random-dopant-induced fluctuation, which cannot be evaluated from the trend of gate capacitance.

The process-variation- and random-dopant-induced Vth

fluctua-tions are summarized inFig. 11. In this study, the device with best immunity against process-variation- and random-dopant-induced Vthfluctuations are the planar MOSFETs with 0.2 nm EOT and the

bulk FinFETs with 1.2 nm EOT. Considering the total Vthfluctuation

according to the relation of Eq.(1), the Vthfluctuation is dominated

by random-dopant effect and the bulk FinFETs with 1.2 nm EOT shows a similar immunity against fluctuation with the planar MOSFETs with 0.2 nm EOT, as shown inFig. 12.Table 2 summa-rizes the components and total Vth fluctuations for the studied

devices. Result of this study confirms the suppression of fluctua-tions with the gate oxide thickness scaling. The immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations and the bulks FinFET device can alleviates the chal-lenges of device’s scaling and have potential in the nanoelectronics application.

4. Conclusions

The threshold voltage fluctuations caused by the random dop-ant effect, the gate-length deviation, and the line-edge roughness has been calculated and compared for the nanoscale planar MOS-FETs and bulk FinMOS-FETs. Fluctuations of the studied planar MOSMOS-FETs with EOT from 1.2 nm to 0.2 nm were compared with the results for 16 nm bulk FinFETs. Result of this study has confirmed the sup-pression of fluctuations with the gate oxide thickness scaling. The

Fig. 9. Cross-sectional views of on-state current density distribution in channel of device, where (b), (c), and (d) show the planar MOSFET device and (e), (f), and (g) show the bulk FinFET device. The corresponding distribution of discrete dopants is shown in (a) and all the cross-section plots are extracted 1 nm below the channel surface. I_on (uA/um) 0 500 1000 1500 2000 2500 3000 3500 Ioff (nA/um) 0 500 1000 1500 2000 2500 3000 FinFET (EOT=1.2nm) Planar (EOT=1.2nm) Planar (EOT=0.8nm) Planar (EOT=0.4nm) Planar (EOT=0.2nm) 2000 nA/um 1500 nA/um 1000 nA/um 800 nA/um 600 nA/um

Fig. 10. Ion–Ioffcurrent characteristics of the studied 16-nm-gate planar MOSFET

and bulk FinFET devices.

EOT (nm) 0.2 0.4 0.6 0.8 1.0 1.2 1.41 .6 0 10 20 30 40 50 60 70 Lg/LER

Random dopant effect (RD)

Bulk FinFET (1.2nm EOT)

Vth Fluctuation (mV)

Planar MOSFET

Fig. 11. Components of the Vthfluctuation of the explored devices. The right most

set of bars are the Vthfluctuation of 16 nm bulk FinFET with EOT 8 1.2 nm and the

others are the planar MOSFETs with various EOT.

EOT (nm) 0.2 0.4 0.6 0.8 1.0 1.2 25 30 35 40 45 50 55 60 65 16nm Bulk FinFET with EOT=1.2nm

16nm Planar MOSFET with various EOT 30.71 31 Vt,total (mV) σ

Fig. 12. Total threshold voltage fluctuation for the studied devices.

Table 2

Components of the threshold voltage fluctuation of the explored planar MOSFETs and bulk FinFETs

Planar MOSFET Bulk FinFET

EOT (nm) 1.2 0.8 0.4 0.2 1.2

Lg/LER 18.1 16.7 12.2 8.18 12.6

RD 58.5 46.6 37.9 29.9 28.3

immunity of the planar MOSFET against random-dopant-induced fluctuation suffers from nature of structural limitations. The bulk FinFETs with 1.2 nm EOT shows a similar immunity against fluctu-ation with the planar MOSFETs with 0.2 nm EOT. Multiple-gate FETs, such as the examined bulk FinFET may alleviate the chal-lenges of device’s scaling and could be a potential candidate in the era of nanoelectronics. We notice that for the bulk FinFETs be-sides the gate-length deviation and line-edge roughness, the ef-fects of Si thickness variation, Si sidewall roughness, and local field enhancement at the top or bottom Si fin are the important sources of fluctuation, which are currently under consideration.

Acknowledgements

This work was supported by Taiwan National Science Council (NSC) under Contract 96-2221-E-009-210 and Contract NSC-96-2752-E-009- 003-PAE, and by the Taiwan Semiconductor Man-ufacturing Company, Hsinchu, Taiwan under a 2006-2008 grant. References

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