364 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 5, MAY 2007
On the RF Extrinsic Resistance Extraction
for Partially-Depleted SOI MOSFETs
Sheng-Chun Wang, Pin Su, Member, IEEE, Kun-Ming Chen, Chien-Ting Lin, Victor Liang, and
Guo-Wei Huang, Member, IEEE
Abstract—We have investigated the radio frequency (RF)
extrinsic resistance extraction for partially-depleted (PD) sil-icon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency depen-dence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs.
Index Terms—Metal-oxide-semiconductor field effect
transis-tors (MOSFETs), radio frequency (RF), resistance extraction, silicon-on-insulator (SOI) technology.
I. INTRODUCTION
D
UE to its highly integrated nature, CMOS technology has become an excellent choice for radio frequency (RF) applications. Silicon-on-insulator (SOI) CMOS is especially promising for RF system-on-chip integration because of the reduction in crosstalk between RF and digital circuits and easy integration of high quality passive elements [1], [2]. With the penetration of SOI CMOS into RF applications [3], [4], RF SOI modeling becomes a crucial design issue.For RF CMOS modeling, the model accuracy hinges upon the extraction of extrinsic gate/source/drain resistance for small-signal, noise, and large-signal ap-plications. Several studies [5]–[7] have presented resistance extraction methods for SOI metal-oxide-semiconductor field effect transistors (MOSFETs) based on those developed for their bulk counterparts [8], [9]. Among these approaches, the zero method [5], [8] developed under the zero condition (i.e., 0) is attractive because it simplifies the corre-sponding equivalent circuit and avoids the error caused by the
Manuscript received August 21, 2006; revised January 3, 2007. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contract NSC94-2215-E-009-049.
S.-C. Wang is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
P. Su is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
K.-M. Chen and G.-W. Huang are with the National Nano Device Laborato-ries, Hsinchu 300, Taiwan, R.O.C.
C.-T. Lin and V. Liang are with the United Microelectronics Corporation, Hsinchu 300, Taiwan, R.O.C.
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2007.895713
Fig. 1. I versus V characteristics for PD SOI MOSFETs used in this study. V is from 0.4 to 0.8 V with step 0.2 V.
non-quasi-static (NQS) effect [7]. Based on the equivalent cir-cuit built for bulk MOSFETs under the zero condition without considering the substrate loss [8], the following frequency-in-dependent resistance expressions have been derived to directly determine and , respectively
(1) (2) (3) For partially-depleted (PD) SOI MOSFETs, however, (1)–(3) may not be valid due to the existence of the floating body re-gion. In this work, we investigate the RF extrinsic resistance extraction for PD SOI MOSFETs. We will show that, for RF SOI MOSFETs, the coupling path between the source and drain terminals through the quasi-neutral body region makes the resis-tance expressions behave frequency-dependently. After taking this effect into account, we develop a physical RF extrinsic re-sistance extraction methodology for PD SOI MOSFETs.
II. DEVICES ANDMEASUREMENTS
The PD SOI MOSFETs used in this study were fabricated using UMC 0.13- m SOI technology. The thicknesses for gate oxide, SOI layer, and buried oxide are 1.4, 40, and 200 nm, re-spectively. The presence of kinks in Fig. 1 shows that the devices under study are partially depleted. These RF devices were laid out in the multi-finger and multi-group structure with various finger number NF, group number NG, and finger length for a given gate length (0.12 m). On-wafer two-port param-eters up to 20 GHz were measured, de-embedded with an open dummy, and then transformed to parameters to obtain the re-sistance versus frequency characteristics.
WANG et al.: RF EXTRINSIC RESISTANCE EXTRACTION 365
Fig. 2. Resistance curves for the bulk and PD SOI MOSFETs with L =W =NF=NG = 0.12 m/2.4 m/16/3.
Fig. 3. (a) Cross-sectional view of the zero PD SOI MOSFET. (b) Equivalent circuit for zero PD SOI MOSFETs.
To further minimize possible substrate resistive loss through the buried oxide layer [10], a bias-network connected to the chuck of the probe station was used to provide the substrate dc ground (i.e., back-gate voltage 0) with RF floating. In fact, as shown in Fig. 2, whether the substrate RF ground is pro-vided or not, the resistance curves are almost unchanged. This indicates that the substrate effect is negligible in this experiment.
III. RESULTS ANDDISCUSSIONS
Fig. 2 also compares the resistance versus frequency charac-teristics under the zero condition for PD SOI MOSFET and its bulk counterpart with identical layout structure and geometry. All of these curves more or less are frequency-dependent. The poor shapes for the bulk MOSFET can be attributed to the com-plicated and significant substrate resistive loss [11], [12]. For the SOI MOSFET, however, the substrate loss may not be respon-sible for this frequency-dependent behavior because the thick buried oxide layer in the SOI transistor has provided good iso-lation from the substrate.
Fig. 3(a) shows a cross-sectional view of the PD SOI MOSFET under the zero condition. The neutral-body coupling path is constituted by source- and drain-side junction capac-itances ( and ), and body conductances ( and
Fig. 4. Modeling results for extrinsic resistance extraction considering the neu-tral-body effect (points: measured data. lines: model).
Fig. 5. Correlation betweenRe(Z 0 Z ); Re(Z ) and Re(Z 0 Z ) (Points: measured data. lines: model).
). Its corresponding equivalent circuit without substrate RF ground is depicted in Fig. 3(b). Here, the neutral-body coupling path is represented by a lumped junction capacitance
1 1 and a lumped body conductance
1 1 ). Based on this equivalent circuit, the following resistance expressions regarding , and can be derived: (4) (5) (6) where and
Note that we have assumed in the deriva-tion. Equations (4)–(6) predict that the existence of neutral body may cause the resistance curves regarding , and frequency-dependent and explain the anomalous SOI be-havior in Fig. 2. It is worth noting that (4)–(6) will approach (1)–(3), respectively, as the frequency (or angular frequency,
366 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 5, MAY 2007
TABLE I MODELPARAMETERS
) approaches infinity. In other words, the extrinsic resis-tances can be determined by the high frequency asymptotes
of , and . Note that
the drain-source coupling capacitance, , will short the neutral-body path and hence eliminate this neutral-body effect at very high frequency.
Using this new model, a physical RF extrinsic resistance ex-traction methodology for PD SOI MOSFETs can be developed. The model-data comparison for the extraction of , and with various layout geometries are shown in Fig. 4. It can be seen that the frequency-dependent resistance characteristics are well fitted by our model. Moreover, according to (4)–(6), , and are mutually cor-related [6] by
(7) (8) (9)
where 0.5
0.5 . Equations (7)–(9) have been verified in Fig. 5. The extracted extrinsic resistances and model parameters
, and for each SOI device are listed in Table I. One can find that is nearly equal to zero whereas is not. This is because the RF devices were laid out in the multi-finger and multi-group structure. The multi-source regions were out-connected at two ends of each finger, while the multi-drain regions were out-connected at only one side. In addition, the interconnection between each group may pro-vide additional resistance for the drain terminal and result in discrepancy between and .
Since all the involved device conductance and capacitances in (4)–(6) are proportional to the total gate width
NF NG , the parameter should increase as decreases. As indicated in Fig. 4, the resistance curves for the device with smaller indeed have a larger deviation from its high-fre-quency asymptote in the lower frehigh-fre-quency regime. Therefore, one can minimize the extraction error resulted from the SOI neu-tral-body effect by using the wide device.
IV. CONCLUSION
We have investigated the extrinsic resistance extraction for PD SOI MOSFETs. Although the thick buried oxide in SOI devices can block the complicated substrate network, the SOI neutral-body coupling effect may become significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on the equivalent circuit, a new model
capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs.
ACKNOWLEDGMENT
The authors would like to thank the staff at UMC for pro-viding the SOI devices used in this study.
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