memory
Yu-Hsien Lin, Hsin-Chiang You, and Chao-Hsin Chien
Citation: Journal of Vacuum Science & Technology B 30, 011201 (2012); doi: 10.1116/1.3668101
View online: http://dx.doi.org/10.1116/1.3668101
View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/30/1?ver=pdfcov
Published by the AVS: Science & Technology of Materials, Interfaces, and Processing
Articles you may be interested in
Silicon-oxide-high- -oxide-silicon memory using a high- Y 2 O 3 nanocrystal film for flash memory application
J. Vac. Sci. Technol. A 27, 700 (2009); 10.1116/1.3151816
Suppression of parasitic electron injection in silicon-oxide-nitride-oxide-silicon-type memory cells using high- k capping layers
J. Vac. Sci. Technol. B 27, 482 (2009); 10.1116/1.3021020
Metal-oxide-high- k -oxide-silicon memory structure using an Yb 2 O 3 charge trapping layer
Appl. Phys. Lett. 93, 183510 (2008); 10.1063/1.3021360
Comparison of structural and electrical properties of praseodymium oxide and praseodymium titanium oxide charge trapping layer memories
J. Appl. Phys. 102, 074111 (2007); 10.1063/1.2786102
Annealing temperature effect on the performance of nonvolatile HfO 2 Si-oxide-nitride-oxide-silicon-type flash memory
This study proposes and demonstrates a silicon-oxide-nitride-oxide-silicon (SONOS)-type memory device based on a high-k dielectric praseodymium oxide (Pr2O3) trapping layer. In the proposed
design, channel hot electron injection programming and band-to-band hot-hole injection erasing allow highly efficient two-bit and four-level device operation. The proposed design also has a total memory window of 5 V, a ten-year Vtretention window larger than 0.8 V between adjacent levels,
and enough memory window for 105 programming/erasing cycles of endurance. The proposed SONOS-type Pr2O3trapping layer flash memory exhibits large memory windows, high program/
erase speed, good endurance, and good disturbance characteristics. VC 2012 American Vacuum
Society. [DOI: 10.1116/1.3668101]
I. INTRODUCTION
Conventional floating gate (FG) memory devices encoun-ter problems with scaling down because they use a thick tunneling oxide to guarantee a long charge retention time for continuous charge storage.1 Upon scaling the tunneling oxide thickness down, the FG easily loses charge due to defect generation caused by program/erase cycles or direct current tunneling.2According to the International Technol-ogy Roadmap for Semiconductors (ITRS), there are critical limitations for aggressively scaling down conventional non-volatile floating gate memories below the 50 nm node.3 A silicon-oxide-nitride-oxide-silicon (SONOS) structure for charging devices has recently become attractive because it does not have a planar scaling problem for floating gate iso-lation and shows great potential for achieving high program/ erase speed, low programming voltage, and low power per-formance.4 However, issues such as erase saturation and vertical stored charge migration remain a problem for SONOS memory.5,6 Many recent studies present different types of high-k trapping layers as potential candidates for replacing Si3N4 to provide charge storage in nonvolatile
memory.6–10 Based on discrete storage nodes, SONOS-type flash memory has great potential to achieve high program/ erase speed, low programming voltage, low power perform-ance, a large memory window, excellent retention, and good endurance.
Rare earth oxides such as Pr2O3are attractive candidates
for trapping layers in memory devices due to their thermody-namic stability, high dielectric constant, proper conduction, valence band offset with silicon, low lattice mismatch with
silicon, and excellent electrical properties.11–14 High trapping state densities can improve the charge-trapping efficiency and, ultimately, achieve a larger operation win-dow. This makes it possible to further reduce the operation voltage and potentially improve memory device scaling.
The experiment in this study fabricated a high perform-ance nonvolatile memory with a high-k material praseodym-ium oxide (Pr2O3) charge-trapping layer. The proposed
design has good characteristics in terms of a considerably large memory window, high speed program/erase, good endurance, and good disturbance for two-bit and four-level device operation.
II. EXPERIMENT
Figure 1 schematically depicts the device structure and process flow of the proposed flash memory. The fabrication process of the praseodymium oxide memory devices began with a local oxidation of silicon (LOCOS)15 isolation process on p-type, 5 – 10 X cm, (100) 150 mm silicon substrates. First, a 3-nm-thick tunnel oxide was thermally grown at 1000C in a vertical furnace system. A praseodym-ium oxide layer was then deposited by the E-gun method16 with praseodymium oxide targets. The samples then went through rapid thermal annealing (RTA) treatment in N2O
ambient at 900 C for 1 min. A blocking oxide approxi-mately 10-nm-thick was then deposited by high-density plasma chemical vapor deposition (HDPCVD)17followed by a 1 min, 900 C N2 densification process. A 200-nm-thick
poly-Si layer was then deposited by low pressure chemical vapor deposition (LPCVD)18to serve as the gate electrode. The gate electrode was patterned and the source/drain (S/D) and gate were doped with self-aligned phosphorous ion implantation at a dosage and energy of 5 1015ions/cm2 and 20 KeV, respectively. The substrate contact was
a)Author to whom correspondence should be addressed; present address:
National United University, Department of Electronic Engineering, No. 1, Lienda, Miaoli, Taiwan, 36003; electronic mail: [email protected]
patterned and the sub-contact was implanted with BF2at a
dosage and energy of 5 1015 ions/cm2 and 40 KeV, respectively. After these implantations, the dopants were activated at 950C for 20 s. Standard complementary metal oxide semiconductor (CMOS) procedures were subsequently completed to fabricate praseodymium oxide high-k memory devices.
III. RESULTS AND DISCUSSION
The proposed Pr2O3trapping layer flash memory employs
channel hot-electron injection and band-to-band hot-hole injection for programming and erasing, respectively.19 All devices described in this paper had dimensions of L/W¼ 2/2 lm. Figure 2 shows the program characteristics as a function of pulse width for different operation conditions. Both source and substrate terminals were biased at 0 V. The “Vtshift” is defined as the threshold voltage change of a
de-vice between the programmed and the erased states. With Vd¼ Vg¼ 10 V, relatively high speed (10 ls) programming
performance can be achieved with a memory window of approximately 2.5 V. Figure3plots the erase characteristics as a function of various operation voltages. The devices were programmed with a 3 V memory window and erased. Excellent erase speeds of various Vg(from5 to 7 V) and
Vd¼ 9 V were obtained. More importantly, there was no
significant over-erase issue. This is because band-to-band hot hole erasing decreases the vertical electric field by
decreasing trapped electrons in the trapping layer, and signif-icantly reduces the hole injection into the trapping layer. Based on the discrete charge storage of the Pr2O3trapping
layer, the proper bias scheme can feasibly achieve 2-bit operation.20Forward and reverse reads can detect the infor-mation stored in the programmed Bit 1 and Bit 2, respec-tively. This means that it is possible to program Bit 1 and read the information using a reverse read scheme.21
Figure 4 shows the four-level threshold voltage (Vth)
distribution of multilevel programming wherein a sharp Vth
distribution can achieve reliable operation. The Vth
distribu-tion reveals that the proposed Pr2O3 trapping layer is
uni-form. The Vthdistribution between adjacent bits still has a
memory window larger than 1 V to detect the information. This demonstrates the feasibility of performing four-level operation with the proposed Pr2O3 trapping layer memory
through a reverse read scheme in a single cell. Moreover, the Vthdistribution range becomes fatter and less sharp. This is
due to increased programming voltage, longer time, and broader channel hot electron distribution range. Thus, 4-level operation adopts a low voltage for sharp Vth
distribu-tion, but requires a memory window larger than 0.8 V to detect the information. Figure5illustrates the retention char-acteristics for four-level operation at room temperature. These results show that the retention time of the memory with a Pr2O3trapping layer can be up to 104s for 15% and
FIG. 1. (Color online) Pr2O3flash memory cross-section cell structure and
process flow of the proposed flash memory cell.
FIG. 2. (Color online) Program characteristics of the memory devices with
different programming conditions.
FIG. 3. (Color online) Erase characteristics of the memory devices with
dif-ferent erasing voltages.
FIG. 4. Four-level threshold voltage (Vth) distribution of multilevel
pro-gramming: The Vthdistribution between adjacent bits still has a memory
window larger than 0.8 V to detect the information.
108s for 35% charge loss at room temperature. The memory window for level-to-level still has a memory window larger than 0.8 V and can detect information for up to 108s.
Figure 6 shows the endurance characteristics for four-level operation after 104P/E cycles. Slight memory window narrowing is apparent, and the individual threshold voltage shifts in the program and erase states become visible after 103cycles.
This indicates the formation of operation-induced trapped electrons22in the tunneling oxide or a mismatch between the localized spatial distributions for injected electron and holes using channel hot-electron programming and band-to-band hot-hole erasing. The uncompensated electron resulting from residual charges in the Pr2O3 trapping layer subsequently
causes the Vt to increase gradually over the P/E cycling.
Even the four-level operation has a sufficient memory win-dow (>0.8 V) to detect information up to 104P/E cycles.
Figure7shows the programming drain disturbance of the proposed Pr2O3flash memory. Three different drain voltages
(Vd¼ 5, 7, and 9 V) were applied to the programming drain
disturbance measurements at room temperature. Results show that a sufficient programming drain disturbance margin exists (DVt< 0.5 V) after programming at a value for Vd
of 9 V at room temperature. Figure 8 shows the gate
disturbance characteristics in the erasing state. For cells sharing a common word-line, gate disturbance may occur when one of the cells is being programmed. A threshold voltage shift of 0.2 V occurred under the following condi-tions: Vg¼ 10 V, Vs¼ Vd¼ Vsub¼ 0 V, and stress for 1000 s.
Because of the small voltage drop at the tunnel oxide due to thicker block oxide, the proposed memory exhibits good gate disturbance characteristics with a tunnel oxide 3 nm thick. Figure9demonstrates the erase-state threshold voltage instability induced by read disturbance in a localized Pr2O3
trapping storage flash memory cell under different operation conditions. The read-disturb effect is the result of two fac-tors: the word-line and the bit-line. The word-line voltage during reading may increase room temperature (RT) drift in the neighboring bit and a relatively large read bit-line volt-age may cause unwanted channel hot-electron injection. This subsequently results in a significant threshold voltage shift in the neighboring bit. The measurements in this study applied gate and drain biases and placed the source at ground. Results demonstrate that almost no read disturbance occurred in the proposed Pr2O3 flash memory under
low-voltage reading (Vg¼ 4 V; Vd¼ 2 V). Even for a larger
memory window, there is almost no read disturbance (ca. 0.1 V) after operation at Vd¼ 4 V after 1000 s at 25C.
FIG. 5. (Color online) Four-level retention characteristics of Pr2O3memory
devices at T¼ 25C: The level-to-level memory window still has a memory
window larger than 0.8 V up to 108s.
FIG. 6. (Color online) Four-level endurance characteristics of the Pr2O3
memory devices: A sufficient memory window (>0.8 V) can obtained and we can detect the information up to 104P/E cycles.
FIG. 7. (Color online) Drain disturbance characteristics of the Pr2O3
mem-ory cells: A sufficient programming drain disturbance margin exists (DVt< 0.5 V) after programming at a value of Vd of 9 V at room
temperature.
FIG. 8. (Color online) Gate disturbance characteristics of Pr2O3 memory
devices: A threshold voltage shift of 0.2 V occurred after stressing at Vg¼ 10 V and Vs¼ Vd¼ Vsub¼ 0 V for 1000 s.
IV. CONCLUSION
This study investigates the effect of memory on the per-formance of a Pr2O3SONOS-type flash memory device. The
proposed design has good characteristics in terms of large memory windows, high speed program/erase, excellent en-durance, and good retention for two-bit/four level operation. Hence, Pr2O3 may be a candidate material for the trapping
layers of a SONOS-type memory device.
ACKNOWLEDGMENT
This project was sponsored by the National Science Council, Taiwan, under Grant No. 100-2218-E-239-002-.
1
J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong,IEEE Trans. Electron Devices50, 2067 (2003).
2R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti,Proc. IEEE, 91, 489
(2003).
3The International Technology Roadmap for Semiconductors
(Semiconduc-tor Industry Association, San Jose, CA, 2001), p. 27, seehttp://www.itrs. net/reports.html.
4R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi,IEEE Trans.
Electron Devices49, 1392 (2002).
5
P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. J. King,Tech. Dig.-Int. Electron Devices Meet.609, 609 (2003).
6T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y.
Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka,Tech. Dig. VLSI Symp.27, 27 (2003).
7
G. D. Wilk, R. M. Wallace, and J. M. Anthony,J. Appl. Phys.89, 5243 (2001).
8M. S. Joo, B. J. Cho, C. C. Yeo, D. S. H. Chan, S. J. Whoang, S. Matthew,
L. K. Bera, N. Bala, and D. L. Kwong,IEEE Trans. Electron Devices50, 2088 (2003).
9Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi,IEEE Trans. Electron
Devices51, 1143 (2004).
10
Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei,IEEE Electron Device Lett.26, 154 (2005).
11A. Sakai, S. Sakashita, M. Sakashita, Y. Yasuda, S. Zaima, and S.
Miyazaki,Appl. Phys. Lett.85, 5322 (2004).
12
A. Fissel, J. Dabrowski, and H. J. Osten,J. Appl. Phys.91, 8986 (2002).
13
G. Lupina, T. Schroeder, J. Dabrowski, C. Wenger, A. U. Mane, H. J. Mus-sig, P. Hoffmann, and D. Schmeisser,J. Appl. Phys.99, 114109 (2006).
14T. M. Pan, F. J. Tsai, C. I. Hsieh, and T. W. Wu,Electrochem Solid-State
Lett.10, G21 (2007).
15
P. V. Zant,Microchip Fabrication, 5th ed. (McGraw-Hill, New York, 2004), p. 398.
16
P. V. Zant,Microchip Fabrication, 5th ed. (McGraw-Hill, New York, 2004), p. 418.
17
P. V. Zant,Microchip Fabrication, 5th ed. (McGraw-Hill, New York, 2004), p. 381.
18P. V. Zant,Microchip Fabrication, 5th ed. (McGraw-Hill, New York,
2004), p. 377.
19
E. Lusky, Y. S. Diamand, I. Bloom, and B. Eitan,IEEE Electron Device Lett.22, 556 (2001).
20B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi,IEEE
Electron Device Lett.21, 543 (2000).
21
Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei,IEEE Trans. Electron Devices53, 782 (2006).
22T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao,IEEE Electron Device
Lett.25, 205 (2002). FIG. 9. (Color online) Read disturbance characteristics of the Pr2O3 flash
memory: A slight Vtshift occurred for Vd< 4 V, after 1000 s at 25C.
