tics that had lower leakage currents but much higher breakdown field, a lower electron trapping rate, and a much larger charge to breakdown. These good properties are attributed to the smoother surface of the deposited disilane poly-I film and the more incor-poration of nitrogen during the rapid thermal annealing (RTA) in N2O ambient. It is suitable to be as the inter-polyoxide of the elec-trically-erasable programmable read only memory (EEPROM).
I. INTRODUCTION
N ORDER to have good data retention characteristics for the deep submicron electrically-erasable programmable read only memory (EEPROM), a thin polyoxide with a low leakage cur-rent, a high breakdown field ( ), a large charge to breakdown ( ) and a low electron trapping rate is required [1]–[4]. Re-cently, TEOS vapor deposited polyoxide with rapid-thermal-an-nealing (RTA) in N O has been reported to have a higher re-liability due to its smoother interface after oxidation [5], [6]. The quality of the TEOS (tetra-ethy1-ortho-silicate) polyoxide is strongly related to the surface roughness and the doping con-centration of polyI. Unfortunately, for the conventional polysil-icon film, the surface roughness increases as the doping concen-tration of polyI decreases [7], reducing the advantage obtained by the TEOS polyoxide.
Disilane polysilicon film was widely used in fabrication of the low-temperature thin-film transistor (TFT) for its lower deposition temperature and larger grain [8], [9]. It was also used as HSG (hemispherical grain) poly-Si films in dynamically random accessible memories (DRAM’s) for its wide transition temperature [10]. It has a much smoother surface in the low doping concentration regime. However, little study was done on growing oxides on it, especially, on depositing TEOS oxide on it. This paper reports, for the first time, the results on inves-tigation on low pressure chemical vapor deposition (LPCVD) TEOS oxide deposited on the disilane polysilicon followed with RTA in N O. It is found that the fabricated polyoxide
Manuscript received August 30, 2000; revised October 13, 2000. This work was supported by the National Science Council, R.O.C., through Contract NSC 88-2215-E-009-054. The review of this paper was arranged by Editor C.-Y. Lu. J. W. Lee, C.-L. Lee, and T. F. Lei are with the Department of Electronic Engi-neering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
C. S. Lai is with the Department of Electronic Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. and also with the Department of Electronic Engineering, Chang Gung University, Tao-Yuan, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9383(01)02354-1.
has a very high , a low electron trapping rate, and a high . The polyoxide, when used in EEPROM applications, can improve performance and reliability of the EEPROM device.
II. EXPERIMENTS
In this study, n -polysilicon/polyoxide/n -polysilicon ca-pacitors were fabricated and used in the measurement. At first, p-type wafers were thermally oxidized in dry O at 950 C to have a 100 Å oxide. Then a 200 nm disilane polysilicon film (poly-I) was deposited at 460 C. The poly-I film was then phosphorous-implanted at an energy of 30 keV of a dose of cm . After rapid-thermal (RT) annealed at 950 C for 30 s in an N ambient to obtain a sheet resistance of 70 /cm for poly-I, the wafers were then deposited with a TEOS oxide of a thickness of 130 Å at 700 C. The oxide was then RT annealed in an N O ambient at 950 C for 30 s. For comparison, the same oxide but RT annealed in O or N ambient at 950 C for 30 s were also prepared. A second silane polysilicon (poly-II) of a thickness of 300 nm was then deposited again. The poly-II was doped by POCl and driven-in at 850 C for 1 h in an N ambient to obtain a sheet resistance of 40 /cm . It was then patterned and grown a 100 nm passivation oxide. After contact hole opening, Al film was deposited, patterned, and sintered at 350 C for 40 min in an N ambient to be gates and contacts of the capacitors. In the above, also for comparison, similar capacitors but with their poly-I grown with silane at 620 C, of a sheet resistance of 140 /cm , were prepared. Also, for comparison, similar capacitors but their oxides grown in O and N O at 850 C by the conventional thermal oxidation method were prepared. The process steps for each sample are compiled in Table I.
The thickness (equivalent oxide thickness ) of the oxide was measured by CV measurement and verified by TEM, and and were measured by an HP4145b semiconductor analyzer.
(a) (b)
(c) (d)
(e) (f)
Fig. 1. AFM images of polyI surface of (a) D-TH-O ; (b) D-TH-N O; (c) D-T-RT-N O; and (d) S-T-RT-N O, (e) D-T, and (f) D-T-RT-O samples with their poly-II and polyoxide removed. The surface roughness is 44 Å, 31 Å, 3 Å, 49 Å, 12 Å, and 34 Å, respectively.
III. RESULTS ANDDISCUSSION
Fig. 1 shows the atomic force microscope (AFM) images of the poly-I surfaces of the following samples: (a) D-TH-O : the O thermal oxide grown on the disilane poly-I; (b) D-TH-N O: the N O thermal oxide grown on the disilane poly-I; (c) D-T-RT-N O: the TEOS oxide deposited on the disilane poly-I with RTN O annealing; (d) S-T-RT-N O: the TEOS oxide deposited on the silane poly-I with RTN O annealing; (e) D-T: the TEOS oxide deposited on the disilane poly-I; and (f) D-T-RT-O : the TEOS oxide deposited on the disilane poly-I
with RTO annealing, respectively. In the above, all images are the surface images of poly-Is of the capacitors with their poly-II’s and polyoxides removed. The roughness obtained from the AFM measurement for each sample are D-TH-O : 44 Å, D-TH-N O: 31 Å, D-T-RT-N O: 3 Å, S-T-RT-N O: 49 Å, D-T: 12 Å, and D-T-RT-O : 34 Å, respectively. From these pictures and data, it can be found that
1) the TEOS with the RTN O sample had the smoothest sur-face;
2) the disilane samples had smoother surface than that of the silane samples;
poly-I/oxide interface roughness.
In addition, for disilane samples, the thermally grown polyoxide had a rougher interface than that of the TEOS oxide. This in-dicates that thermal oxidation enhanced interface roughness. Also, the oxides grown or annealed in the N O ambient had a smoother interface than those treated in the O ambient. This was probably caused by the fact that N O oxidation or annealing provided nitrogen which passivated grain boundaries of the de-posited poly-I layer and reduced the grain boundary enhance-ment effect [1].
Fig. 2 shows the cross section TEM images of the D-T-RT-N O and S-T-RT-N O samples. These pictures show that the D-T-RT-N O sample had a smoother interface than that of the S-T-RT-N O sample. Two samples had a similar grain size on the poly-I film. However, it is noticed that, for the D-T-RT-N O sample, both its poysilicon-II/oxide/polysilicon-I interfaces had similar smoothness. In addition, from the TEM picture of the D-T-RT-N O sample, the oxide thickness can be estimated to be 150 Å, which is the same as the value derived from the characteristic of the sample. The dielectric constant of the polyoxide was 3.9.
Fig. 3 shows the (a) positive and (b) negative – char-acteristics of the six samples. The D-T-RT-N O sample, i.e., the TEOS oxide deposited on the disilane polysilicon film with RTN O annealing, had the lowest leakage current and the highest breakdown field. This could be attributed to the much smoother poly-I of this sample. In the figure, the D-T sample, i.e., the D-T-RT-N O sample without the RT N O annealing, had a poorer characteristics than that of the D-T-RT-N O sample, although it had a relatively smooth poly-I/oxide interface. Hence, the RT annealing in N O is an important step in improving the quality of the oxide. It annealed the deposited oxide, created an additional 20 Å thermal oxide at the poly-I/oxide interface, and introduced nitrogen into the oxide. The latter will be addressed further next by the support of SIMS data. In addition, it is seen that besides the D-T-RT-N O sample, all other samples had asymmetrical – characteristics. That the D-T-RT-N O sample had the sym-metrical – characteristics is believed due to the fact that it had a symmetrical smoothness on its both polysilicon-II/oxide and oxide/polysilicon-I interfaces, as revealed by the previous TEM pictures.
Comparing the – characteristics of the D-T sample with those of the thermally grown polyoxides grown on either the disilane poly-I, i.e., D-TH-O and D-TH-N O, or on the silane
Fig. 3. J–E characteristics of the D-TH-O , D-TH-N O, S-TH-N O, D-T-RT-N O, S-T-RT-N O, and D-T six samples with (a) poly-II positive biased and (b) poly-II negative biased.
poly-I, i.e., D-TH-N O and S-TH-N O, we find that the D-T sample, even though it had relatively smooth poly-II/oxide and oxide/poly-II interfaces, had a higher leakage current at the low
Fig. 4. J–E characteristics of the D-T-RT-N O, D-T, D-T-N , and D-T-RT-O four samples with (a) poly-II positive biased and (b) poly-II negative biased.
electric field regime. It is because, the TEOS oxide, deposited at a low temperature (700 C), had a porous structure before RT annealing. This led a high trap density existing in the oxide, pro-viding conduction paths for injected electrons under the applied field.
Fig. 4 shows the (a) positive – characteristics and (b) the negative – characteristics of the TEOS oxide deposited on the disilane films with rapid thermal annealing at 950 C 30 s in N , O , and N O ambients, respectively. We can see that the RTN O annealed sample had the lowest leakage current. This can be simply explained by the fact that it had a rela-tively smoother interface than those of other samples. The RTN sample did not have any improvement as compared with the as-deposited TEOS sample. In addition, we see that the RTO improved the – characteristics of the TEOS oxide only in the positive bias. The improvement could be due
Fig. 5. Electron trapping characteristics of the D-TH-O , D-TH-N O, D-T-RT-N O, S-T-RT-N O, D-T-RT-O , and D-T six samples with (a) poly-II positive biased and (b) poly-II negative biased.
to the additional thermal oxide grown during the annealing process. However, this process also enhanced the roughness of the polyoxide/polysilicon-I interface, consequently, that of the polysilicon-II/polyoxide interface. This might be the reason that the RTO sample had the worse – characteristic than that of the as-deposited TEOS sample in the negative bias. Hence, in one word, owing to the smoothest interface and an additional oxide grown during annealing, the TEOS oxide deposited on the disilane polysilicon film with RTN O annealing is the best way to fabricate low leakage current polyoxides in our experiment.
Fig. 5 shows electron trapping characteristics of both polar-ities for the six samples under the 1 mA/cm constant current stress. The electron trapping characteristics under stress are
Fig. 6. Weibull plots ofQ of the D-TH-O , D-TH-N O, D-T-RT-N O, S-T-RT-N O, D-T-RT-O , and D-T six samples with (a) poly-II positive biased and (b) poly-II negative biased where the oxide thickness of the D-TH-O , D-TH-N O, and D-T is 130 Å and 150 Å of D-T-RT-N O, D-T-RT-O , and S-T-RT-N O, respectively.
determined by a combination of factors such as the injecting surface roughness, the intrinsic quality of the oxide, and the nitrogen incorporation at the interface. In general, a rougher in-jecting surface leads to a nonuniform electric field distribution, consequently, nonuniform injected electron distribution both at the injection interface and in the bulk of the polyoxide, leading to a higher trapping rate. In the figure, for the positive stress, where the poly-I was the injecting surface, the S-T-RT-N O sample had the highest trapping rate, reflecting its interface roughness. While the D-T-RT-N O sample had the lowest trapping rate, which is consistent with the fact that it had the smoothest interface. In addition, for the D-T-RT-N O sample,
Fig. 7. SIMS profiles of Nitrogen count of the D-TH-O , D-TH-N O, S-T-RT-N O, D-T-RT-N O, and S-T-RT-N O samples, respectively.
it had asymmetric trapping characteristics, and for the positive polarity stress, it had a net hole trapping characteristic at the beginning stage of the stress. This might be due to the more nitrogen incorporation within the oxide since similar phe-nomenon were observed for the reported nitrogen-rich oxides prepared by N O or NO oxidation [11], [12]. Comparing the positive stress electron trapping characteristics of the variously prepared oxide samples on the disilane poly-I, the N O treated samples had smaller electron trapping rates than those of samples without the N O treatment. This indicates that N incorporation suppresses electron trapping [1]. For the negative stress electron trapping characteristics, however, since they are less relevant to the interface roughness of the polyoxide/poly-I, the N incorporation and the oxide intrinsic quality are the dominant factors in determining the characteristics. In the figure, it is still seen that the D-T-RT-N O sample had the smallest electron trapping rate, which reflected fact that it had the smoothest polysilicon-II/oxide injecting interface and the best oxide quality.
Fig. 6 shows Weibull plots of of our experimental samples in both polarities, respectively. Also, it is seen that the D-T-RT-N O sample had the best distributions for both polarities. Also, the D-T-RT-O sample had the next better distributions and the D-T was the third one. That is, for the distribution consideration, the TEOS deposited on disilane film is a superior process then the thermal or the silane poly-I processes. Furthermore, among all the distributions, the D-T-RT-N O sample had the most symmetrical distributions. This is also believed to be due to the fact that the D-T-RT-N O had symmetrically smooth surfaces at both poly-I and poly-II interfaces. In addition, the N incorporation might also con-tribute to the result.
Fig. 7 shows the SIMS nitrogen profiles of D-T-RT-N O, S-T-RT-N O, D-TH-O , D-TH-N O, and S-TH-N O samples, respectively. The profiles show that the D-T-RT-N O samples had the highest nitrogen distribution among all the samples.
Fig. 8. XRD profiles of (a) disilane and (b) silane samples.
It is believed that it was this higher concentration of nitrogen incorporating reduces the dangling or strained bonds, conse-quently traps, in oxides. With fewer trappings, also the stronger nitrogen silicon bonds, the oxide had a lower leakage, a lower electron trapping rate, higher and . In the figure, it is seen that the RT-N O samples had higher nitrogen contents than those of the thermal N O samples. Also, the disilane sam-ples with the N O treatment had higher nitrogen content than those of the silane samples. That is, the nitrogen content in the D-T-RT-N O and the D-TH-N O samples were higher than that of the S-T-RT-N O sample. Fig. 8 shows the XRD (X-ray diffraction) patterns for (a) disilane polysilicon film and (b) silane polysilicon film, respectively. The patterns show that the disilane film had a strong peak at orientation but weak at orientations while the silane film had the strong orientations but relatively weak orientation. This means that the nitrogen incorporation was heavily dependent on the microstructure of poly-I film. This microstructure variations for polysilicons prepared by different methods had been discussed in [13] and a surface energy dependence model, that is, the
tron trapping rate characteristics and also the largest distri-bution.
IV. CONCLUSION
In this work, the TEOS oxide deposited on the disilane polysilicon and then RT annealed in N O had been investigated along with other oxides such as those deposited on the silane polysilicon or directly thermally oxidized on polysilicon films. It was found that, due to the smoother surface of the disilane poly-I polysilicon and the higher nitrogen incorporation during the RT N O annealing process, the TEOS oxide had symmet-rical positive and negative – characteristics, a much lower electron trapping rate, and a high than all other oxides. The oxide is very suitable for the application as the inter-polyoxide for EEPROM.
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Chung-Len Lee (S’70–M’75–M’81–SM’92) received the B.S. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1968, and the M.S. and Ph.D. degrees from Carnegie Mellon University, Pittsburgh, PA, in 1971 and 1975, respectively, all in electrical engineering.
Since 1975, he has been with the Department of Electronic Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he has been engaged in teaching and research in the fields of semiconductor devices, integrated circuits, VLSI, and computer-aided design and testing. He has supervised more than 100 M.S. and Ph.D. students to complete their theses and has published more than 200 papers in the above areas. He has been involved in various technical activities in the above areas in Taiwan and other parts of Asia.
Dr. Lee is on the Editorial Board of JETTA.
partment of Electronics Engineering. His research interests are semiconductor devices and VLSI technologies.
Chao-Sung Lai was born in I-Lan, Taiwan, R.O.C.,
on May 20, 1969. He received the B.S. and Ph.D. de-grees from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1996, respectively.
In 1996, he joined the National Nano Device Lab-oratory, Hsinchu, where he was engaged in the re-search of SOl devices. In 1997, he joined the Chang Gung University, Tao-Yuan, Taiwan, as an Assistant Professor, where he has been engaged in the research of the characterization and reliability of deep-submi-cron MOSFET’s, nitrated thin gate oxides, shallow trench isolation, and the modeling of dielectrics’ reliability. He was the consul-tant of Nan-Ya Technology, Inc. for the 0.18-m Logic-Team since 1997.
