連續時間轉導電容式三角積分調變器之實現

國 立 交 通 大 學

電信工程學系

碩 士 論 文

連續時間轉導電容式三角積分調變器之實現

Implementation of the continuous-time transconductor-capacitor

Delta-Sigma modulator

研究生：吳國璽

指導教授：洪崇智 博士

連續時間轉導電容式三角積分調變器之實現

Implementation of the continuous-time transconductor-capacitor

Delta-Sigma modulator

研 究 生：吳國璽 Student：Kuo-Hsi Wu

指導教授：洪崇智 Advisor：Chung-Chih Hung

國 立 交 通 大 學

電信工程系

碩士論文

A Thesis

Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

in

Communication Engineering October 2007

Hsinchu, Taiwan, Republic of China

連續時間轉導電容式三角積分調變器之實現

學生：吳國璽

指導教授：洪崇智

國立交通大學電信工程學系碩士班

摘要

由於近年來無線通訊蓬勃發展，因此適用於無線通訊中的類比數位轉換器也受 到更大的矚目。一般無線通訊常為窄頻通訊，為了簡化架構通常希望類比到數位轉 換器在頻帶內可有更高的抗雜訊能力。另一方面也希望能夠在低電壓、低功率下操 作，因此，一個高解析度、低功率耗電且面積小的類比數位轉換器是很重要的。而 三角積分類比數位轉換器就非常符合這個需求，因為它在有限頻寬的限制下可以達 到非常高的解析度。除此之外，類比所佔的成份也相對比較少且對製程漂移的影響 也比較小。因此，近幾年來三角積分類比數位轉換器都扮演著非常重要的角色。 三角積分類比數位轉換器在不同的應用範圍下通常會有兩種種類，一種是離散 時間三角積分類比數位轉換器，因為它通常都是用交換電容的電路下實現，所以又 稱為交換電容三角積分類比數位轉換器。早期論文以離散時間三角積分類比到數位 為主，但是2002 年以後，連續時間三角積分類比到數位則大量的被發表。原因為連 續時間三角積分通常對於運算放大器的要求比較寬鬆，它不需要在一個clock 的時 間下做處理，所以耗費功率比較低，而且具有Anti-aliasing 的性質。 因此，為了將連續時間三角積分類比數位轉換器的優點應用在通信的範圍內， 此研究主題就是做出一個適用於GSM 系統 200k 赫茲頻帶、取樣頻率 20MS/s 的低 功率三階零點最佳化的連續時間轉導電容三角積分類比數位轉換器，以符合可攜式 電子產品需要低消耗功率的趨勢。 晶片是以台積電 0.18 微米標準互補式金氧半導體製程所製造。在 200k 赫茲頻 帶內的量測結果為：最大訊號雜訊失真比為45dB，訊號雜訊比為 47.8dB，動態範 圍是49dB，解析度為 7.2 位元，與預測結果相差約 4 位元。

Implementation of the continuous-time transconductor-capacitor

Delta-Sigma modulator

Student : Kuo-Hsi Wu Advisors : Dr. Chung-Chih Hung

Department of Communication Engineering

National Chiao Tung University

Abstract

Because of the rapid growth of wireless communication, there has been more focus on analog-to-discrete converter (ADC) for wireless communication. Since the frequency is usually narrow-band in general wireless communication, in order to reduce the

complexity of the architecture, we usually require the ADC has the ability of in-band anti-noise. Besides, it is important the ADC operates in low voltage, low-power, and small area. The delta-sigma (ΔΣ) ADC is very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation.

Typically, there are two kinds of ΔΣ ADCs. The first one is the discrete-time (DT) ΔΣ ADC and the other is the continuous-time (CT) ΔΣ ADC. The DT ΔΣ ADC also called the switched-capacitor (SC) ΔΣ ADC because of using switched capacitors. The CT ΔΣ ADC obtains lots of attentions lately. Because the requirement of integrator is relaxed, it does not need to process signals within a clock time. This results in further power reduction.

In order to combine the advantages of the CT ΔΣ ADC system into low-power communication system, this research focuses on low power 20MS/s sample frequency 3-rd order zero optimization CT GM-C ΔΣ ADC for GSM communication system.

The chip has been fabricated by TSMC 0.18-um CMOS process. The measured peak SNDR is 45dB, SNR is 47.8dB and the DR is 49dB. The resolution is 7.2 bits that is 4 bits lower than prediction in 200k HZ signal band.

誌謝

隨著這份碩士論文的完成，兩年來在交大的求學生活也即將告一個段落，往後 迎接著我的，又是另一段嶄新的人生旅程。本論文得以順利完成，首先，要感謝我 的指導教授洪崇智老師在我兩年的研究生活中，對我的指導與照顧，並且在研究主 題上給予我寬廣的發展空間。而類比積體電路實驗室所提供完備的軟硬體資源，讓 我在短短兩年碩士班研究中，學習到如何開始設計類比積體電路，乃至於量測電路， 甚至單獨面對及思考問題的所在。此外要感謝李育民教授、黃淑娟教授、陳科宏教 授撥冗擔任我的口試委員並提供寶貴意見，使得本論文更為完整。也感謝國家晶片 系統設計中心提供先進的半導體製程，讓我有機會將所設計的電路加以實現並完成 驗證。 另一方面，要感謝所有類比積體電路實驗室的成員兩年來的互相照顧與扶持。 首先，感謝博士班的學長羅天佑、薛文弘、廖介偉、黃哲揚以及已畢業的碩士班學 長何俊達、黃琳家、蔡宗諺、林政翰、楊家泰和陳家敏在研究上所給予我的幫助與 鼓勵，尤其是俊達學長，由於他平時不吝惜的賜教與量測晶片時給予的幫助，使得 我的論文研究得以順利完成。另外我要感謝白逸維、邱建豪、廖德文、高正昇、林 明澤、黃旭右和傅崇賢等諸位同窗，透過平日與你們的切磋討論，使我不論在課業 上，或研究上都得到了不少收穫。尤其是718實驗室的同學們，兩年來陪我ㄧ塊兒努 力奮鬥，一起渡過同甘苦的日子，也因為你們，讓我的碩士班生活更加多采多姿， 增添許多快樂與充實的回憶。此外也感謝學弟們林永洲、郭智龍、夏竹緯、楊文霖， 邱楓翔，黃介仁的加入，讓實驗室注入一股新的活力與朝氣。另外感謝好友呂玉玲， 在我低潮時陪伴我，讓我有勇氣面對接下來的挑戰。感謝新竹伙食團所有夥伴，讓 我吃飽睡好，體力充沛。 到這邊，特別要致上最深的感謝給我的父母及家人們，謝謝你們從小到大所給 予我的栽培、照顧與鼓勵，讓我得以無後顧之憂地完成學業，朝自己的理想邁進， 衷心感謝你們對我的付出。 最後，所有關心我、愛護我和曾經幫助過我的人，願我在未來的人生能有一絲 的榮耀歸予你們，謝謝你們。要感謝的人事物太多了，那就謝天吧！ 吳國璽 于 交通大學工程四館 718 實驗室 2007.10.9

Contents

摘要

... I

Abstract ...II

誌謝

... III

Contents...IV

List of figures...VI

List of tables ... VIII

CH1 Introduction...1

1.1 Research Motivation ... 1

CH2 Problem Definition...3

2.1 Continuous-Time vs. Discrete-Time ΔΣ Modulators... 3

2.2 Single-bit vs. multi-bits ΔΣ Modulators ... 6

2.3 Active RC vs. GM-C filter ΔΣ Modulators ... 8

2.4 Conclusion ... 9

CH3 An Overview of Sigma Delta Data Converters ...10

3.1 Introduction... 10

3.2 Overview of Analog-to-Digital Data Converters... 10

3.2.1 Categories of Analog-to-Digital Data Converters... 10

3.2.2 Over-sampling Ratio (OSR) ... 11

3.2.3 Signal to Noise Ratio (SNR) & Spurious Free Dynamic Range (SNDR)12 3.2.4 Spurious Free Dynamic Range (SFDR)... 12

3.2.5 Dynamic Range at the input (DR) ... 12

3.2.6 Effective Number of Bits (ENOB)... 12

3.2.7 Overload Level (OL)... 13

3.3 Sampling Theorem... 13

3.4 Quantization Noise... 14

3.5 Over-sampling Technique ... 18

3.6 Noise Shaping ... 20

3.6.1 Architecture of noise shaping... 20

3.6.2 First-Order ΔΣ Modulator ... 22

3.6.3 Second-Order ΔΣ Modulator... 25

3.6.4 Higher-Order ΔΣ Modulator ... 28

3.6.5 System Analysis of ΔΣ Analog-to-Digital Converters ... 30

3.7 Conclusion ... 31

CH4 Transformation of a Discrete-Time to Continuous-Time...33

4.1 Introduction... 33

4.2 The Impulse-Invariant Transform ... 33

4.3 NRZ Transformation... 35

4.3.1 Effect of Excess Loop Delay ... 41

4.3.2 Root locus of effect of Excess Loop Delay... 44

5.1 Introduction... 46

5.2 Behavior Simulation ... 46

5.2.1 Determine the coefficients for CRFB structure ... 46

5.2.2 Transfer coefficient from discrete-time to continuous-time ... 49

5.2.3 Optimization of the NTF zeros ... 51

5.3 Circuit level Simulation ... 52

5.3.1 GM cell ... 53

5.3.2 Comparator ... 58

5.3.3 Feedback DAC... 59

5.4 Simulation Result... 61

5.5 Layout level design ... 62

CH6 Test Setup and Experimental Results...64

6.1 Measuring equipment... 64

6.2 Power supply regulators... 66

6.3 Input terminal circuit... 66

6.4 Pin configuration and testing board ... 67

6.5 Performance evaluations of SDM... 68

6.6 Summary ... 70

CH7 Conclusions...71

List of figures

Fig 1. 1 Application of ΔΣ ADC in communication receiver ... 1

Fig 2. 1 Discrete-time ΔΣ modulator... 3

Fig 2. 2 Continuous-time ΔΣ modulator ... 4

Fig 3. 1 A/D Converter technologies, resolution and bandwidth ... 11

Fig 3. 2 Illustration of the aliasing of the sampling process (f_s <2 )f_b ... 13

Fig 3. 3 Illustration of the aliasing of the sampling process ( 2f_b ≤ f_ns)... 14

Fig 3. 4 Quantized signal... 15

Fig 3. 5 Quantizer and its linear model... 16

Fig 3. 6 The pdf of quantization noise... 16

Fig 3. 7 Power spectrum density of q(n)... 17

Fig 3. 8(a)Quantization noise power spectrum density for Nyquist-rate... 19

Fig 3. 9 (a) Over-sampling conversion with digital low-pass filter... 19

Fig 3. 10 Block diagram of (a) a noise-shaped SDM and (b) its linear model... 21

Fig 3. 11 The First-Order SDM... 22

Fig 3. 12 The Second-Order SDM... 25

Fig 3. 13 Power spectrum density of 1st order, 2nd order noise-shaping and non noise-shaping strategy... 27

Fig 3. 14 Magnitude of NTF... 27

Fig 3. 15 The Higher-Order SDM... 28

Fig 3. 16 Plot of SNR versus SDM... 30

Fig 3. 17 Block diagram of an over-sampling A/D converter... 31

Fig 3. 18 Signal and spectra in an over-sampling ADC... 32

Fig 4. 1 continuous-time ΔΣmodulator... 34

Fig 4. 2 ΔΣ open loop block diagram... 34

Fig 4. 3 Open-loop impulse response of the second-order low-pass modulator... 35

Fig 4. 4 A continuous-time ΔΣmodulator in S-domain... 36

Fig 4. 5 The DAC pulse... 40

Fig 4. 6 Illustrations of excess loop delay on NRZ DAC pulse... 41

Fig 4. 7 The delayed NRZ pulse as a linear combination... 43

Fig 4. 8 Linear SDM with one-bit quantizer arbitrary gain k.... 44

Fig 4. 9 Effect of loop delay on root locus of NTF ( , )zτ_d ... 45

Fig 5. 1 MATLAB code for creating a low-pass NTF... 47

Fig 5. 2 MATLAB code with coefficient and CRFB structure... 49

Fig 5. 3 A CIFB ΔΣ structure... 49

Fig 5. 4 CRFB continuous-time ΔΣ in time domain... 50

Fig 5. 5 The time-domain output data... 51

Fig 5. 6 The power spectrum of output data... 51

Fig 5. 7 Implementation of third-order GM-C continuous-time SDM... 53

Fig 5. 8 (a) Common-drain amplifier (voltage follower) (b) FVF.... 54

Fig 5. 9 Schematic of FVF GM... 55

Fig 5. 10 Gain-bandwidth, phase-margin and GM of FVF... 56

Fig 5. 12 Current-Mode Comparator... 58

Fig 5. 13 Comparator latch and sampling clock... 59

Fig 5. 14 (a) The cascade transistors DAC. (b) DAC with ideal current source.... 59

Fig 5. 15 Tradeoff between dc output resistance and the non-dominant pole. [20].. 60

Fig 5. 16 The simulation of continuous-time GM-C SDM in time-domain.... 61

Fig 5. 17 The power spectrum of continuous-time GM-C SDM.... 61

Fig 5. 18 Diagram of SDM layout... 63

Fig 6. 1 Experimental testing setup... 64

Fig 6. 2 Function generator Agilent 33250A... 65

Fig 6. 3 Logic analyzer Agilent 16702B... 65

Fig 6. 4 Oscilloscope Agilent S4832D... 65

Fig 6. 5 Power supply regulator... 66

Fig 6. 6 Input terminal circuit... 67

Fig 6. 7(a) Pin configuration diagram and (b) Pin assignment... 67

Fig 6. 8 Photograph of the SDM DUT board... 68

Fig 6. 9 Measurement result of output waveform... 68

Fig 6. 10 Measured output spectrum... 69

List of tables

Table 2.1 Main advantages of continuous-time ΣΔ modulators over DT ΣΔ

modulators... 6

Table 2.2 Main disadvantages of continuous-time ΣΔ modulators compared to DT ΣΔ modulators... 6

Table 4.1 s-domain equivalences for z-domain loop filter poles [12]... 40

Table 5.1 The zero placements for minimum in-band noise... 52

Table 5.2 Specification of the first amplifier... 57

Table 5.3 The specification of the continuous-time GM-C SDM.... 62

CH1 Introduction

1.1 Research Motivation

Nowadays, the demand for the wide band communications is driving the advancement of the digital modulation techniques and the increasing complexity of circuits. For this purpose, the analog signal processing is replaced with the digital signal processing circuit in the receiver.

Besides this, the complexity and single-chip integration of the analog circuit in the receiver chain can also be implemented by a proper architecture. As shown in Fig.1.1, by pushing the A/D converters close to the antenna, the total analog components in the receiver chain will be reduced.

Fig 1. 1 Application of ΔΣ ADC in communication receiver

Many design challenges, however, exist when the A/D converters move close to the antenna. It is challenging to achieve high-resolution, low-voltage and low-power operation in high-performance communication systems. Without the switched -capacitor circuits in continuous-time delta-sigma ADCs, the requirements of the transconductance amplifiers(GM) are more relaxed and the power consumption of the GM are thus greatly reduced. In addition to this, the speed of the continuous-time circuits is not limited to the settling time of the charge, and the wide bandwidth is more easily attained. The over-sampling techniques with noise shaping strategy are widely used to implement the analog-to-digital interface between analog and digital domain in digital systems. This type of systems require high resolution or low power consumption. Sigma-delta data

converters have meaningful advantages over traditional Nyquist-rate counterparts. The anti-aliasing filter is usually in front of the switched capacitor circuits to avoid the aliasing effect. However the filter is not required in the continuous-time delta-sigma ADC, that further simplify the receiver design.

CH2 Problem Definition

2.1 Continuous-Time vs. Discrete-Time ΔΣ Modulators

The general structures of DT and CT ΣΔ modulators are shown in Figures 2.1 and 2.2 respectively.

In the following we will discuss the main advantages of CT ΣΔ modulators over their DT counterparts.

Fig 2. 1 Discrete-time ΔΣ modulator

Low Voltage Operation:

The continuously decreasing supply voltage of recent CMOS technologies is causing important limitations to the performances of switched-capacitor circuits. Switch-bootstrapping or switched-OPamp circuit techniques are now necessary in order to obtain sufficiently low on-resistances.

Fig 2. 2 Continuous-time ΔΣ modulator Sampling Frequency:

In switched-capacitor circuits several errors occur while sampling the input signal. These errors are due to the switch non-linearity, charge injection, clock feedthrough and finite settling time. Sampling errors in switched-capacitor circuits limit the sampling frequency, fs, of DT ΣΔ modulators.

In CT modulators sampling occurs inside the ΣΔ loop, therefore sampling errors are shaped out of the frequency band of interest just like quantization noise.

Power Consumption:

In switched-capacitor circuits the unity gain frequency of operational amplifiers must be at least five times the sample rate. High quiescent current is then required to achieve high bandwith. On the other hand, unity gain frequencies of the integrators in the CT ΣΔ are usually lower than the sampling frequency.

Furthermore, since sampling occurs inside the ΣΔ loop, this strongly reduces:

. Thermal noise is aliasing in the frequency band of interest.

power consumption than their DT counterparts.

It has also been shown, in [1], that CT ΣΔ modulators are less sensitive to asynchronous substrate interference from neighboring digital circuitry than DT ΣΔ modulators. This will be an important issue for future SOC (System on Chip) design.

While DT ΣΔ modulators are insensitive to the shape of the feedback signal as long as full settling occurs, the main disadvantages of CT ΣΔ modulators are related to switching characteristics of the feedback signal:

Excess Loop Delay:

The delay in the feedback signal is mainly due to the comparator response-time. This delay has been found to alter the frequency response and degrade the signal-to-noise ratio (SNR) of the CT ΣΔ modulators. Using a Return-to-Zero (RZ) feedback signal gives enough time for the comparator output to settle and thus eliminates any influence of the comparator delay on the SNR.

DAC Output Rise and Fall Time Asymmetry:

Unequal rise and fall times of the DAC output current introduces harmonic distortion. The effect of this waveform asymmetry can also be highly attenuated by the use of a RZ feedback DAC.

Clock Jitter:

Clock jitter in feedback signal increases the noise level in the signal band. Unlike excess loop delay and DAC waveform asymmetry, clock jitter influence on the CT modulators cannot be attenuated by a RZ feedback signal.

After this discussion on the advantages and disadvantages of CT ΣΔ modulators compared to the DT ΣΔ modulators (summarized in tables 2.1 and 2.2), we believe that CT modulators will play an important role in recent and future CMOS technologies. This is mainly because of their advantages concerning low voltage, low power and high sampling frequency.

Table 2.1 Main advantages of continuous-time ΣΔ modulators over DT ΣΔ modulators

Table 2.2 Main disadvantages of continuous-time ΣΔ modulators compared to DT ΣΔ modulators

In the following, we will discuss the main difficulties and the different issues associated with the design and implementation of CT ΣΔ modulators.

2.2 Single-bit vs. multi-bits ΔΣ Modulators

The ADC resolution at a low OSR can be improved by using a higher-order loop filter, and/or by increasing the internal quantizer resolution. For single-bit, single-loop modulators, the integrator’s gain must be reduced to preserve the loop stability. Therefore,

simply increasing the loop filter order at a low OSR will result in a poor SNR improvement.

Since multibit quantizers have a more linear gain than single-bit quantizers, the stability of multibit, single-loop SD modulators is significantly improved. As a result, more aggressive noise transfer function can be designed, with the benefit of extra dynamic range for every additional bits n of DR ∝ 20 log (2n - 1) dB.

Alternatively, increasing quantizer resolution enables us to use a lower noise-shaping filter for a given OSR. Unfortunately, it is necessary to double the number of comparators for each additional bit of quantizer resolution. Obviously, this costs silicon area as well as

power dissipation and thus degrades the FOM for a given resolution In addition, multi-bits SD ADCs are sensitive to non-idealities such as mismatch in the feedback digital-to-analog converter (DAC), as these errors are added directly to the input signal and are thus not noise-shaped.

Nevertheless, deep-submicron technologies feature excellent matching characteristic as high as 11 bits or 12 bits of resolution. Hence, careful layout and design can fulfill linearity requirements of an internal-feedback DAC, provided that the SD ADC is lower than 12-bit resolution, which is typically the case for W-CDMA.

For a SD ADC’s resolution that exceeds the matching possibilities of CMOS or Bi-CMOS, this problem must be addressed. The solution consists of using dynamic element matching (DEM).

DEM converts the DAC element errors to high frequency noise. Thereby, highly linear over-sampling DAC can be built with only moderate matching requirements for the DAC element.

DEM techniques have been developed since 1998, starting with randomization of the DAC elements. The methods are continuously improved with respect to implementation efficiency and order of shaping. Since the presentation of [2] in 1995 and the disclosure of the ADC design in 1997, these techniques have been well established in the sigma

delta design community, allowing efficient and robust implementation of sigma-delta ADC’s with resolution of more than 14 bits and bandwidth beyond 1 MHz.

However, the single bit should be preferred to multi-bit SD ADCs when the conversion bandwidth is lower than 5 MHz (GSM, Bluetooth, W-CDMA) because they achieved better FOM and are less silicon area-consuming.

2.3 Active RC vs. GM-C filter ΔΣ Modulators

Active RC integrator has an amplifier in feedback loop and gives better linearity performance than a GM-C integrator. In a GM-C integrator, the transconductor is in open loop and hence you would expect lower linearity than an amplifier operating in a feedback loop.

In a CT sigma-delta (or for that matter any sigma-delta), the linearity of the overall system is limited by the linearity of the first stage and the linearity of the DAC connected to the first stage (higher OSR helps to suppress this requirement to some extent). The linearity of the subsequent stages is masked by the loop gain upto that stage, so the 2nd and 3rd stage does not have very stringent linearity requirements. Because of this reason, it is preferable to have active-RC integrator as first stage.

The main disadvantage of active-RC is that the amplifier bandwidth has to be high enough to operate in feedback configuration. In addition, it needs to have enough gain in the signal bandwidth to provide good linearity (linearity is related to gain at that frequency, higher the amplifier gain in the signal frequency, better is the linearity). The gm of GM-C integrator has lower gain bandwidth requirement since it operates in open loop and hence can consume lower power.

So in terms of power optimization, first stage has active-RC (higher power) and subsequent stages have GM-C (lower power). Overall, this arrangement gives best performance optimum power consumption.

first stage active-RC integrator.

Advantage of an all GM-C would be lower power at the cost of lower linearity. Input referred noise comparison cannot be generalized as it depends on the value of R in the active-RC integrator, but the R values can be adjusted such that input referred noise of active-RC integrator can be made lower than the GM-C integrator, which implies a higher dynamic range if active-RC integrator is used as the first stage.

2.4 Conclusion

The published SD ADCs for wireless applications have been reviewed for the 2002-2004 period. Since 2003, there has been a strong trend to increase the bandwidth conversion while keeping reasonable clock frequency. This means that the OSR tends to decrease.

As a result, multi-bit SD loops are preferred for bandwidth demanding applications such as WLAN. However, single-bit SD modulators are recommended for wireless applications that require less than 5 MHz conversion bandwidth because they offer better trade-offs for power, area and circuit complexity. Moreover CT SD modulators are suited for a low-cost integration because they provide anti-aliasing filtering without silicon-area penalty and can potentially operate with less power consumption than DT implementation. At least, single loop topology is preferable in low-voltage, low-power designs because it is less sensitive to analog circuit non-idealities, such as insufficient op-amp dc gain that tends to decrease at each CMOS technology node.

CH3 An Overview of Sigma Delta Data

Converters

3.1 Introduction

This chapter reviews the basic concept of design the sigma-delta data converter. The discussion begins with a brief overview of data converter in the aspects of speed, resolution, and architecture. After this issue, the theories of how sigma-delta modulators work including sampling, quantization, over-sampling, and noise shaping will be discussed. Following the introduction, tradeoffs of various sigma-delta modulator architectures will be discussed.

3.2 Overview of Analog-to-Digital Data Converters

The operations of analog-to-digital data converters can be roughly separated into two steps: sampling and quantization. The process of sampling transforms continuous time analog signals into discrete time step-like signals. The process of quantization converts the step-like signals to a set of discrete levels. Then, these discrete levels signals can be coded and be transmitted into DSP units or digital systems.

3.2.1 Categories of Analog-to-Digital Data Converters

According to operation, speed, and accuracy, there are three categories of analog- to-digital converter shown in Fig.3.1. Each category is applied in different field. But the demarcation for some structures nowadays is a little blurred.

Fig 3. 1 A/D Converter technologies, resolution and bandwidth

3.2.2 Over-sampling Ratio (OSR)

The over-sampling ratio (OSR) of a data converter is defined as

2 s b f OSR f = (3.1) where f is the sampling frequency and _s f is the signal bandwidth. When the OSR is b equal to 1 ( f_s =2f_b), it means the data converter is the Nyqist-rate data converter, however, when the OSR is great than 1, it means the data converter is the over-sampling data converter. The OSR is the important parameter for over-sampling data converters. The OSR increases the SNR by (2n+ ⋅1) 3dB or by 2n+ per octave, where n is the 1 order of loop-filter.

The larger the OSR, the larger the sampling frequency when the signal

bandwidth is fixed. Thus, it will need faster circuit and consume more power consumption. But the OSR need to keep as low as possible for high signal bandwidth consideration. In order to obtain the advantages of using noise- shaping strategy, the OSR should be at least 4 [3].

3.2.3 Signal to Noise Ratio (SNR) & Spurious Free Dynamic Range (SNDR) The signal-to-noise ratio (SNR) of a data converter is the ratio of the signal power to the noise power, which measured at the output of the data converter. The maximum SNR that a converter can achieve is called the peak signal-to-noise ratio. Generally, the theoretical value of SNR for an N-bit Nyquist-rate ADC is given by

6.02 1.76

SNR= ⋅ +N dB (3.2)

But for over-sampling ADC, the theoretical value of SNR is

6.02 1.76 10log( )

SNR= ⋅ +N + OSR dB (3.3)

The signal to noise and distortion ratio (SNDR) of a data converter is the ratio of the signal power to the power of the noise plus the harmonic distortion components, which measured at the output of the data converter. The maximum SNDR that a converter can achieve is called the peak signal to noise and distortion ratio. Generally, SNDR is lower than SNR.

3.2.4 Spurious Free Dynamic Range (SFDR)

The spurious free dynamic range (SFDR) is defined as the ratio of rms value of amplitude of the fundamental signal to the rms value of the largest harmonic distortion component in a specified frequency range. SFDR may be much larger than SNDR of a data converter.

3.2.5 Dynamic Range at the input (DR)

The dynamic range is defined as the ratio between the power of the largest input signal which didn’t significantly degrade the performance and the power of the smallest detectable input signal which is determined by the noise floor of converters.

3.2.6 Effective Number of Bits (ENOB)

For data converter, a specification often used in place of the SNR or SNDR is ENOB, which is a global indication of how many bits would be required to get the same performance as the converter. ENOB can be defined as follows:

1.76 6.02 SNDR

ENOB= − bits . (3.4) 3.2.7 Overload Level (OL)

OL is defined as the relative input amplitude where the SNR is decreased by 6dB compared to peak SNR value.

3.3 Sampling Theorem

Naturally, signals transmitted in the air are analog whether they originate from. The analog signals need to be sampled to become the digital signals for suitability in processing in the digital system. Thus, sampling is a very important procedure in the front end of the overall system. How much information can be preserve from the original signals depend on how fine to sample the signals and deal. It is crucial to choose the sampling frequency with a fixed signal bandwidth. And the relationship between the sampling frequency, f , and the signal bandwidth,_s f , is shown as follows : b

2

s b

f ≥ f (3.5)

At least the sampling frequency must be greater than twice the input signal bandwidth to avoid aliasing. If f is smaller than twice the signal bandwidth, aliasing will occur at the _s output signal spectrum as shown in Figure 3.2.

b f b f − s f 2fs 3fs 4fs s f − 2fs − 3fs − 4fs − 0 0 −4fs −3fs −2fs −fs 0 fs 2fs 3fs 4fs Input Signal Spectrum

Sampling Clock Spectrum (Impulse Function) Convolution Output Signal Spectrum _s 2 _b when f < f

Fig 3. 2 Illustration of the aliasing of the sampling process (f_s <2 )f_b

order to match the equation. The frequency f show be larger than 2_ns f .This is more _b popular to deal with aliasing problems because there is no information of original input signal loss as shown in Figure 3.3. And just a low pass filter at the output is needed to recover the original signal.

b f b f − ns f 2fns ns f − 2fns − 0 0 −2fns −fns 0 fns 2fns Input Signal Spectrum

Sampling Clock Spectrum (Impulse Function) Convolution Output Signal Spectrum _ns 2 _b when f ≥ f

Fig 3. 3 Illustration of the aliasing of the sampling process ( 2f_b≤ f_ns)

3.4 Quantization Noise

The quantizer is the interface between analog and digital domain. Once the analog signals pass through the quantizer, the signals will be digitized and separated into several different levels. The space between two adjacent levels is called a step size, Δ. There are two types of quantizer. One is uniform, and another is non-uniform. In a uniform quantizer, the distance between two adjacent levels is uniform; otherwise it is a non-uniform quantizer.

The process of quantization introduces an error, q(n). The error is defined as the difference between the input signal, x(n), and the output signal, y(n). And it is called the quantization error. Figure 3.4 and Figure show the quantization process and assume the quantizer is uniform.

to Bennett [4]. Bennett first developed conditions under which quantization noise could be reasonably modeled as additive white noise. A common statement of the approximation is that the quantization error has the following properties, which we call it the “input-independent additive white-noise approximation” [5]:

a. q(n) is statistically independent of the input signal b. q(n) is uniformly distributed in [-Δ/2, Δ/2]

c. q(n) is an independent identically distributed sequence or q[n] has a flat power spectral density (white).

Fig 3. 4 Quantized signal

Since the quantization noise, q(n), is equal to y(n)-x(n), a quantizer can be modeled as shown in Figure 3.5 [6] . For a uniform quantizer, if the input signal does not overload, the quantization error will be bounded by ±Δ/2. If the Δ is very small, it is convenient and reasonable to assume the quantization noise is zero

mean and uniform distribution (Figure 3.6). The probability density function (pdf) of the quantization noise can be express as

1 , - 2 ( ) 2 ( ) 0, otherwise Q q n f q = ⎨⎧ Δ Δ ≤ ≤ Δ ⎩ (3.6)

x(n)

y(n)

Quantizer

x(n)

y(n)

q(n)

Model

Fig 3. 5 Quantizer and its linear model

( ) Q f q

2

− Δ

1

Δ

2

Δ

Fig 3. 6 The pdf of quantization noise

From Figure 3.6, the power of quantization noise can be shown as follows:

2 2 ₂ , ₂ 1 12 Q noise P Δ q dq −Δ Δ = = Δ

∫

(3.7) The power spectrum density of q(n), S_Q( )f , within the range of ± f calculated using the _s equation (3.8) is

2 ₂ , _{12 2} ( ) s s f Q noise _f Q P S f df − Δ = =

∫

(3.8) And we obtain the final result of S_Q( )f as

( ) 12 Q s S f f Δ = (3.9)

From equation (3.9) we show that power spectrum density is inversely proportional to sampling frequency shown in Figure 3.7. The larger the sampling frequency is, the less the noise amplitude is.

Fig 3. 7 Power spectrum density of q(n)

Assume the quantization signal is uniformly distributed over the range± , and N is the V_A bits per sample. The step size can be write as

2 2 A N V Δ = (3.10)

According to the equations above, the SNR can be shown as

2 2 , 2 10 log 10log( ) 6.02 1.76 12 signal A Q noise P _V SNR N P = = = + Δ (3.11)

Equation (3.11) shows that increasing the number of bits per sample in the qunatizer increases the accuracy of the converter by 6dB for each extra bit.

3.5 Over-sampling Technique

Over-sampling is an important technique for sigma-delta ADCs. It can release the requirement of anti-aliasing filter. And it also can improve the resolution of a sigma-delta ADC. This improvement is achieved by over-sampling the signal. In other words, the sampling rate is much greater than Nyquist-rate. The definition of over-sampling ratio (OSR) is 2 _s b f OSR f = (3.12)

where f is the sampling frequency and _s f is the input signal bandwidth. Assuming _b the quantization noise is white noise. It means that noise power is uniformly distributed between −f_s 2 and f_s 2. It had shown that total amount of noise power injected into the quantized signals are the same whether they are over-sampling or Nyquist-rate conversions. But the distributions are different due to different sampling frequencies. Figure 3.8 shows the power spectrum density of quantization noise S_Q( )f for conversion of Nyquist-rate (dotted line) sampling with sampling frequency, f_{s NR,} , and over-sampling (solid line) sampling with sampling frequency, f_{s OS,} , which is much greater than input signal bandwidth, f . The power spectrum density of input signal _b bandwidth for Nyquist rate is much greater than over-sampling.

The area of the both two rectangles meaning the total amount of noise power are the same and equal to _Δ2 _{12. From Figure 3.8, it shows that the quantization noise power} has spread to f_{s OS,} 2 and only a small fraction of quantization noise fall into the range of − and f_b f . And the quantization noise outside the signal band will be attenuated by b a digital low-pass filter as shown in Figure 3.9. Recollecting the quantization noise power

Fig 3. 8(a) Quantization noise power spectrum density for Nyquist-rate (b) Over-sampling (solid line) conversion

spectrum density in equation (3.9) then we can show that the quantization noise is becoming ( ) LP H f (a) b f b f − f_s s f − ( ) LP H f (b)

Fig 3. 9 (a) Over-sampling conversion with digital low-pass filter (b)magnitude of frequency response of digital low-pass filter

2 , 2 2 ( ) ( ) ( ) 2 (2 ) 12 12 b b s b f f Q noise _f Q LP _f Q b b s s P S f H f df S f df f f f f − − = ⋅ = Δ Δ = ⋅ = ⋅

∫

∫

(3.13) then we obtain 2 2 , 2 1 12 12 b Q noise s f P f OSR Δ Δ = ⋅ = ⋅ (3.14)

According equation (3.7), (3.10), (3.12) and (3.14), the SNR of over-sampling conversion is

2

2 ,

2

10 log 10 log 6.02 1.76 10log( )

1 12 A signal Q noise V P SNR N OSR P OSR ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ = ⎜_⎜ ⎟_⎟= ⎜ ⎟= + + Δ ⎜ ⎟ ⎝ ⎠ _{⎜ ⋅ ⎟} ⎝ ⎠ (3.15)

The first term of equation (3.15) denotes the contribution of N-bit quantizer and the last term is the enhancement of over-sampling technique. For every doubling the OSR, the SNR improve by 3dB corresponding to improve the resolution by 0.5 bit. Besides, since the resolution of N-bit quantizer is lower than overall resolution of system, it could reduce the complexity of analog circuit and power of overall system.

3.6 Noise Shaping

3.6.1 Architecture of noise shaping

A general noise-shaped sigma-delta modulator and its linear model have been shown in Figure 3.10.

(a)

(b)

Fig 3. 10 Block diagram of (a) a noise-shaped SDM and (b) its linear model We can show that

( )y n =x n( − +1) q n( )−q n( − (3.16) 1)

After transforming equation (3.16) by Z-transform, we obtain

( ) 1 ( ) ( ) ( ) 1 ( ) 1 ( ) H z Y z X z Q z H z H z = + + + (3.17)

Then we can derive signal transfer function (S_TF( )z ) by setting Q(z)=0

( ) ( ) ( ) ( ) 1 ( ) TF Y z H z S z X z H z = = + (3.18)

The same, we can derive noise transfer function (N_TF( )z ) by setting X(z)=0 ( ) 1 ( ) ( ) 1 ( ) TF Y z N z Q z H z = = + (3.19)

The equation (3.17) will become

( ) _TF( ) ( ) _TF( ) ( )

Y z =S z ⋅X z +N z Y z⋅ (3.20)

The STF generally have all-pass or low-pass frequency response and the NTF have high-pass frequency response. In other words, the STF will be approximately unity over the signal band and the NTF will be approximately zero over the same frequency band. The quantization noise will be removed to high frequency band when using noise-shaping strategy [7]. The quantization noise over the frequency band of interest will be reduced and do not affect the input signal. This would improve the SNR significantly for overall system.

3.6.2 First-Order ΔΣ Modulator

Fig 3. 11 The First-Order SDM

In Figure 3.11, it is a simple block diagram of the first-order SDM [8]. It includes an integrator and 1-bit quantizer. The noise-transfer function,N_TF( )z , should have a zero at DC. And zeros of N ( )z are equal to poles of the H z (ie., has a pole at z=1). ( )

Therefore, the quantization noise will be high-pass filtered. In other words, the ( )

H z will be small and the N_TF( )z will large over the frequency band of interest. Thus, the discrete time integrator with a pole at DC can be expressed as

1 1 1 ( ) 1 1 z H z z z − − = = − − (3.21)

According to equation (3.18) and (3.19) we obtain

1 1 1 1 1 ( ) 1 ( ) 1 ( ) 1 1 TF H z z z S z z H z z z − − − − − − = = = + + − (3.22) 1 1 1 1 1 ( ) 1 1 ( ) 1 1 TF N z z H z z z − − − = = = − + + − (3.23)

The total transfer function of system is

1 1

( ) ( ) ( ) (1 )

Y z =X z ⋅z− +Q z ⋅ −z− (3.24)

From equation (3.24) we know the STF is just a delay and NTF is a high-pass filter. In another word, the output signal comprises the delayed input signal and high-pass filtered quantization noise. Now, we may consider the amplitude of the noise transfer function, N_TF( )z . Let _z=_ej Tω =_ej2πf fs, equation (3.23) will becomes

2 1 ( ) 1 1 1 2 2 sin 2 s s s s s j f f j T TF j f f j f f j f f j f f s N z z e e e e j e j f j e f π ω π π π π π − − − − − − = − = − = − − = ⋅ ⋅ ⎛ ⎞ = _{⎜ ⎟}⋅ ⋅ ⎝ ⎠ Then we obtain ( ) 2sin TF s f N f f π ⎛ ⎞ = _{⎜ ⎟} ⎝ ⎠ (3.25)

The quantization noise power over the signal band is shown as follows: 2 2 2 , 1 ( ) ( ) 2sin 12 b b b b f f Q noise _f Q TF _f s s f P S f N z df df f f π − − ⎡ ⎛ ⎞⎤ Δ = ⋅ = _{⎢ ⎜ ⎟⎥} ⎝ ⎠ ⎣ ⎦

∫

∫

(3.26)

Because OSR  for over-sampling conversion,1 f would be much larger thans f . Thus, b

(

)

sin πf f_s can be approximated to π f f_s. Equation (2.26) will become

2 3 ₃ 2 2 2 2 2 , 2 1 2 12 12 3 36 b b f b Q noise _f s s s f f P f f f OSR π π π − ⎡ ⎛ ⎞⎤ ⎛ ⎞ Δ Δ Δ ⎛ ⎞ = _{⎢ ⎜ ⎟⎥} = ⋅ ⋅_{⎜ ⎟} = _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦

∫

(3.27)

Using the equation (3.10) and (3.27), we obtain the SNR of first-order SDM

(

)

2 2 2 3 3 2 2 2 2 , 2 8 2

10 log 10 log 10 log

1 1 36 36 6.02 1.76 5.17 30 log dB N A signal Q noise V P SNR P OSR OSR b OSR π π ⎛ ⎞ ⎛ _Δ ⎞ ⎜ ⎟ ⎜ ⎟ ⎛ ⎞ _{⎜ ⎟ ⎜ ⎟} = ⎜_⎜ ⎟_⎟= _{⎜ ⎟}= _{⎜ ⎟} Δ ⎛ ⎞ Δ ⎛ ⎞ ⎝ ⎠ _{⎜ ⎜ ⎟ ⎟ ⎜ ⎜ ⎟ ⎟} ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ = + − + (3.28)

For every doubling the OSR, the SNR will improve by 9dB (ie., resolution will increase 1.5 bits). This result can be compared with equation (3.15), the SNR only can improve by 3dB when over-sampling conversion do not use noise-shaping strategy. It will be much efficiency when using noise-shaping technique.

3.6.3 Second-Order ΔΣ Modulator

Fig 3. 12 The Second-Order SDM

In Figure 3.12, it is a block diagram of a second-order SDM. It is popular and widely used in SDM designing. It includes two integrators and a 1-bit quantizer. Its fundamental theorem is the same as the first-order SDM. Thus, the transfer function can be expressed as

_{( ) ( )} 2 _{( ) (1} 1 2₎

Y z =X z ⋅z− +Q z ⋅ −z− (3.29)

And we can show the S_TF( )z and NTF( )z

_{( )} 2 TF S z =z− (3.30) 1 2 ( ) (1 ) TF N z = −z− (3.31)

Thus we obtain the magnitude of N_TF

2 ( ) 2sin TF s f N f f π ⎡ ⎛ ⎞⎤ = ⎢ ⎜ ⎟⎥ ⎝ ⎠ ⎣ ⎦ (3.32)

2 2 2 , 4 5 5 2 2 4 2 4 1 ( ) ( ) 2sin 12 2 1 2 12 12 5 60 b b b b b b f f Q noise _f Q TF _f s s f b f s s s f P S f N z df df f f f f f f f OSR π π π π − − − ⎡ ⎛ ⎞⎤ Δ = ⋅ = _{⎢ ⎜ ⎟⎥} ⎝ ⎠ ⎣ ⎦ ⎡ ⎛ ⎞⎤ ⎛ ⎞ Δ Δ Δ ⎛ ⎞ ≈ _{⎢ ⎜ ⎟⎥} = ⋅ ⋅_{⎜ ⎟} = _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦

∫

∫

∫

(3.33)

With the same method, we can obtain the SNR of the second-order SDM as

(

)

2 2 2 5 5 2 4 2 4 , 2 8 2

10 log 10 log 10log

1 1 60 60 6.02 1.76 12.9 50 log dB N A signal Q noise V P SNR P OSR OSR b OSR π π ⎛ ⎞ ⎛ _Δ ⎞ ⎜ ⎟ ⎜ ⎟ ⎛ ⎞ _{⎜ ⎟ ⎜ ⎟} = ⎜_⎜ ⎟_⎟= _{⎜ ⎟}= _{⎜ ⎟} Δ ⎛ ⎞ Δ ⎛ ⎞ ⎝ ⎠ _{⎜ ⎜ ⎟ ⎟ ⎜ ⎜ ⎟ ⎟} ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ = + − + (3.34)

For every doubling the OSR, the SNR will improve by 15dB (ie., resolution will increase 2.5 bits). This result can be compared with equation (3.15) and (3.28), the second-order SDM can provide more suppression over the same band, and thus more noise power outside the signal band. Figure 3.13 shows the phenomenon of using noise-shaping technique or not. For a fixed signal band, the case of no noise-shaping has the largest quantization power over the signal band. The second and the third are

Fig 3. 13 Power spectrum density of 1st _{order, 2}nd _{order noise-shaping and non}

noise-shaping strategy

the first-order SDM and the second-order SDM respectively. As the number of order increasing, the quantization noise power will decrease over the same signal band. The simulation result can show as Figure 3.14.

3.6.4 Higher-Order ΔΣ Modulator

Fig 3. 15 The Higher-Order SDM

Higher-order SDM is divided into single-stage and multi-stage structures [9]. Figure 3.15 is the system block diagram of single-stage Lth-order SDM. Here, we will discuss the change of quantization noise and SNR when the number of order increases.

With the same approach, we obtain the noise-transfer function,N_TF,of the Lth-order SDM as follows:

(

1

)

L TF

N = −z (3.35) In a similar manner, the quantization-noise power over the signal band of the single-stage Lth-order SDM with N-bits quantizer is

2 2 2 , 2 2 1 2 2 2 1 2 2 1 ( ) ( ) 2sin 12 2 2 12 12 2 1 1 12(2 1) b b b b b b L f f Q noise _f Q TF _f s s L _L L f b f s s s L L f P S f N z df df f f f f f f L f L OSR π π π π − − + − + ⎡ ⎛ ⎞⎤ Δ = ⋅ = _{⎢ ⎜ ⎟⎥} ⎝ ⎠ ⎣ ⎦ ⎡ ⎛ ⎞⎤ ⎛ ⎞ Δ Δ ≈ _{⎢ ⎜ ⎟⎥} = ⋅ ⋅_{⎜ ⎟} + ⎝ ⎠ ⎝ ⎠ ⎣ ⎦ Δ ⎛ ⎞ = _{⎜ ⎟} + ⎝ ⎠

∫

∫

∫

(3.36)

2 2 1 2 2 , 2 2 2 1 2 2 2 10log 10log 1 12(2 1) 2 8 10log 1 12(2 1) A signal L L Q noise N L L V P SNR P L OSR L OSR π π + + ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ _{⎜ ⎟} = ⎜_⎜ ⎟_⎟= _{⎜ ⎟} Δ ⎛ ⎞ ⎝ ⎠ _{⎜ ⎜ ⎟ ⎟} + ⎝ ⎠ ⎝ ⎠ ⎛ _Δ ⎞ ⎜ ⎟ ⎜ ⎟ = ⎜ _{Δ ⎛ ⎞} ⎟ ⎜ _{⎜ ⎟} ⎟ + ⎝ ⎠ ⎝ ⎠

Finally, we get the result

(

) (

)

2 6.02 1.76 10 log 20 10 log dB 2 1 L SNR b L OSR L π ⎛ ⎞ = + + _{⎜ ⎟}+ + + ⎝ ⎠ (3.37)

From equation (3.37), we know that for every doubling the OSR, the SNR will improve by (6L+3) dB (ie., resolution will increase L+0.5 bits). There are three ways to increase the SNR of a SDM. First, we can increase the bits of quantizer. The disadvantage is that multi-bit quantizer would induce harmonic distortion because of mismatch. Second, we can increase the number of order of a SDM. But it may have stability problem when the order is greater than 2. Third, increasing the OSR is the most popular way to improve the performance But for low power design, increasing

Fig 3. 16 Plot of SNR versus SDM

the OSR is not suitable becausethe requirement of the integrators, such as settling time, bandwidth, and slew rate will be increased. Beside, the power of decimation filter will also be increased because of high sampling frequency. Figure 3.16 is the SNR of SDM. This plot provides a tradeoff between order, OSR and the power dissipation.

3.6.5 System Analysis of ΔΣ Analog-to-Digital Converters

The system architecture for a typical over-sampling ADC is shown in Figure 3.17. The anti-aliasing filter is used to filter the out-of-band noise of original input signal to avoid noise folding into signal band. Then, the signal is sampled and held and applied to a SDM and output a 1-bit digital signal. Usually, the sample-and-hold usually combines with the SDM. These three blocks are belonging to analog domain. A decimation filter which contains a digital low-pass filter and a down-sampling not only suppresses the

out-of-band quantization noise but also down-sample the sampling frequency from f _s to Nyquist-rate [10]. Note that the digital low-pass filter here is like an anti-aliasing filter to limit signals to one-half the output sampling rate. The decimation filters generally are implemented using digital circuit technique in order to reduce the power dissipation and are easy to implement. Figure 3.18 shows the signal and spectra of each stage of over-sampling ADC [11].

Fig 3. 17 Block diagram of an over-sampling A/D converter

3.7 Conclusion

In this chapter, we have introduced the basic principles of sigma-delta modulator. Among these, the most important is the properties of shaped quantization error. Here, various architectures of SDM such as single-loop and cascaded was introduced and compared. And then, the advantages and disadvantages of multi-bit quantizer was described and analyzed. In the final part of this chapter, we discuss how the signal and spectra change in different section of the over-sampling ADC and DAC. This would make us much clear about the operation of over-sampling system.

c X (t) sh X (t) 1 2 3 4 lp X (n) ± sdm X (n) = 1 1 2 3 s X (n) 1 2 3 c X (f) o f f_s ω s X ( ) π 2π 4π 6π 8π 10π 12π ω f sh X (f) o f f_s f ω sdm X ( ) 0 2 s f f π ω 2π ω lp X ( ) 0 2 s f f π ω 2π t n n n Time Frequency

CH4 Transformation of a Discrete-Time to

Continuous-Time

4.1 Introduction

Early designs of continuous-time ΣΔ modulators were approximate, guided by the intuition that the general continuous-time integrators

ω

₀ should work for low-pass modulators and correspondingly the continuous-time resonators _/( 2 ₎

OS S O

ω +ω for

band-pass modulators. However, this simple assumption leads to implementation of an incorrect loop transfer function for a ΣΔ modulator. In this chapter it is shown that a continuous-time ΣΔ loop filter has to be designed according to the digital to analog converter (DAC) output waveform in the feedback path of the modulator. A simple explanation is that the continuous-time filter respond to an input signal continuously, unlike the SC filter in which an analog charge is supplied to the filter at a clock phase φ and the output analog voltage is ready at a clock phase φ. So a SC filter doesn’t see the variations of the input signal during the clock period φ and φ. On the other hand, form the linear system theory the output of a continuous-time filter is the result of convolution of the filter response with the input signal in the time interval t [∈ −∞ ∞ . , ]

4.2 The Impulse-Invariant Transform

A clock diagram of a continuous-time ΣΔ modulator is shown in Fig.4.1. Because of the presence of a sampler inside the loop (the quantizer is clocked, making for implicit sampling) the overall loop transfer function in a continuous-time modulator is really a discrete-time transfer function! In other words as shown in Fig. 4.2 the loop transfer function from the output of quantizer back to its input has an exact equivalent z-domain transfer function H(z). This doesn’t mean that the waveforms inside the loop are

Fig 4. 1 continuous-time ΔΣ modulator

Fig 4. 2 ΔΣ open loop block diagram

However, the sample values of the continuous-time waveform at the input of the quantizer at the sample times define an exact discrete-time impulse response for the continuous-time loop. In order to clarify this statement a examples of a second-order low-pass ΣΔ modulators with loop transfer functions of is given here briefly. The loop impulse responses of these discrete-time systems and their corresponding continuous-time counterparts are shown in Fig. 4.3.

Fig 4. 3 Open-loop impulse response of the second-order low-pass modulator As shown in these figures the open-loop impulse responses of the discrete-time loop filters match the samples of the impulse response of the continuous-time modulator loops. The continuous-time waveforms shown in Fig. 4.3 is actually the pulse responses of the continuous-time ΔΣ loop filter as depicted in Fig. 4.2. Detailed analysis of these

examples is given in next Sec. 4.3.

The loop behavior is completely determined by what the sampler inside the loop sees at its sample times, and that can be written as a difference equation. So, if a designer wants to analyze the performance of a continuous-time ΔΣ modulator (SNR and stability), he/she should first derive the equivalent z-domain transfer function for the ΔΣ loop. Then further analysis can be done in the z-domain as for traditional discrete-time modulators. Therefore the noise-shaping behavior of “continuous-time” ΔΣ loops can be designed entirely in the “discrete-time” domain and the exact same noise-shaping behavior obtained for either continuous-time or discrete-time systems.

4.3 NRZ Transformation

The ΔΣ modulator of Fig. 4.1 is shown again in Fig.4.4 in more detail. The loop filter is represented by ˆH s and the DAC transfer function by a zero-order-hold (ZOH) in ( )

which p is the opening aperture. The non-return-to-zero(NRZ) DAC p=T where T is a sampling period. Fig. 4.2 shows the ΔΣ signal path from the output of quantizer back to its input for a NRZ DAC.

Fig 4. 4 A continuous-time ΔΣ modulator in S-domain

As can be seen from Fig. 4.2 the overall ΔΣ loop gain is a discrete-time function, so one can derive the exact discrete-time transfer function, H(z), of the loop given the transfer functions of the continuous-time loop filter, ˆ ( )H s , and the ZOH as follows:

1

[

( )

]

1

1

l

( )

sp t nT

e

Z

H z

L

H s

s

− − − =

⎡

−

⎤

=

_⎢

_⎥

⎣

⎦

(4.1)

Equation (4.1) can be expressed in the time domain by

(4.2)

where Rp(t), the impulse response of ZOH, is a pulse with width of p as shown in Fig. 4.4,

 ( )

h t is the impulse response of the continuous-time loop filter, h(n) is the overall

has a pulse waveform, (4.1) and (4.2) are known as the pulse invariant transformation.

Consider the case where p=T corresponding to NRZ feedback pulse. Then the loop filter NRZ pulse response from (4.2) can be described as following:

(4.3)

For a continuous-time loop filter with single-poles described in residue form by

1

ˆ

ˆ ( )

N k k k

a

H s

s

s

=

=

−

∑

(4.4)

the impulse response would be

1

ˆ

( )

k

( )

N S t k k

h t

a e

u t

=

=

∑



(4.5)

Substitutingh t ( ) into (4.3), we have

(4.6)

Looking at samples of loop impulse response, h(t), at sampling times i.e. t=nT gives the discrete-time loop impulse response equivalent

(4.7)

The z-domain loop transfer function of the loop then can be derived from (4.7)

(4.8)

There are some interesting properties in the pulse invariant transformation given in

(4.6)-(4.8) which have to be addressed:

1) The first sample of the loop filter pulse response is zero (4.7). This is described by a delay factor which always exists in the numerator of the pulse invariant transformation function (4.8). This delay is related to the causality property associated with convolution of two ordinary signals which don’t contain any impulse function δ(t) component. That’s why, as will be seen in the transformation of any discrete-time ΔΣ loop filter to a

continuous-time equivalent, one delay is always absorbed in pulse transformation.

2) The overall continuous-time loop response (4.6) is described by different functions in the regions of 0 ≤ t < T and t ≥ T, where T is the sampling period. This has already been shown in Fig. 4.3 for second-order low-pass modulators. It should be noted that,

however, the overall loop response has continuity at T. The equivalent discrete-time loop filter (4.8) can be written as

1 1 1

( )

1

N k k k

a Z

H z

Z Z

− − =

=

−

∑

(4.9)

where the new residue is

1

ˆ

(1

S Tk

) cos

k k k

a

a

e

s

θ

−

=

−

−

(4.10)

and the new pole is at S Tk

k

Z

=

e

Note that (4.9) is the NRZ pulse transformation of (4.4) rewritten here

1

ˆ

ˆ

_{( )}

N k k k

a

H

S

S

s

=

=

−

∑

(4.11)

This has the properties one would expect: a pole at s = 0 transforms to one at z = 1, and a pole at s = j2π( fs / 4) transforms to one at z = j.

To actually do the transform, we proceed as follows. First, we write H z( ) as a partial fraction expansion. Then we choose a DAC pulse shape. We can assume a perfectly rectangular DAC pulse of magnitude 1 that from α to β. It can be shown as equation (4.11) and Figure 4.5. This covers most types of practical DAC pulse. Finally,

1, , 0 < 1 ˆ( , ) 0, otherwise. t r α β = ⎨⎧ α ≤ <β ≤α β ≤ ⎩ (4.11)

Fig 4. 5 The DAC pulse

We use Table 4.1 to convert each partial fraction pole from z to s. Then we will obtain the result of ˆH s . For example, if we use the DAC type, (α, β)=(0,1) in (4.11). And the ( ) transfer function is

(

)

2 2 1 ( ) 1 z H z z − + = − (4.12)

Table 4.1 s-domain equivalences for z-domain loop filter poles [12] z-domain pole Limit for z_k = 1

0 k y z−z 0 k r s−s , 0 0 y r β α = −

(

0

)

2 k y z−z

(

)

1 0 2 k r s r s s + − , 0 0 y r β α = −

(

)

0 1 2 1 2 y r α β β α + − = −

(

0

)

3 k y z−z

(

)

2 2 1 0 3 k r s r s r s s + + − , 0 0 y r β α = −

(

)

0 1 2 1 2 y r α β β α + − = − 0

(

)

(

)

2 1 9 9 4 12 12 y r β β α α αβ β α = ⎡_⎣ − + − + + ⎤_⎦ −

(

)

2 2 1 ( ) 1 ₁ H z z z − − = + − ₋ (4.13)

Applying the first row of Table 4.1, we obtain

2 2 2 1 0.5 1 1.5 ˆ ( ) s s H s s s s − − + − + = + = − (4.14)

Then we had transformed the H z to ˆ ( )( ) H s and obtain the new coefficients for continuous-time SDM.

4.3.1 Effect of Excess Loop Delay

Continuous-time SDM suffers a problem not seen in discrete-time design. That is the excess loop delay [13]. Excess loop delay arises because of nonzero delay between the quantizer clock edge and the time when a change in output bit is seen at the feedback point in the modulator. It arises because the nonzero switching time of the transistors in the feedback path. Its effect is severe if the sampling clock speed is an appreciable fraction of the maximum transistor switching speed.

S

T

τ

d

T

_S

Fig 4. 6 Illustrations of excess loop delay on NRZ DAC pulse

We assume that excess loop delay can be expressed as a fraction of the sampling period

S d dT

τ

=

ρ

(4.15)

T

f , the quantizer clock frequency f , and the number of transistors in the feedback path _S

t

n (as well as other things like the loading on each transistor). As a crude approximation, we could assume transistors switch fully at the maximum speed, i.e. after time 1/ f , in _T which case we could write

t S d T n f f

ρ

= (4.16) d

τ could end up being a significant fraction of T depending on the parameters in _S (4.16). This is particularly likely in GHz-speed modulators built in a process with an f _T of a few tens of GHz. For example , a OSR of about 50 and 5MHz bandwidth

Sigma-delta modulator ,which means we must clock at f =50(2*5)=500MHz. _S comparator output differential pair must switch. The DAC must also switch, and thus

t

n =2. In a f =10GHz process, therefore, _T 2 0.5 10%

10

d

ρ

=

⋅ = is the amount of excess delay predicted by (4.16).

We recall DAC pulses as rectangular with the form

1, , 0 < 1 ˆ( , ) 0, otherwise. t r α β = ⎨⎧ α≤ <β ≤α β≤ ⎩ in (4.11)

Suppose we have assumed that we have an NRZ DAC with (α β, ) = (0,1), and we have found the equivalent Hˆ( )s for a desired H(z) using Table 4.1 or MATLAB. If we use this filter in a system with delayed pulses as in Fig 4.6, then the system no longer has the same α and β. This means the equivalence between Hˆ( )s and H(z) is affected. Then we are going to understand the effect of excess loop delay of DAC. Suppose we are designing a CT double integration modulator, and we have NRZ DAC pulse, then we would have found Hˆ( )s to be Hˆ( ) 1 1.5₂ s

s

s = − + .suppose further that we have excess loop delay τ , so that in actuality we have NR DAC pulse delayed by τ as in figure

4.6. In that case, we have (α β, ) = (τ_d, τ_d+1). What is the equivalent H(z) for such an

ˆ_{( )}

Hs and DAC pulse?

The formulae in Table 4.1 only apply for a pulse with β ≤ 1, but once again, superposition comes to our rescue: it is possible to write a τ_d-delayed NRZ pulse as

(0, )

( ,1 )

( ,1)

ˆ

_{( )}

ˆ

ˆ

_{( 1)}

d d d

t

d τ

t

τ τ

+

τ

ϒ

=

ϒ

+

ϒ

−

_(4.17)

That is the linear combination of a DAC pulse from τ_d to 1 and a one-sample -delayed DAC pulse form 0 to τ_d as shown in figure 4.7.

Fig 4. 7 The delayed NRZ pulse as a linear combination Writing ˆH s in partial fractions gives ( )

2 1.5 1 ˆ ( ) H s s s − − = + (4.18)

Applying Table 4.1 to each term of (4.18), for each of the two DAC pulses in (4.17), yields 1 1.5(1 ) 1.5 1.5 1 1 d _z d s z z τ − τ − − − − → + − − (4.19) 2 2 2 2 ( 0.5 0.5 ) 0.5( 1 ) 1 ( 1) d d z d s z

τ

τ

τ

− + − + − + − _→ − 2 1 2 ( 1 0.5 ) 0.5 ( 1) d d z d z z τ τ τ − − + − + − (4.20)