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Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs

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IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 5, MAY 2009 529

Distinguishing Between STI Stress and Delta

Width in Gate Direct Tunneling Current

of Narrow n-MOSFETs

Chen-Yu Hsieh, Student Member, IEEE, Yi-Tang Lin, and Ming-Jer Chen, Senior Member, IEEE

Abstract—Direct tunneling current across a 1.27-nm-thick gate oxide of n-MOSFETs under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 µm). The apparent gate current per unit width ex-hibits an increasing trend with decreasingW . In this narrowing direction, two fundamentally different effects are encountered: one of the delta width(ΔW ) near the STI edge, and the other of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to domi-nate over the stress effect in narrow devices, while for the wide ones, they are comparable. The extracted ΔW (∼63 nm) and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are cooperative in constituting gate current variation, but both have opposite effects on the drain current one. Index Terms—Delta width, layout, mechanical stress, MOSFET, piezoresistance, shallow trench isolation (STI), tunneling.

I. INTRODUCTION

T

HE significance of the shallow-trench-isolation (STI)-induced mechanical stress in highly scaled MOSFETs has been widely recognized [1]. The linkage between layout design and the underlying STI stress has also been well con-structed [2]–[4]. Further applications pertaining to the layout dependences of the STI-stress-altered dopant diffusion [5], [6], gate direct tunneling [6], [7], threshold voltage [6]–[8], sub-threshold leakage [6], [8], and mobility [2], [4], [6], [7] have all been successfully demonstrated. However, care must be taken in the narrowing direction. The STI channel stress may be enhanced, but on the other hand, the delta width due to STI corner rounding is increasingly important. Thus, the ability to distinguish the delta width effect from the STI stress one is essential. Two such examples on drain current variation have recently been published [9], [10]. However, so far, effects on

Manuscript received October 7, 2008; revised January 31, 2009. First pub-lished March 31, 2009; current version pubpub-lished April 28, 2009. This work was supported by the National Science Council of Taiwan under Contract NSC 95-2221-E-009-295-MY3. The review of this letter was arranged by Editor K. De Meyer.

The authors are with the Department of Electronics Engineering, Na-tional Chiao Tung University, Hsinchu 300, Taiwan (e-mail: chenmj@faculty. nctu.edu.tw).

Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2009.2015471

Fig. 1. Schematically drawn cross-sectional view of the device in the channel width direction, which can be obtained from the existing simulated device structure in a state-of-the-art manufacturing process [3]. The effective channel width designatedWeffis the drawn widthW plus the delta width ΔW .

the gate direct tunneling counterpart were not yet addressed. Here, we elaborate on how to unambiguously elucidate the STI-stress-altered gate direct tunneling current in narrow devices.

II. EXPERIMENTALSETUP

Some 1.27-nm gate oxide n-channel MOSFETs on (001) wafer were fabricated in a state-of-the-art manufacturing process. In this process, STI-induced compressive stress was applied. The gate-edge-to-STI spacing in the source diffusion, the gate lengthL along the direction 110, and the gate-edge-to-STI spacing in the drain diffusion were all fixed at 0.5μm. The cross-sectional view of the test device is schematically shown in Fig. 1. The drawn gate width W spanned in a wide range of 0.11, 0.24, 0.6, 1.0, and 10 μm. The gate direct tunneling current was measured in inversion, with the source, drain, and substrate being tied to the ground. The change percentage of the apparent gate current per unit width, which is the actual gate current divided by corresponding W with respect toW = 10 μm, is plotted in Fig. 2 versus W .

III. DATAFITTING ANDPARAMETEREXTRACTION

As shown in Fig. 1, the actual channel width designatedWeff is the drawn gate width plus the delta width:Weff = W + ΔW . The corresponding stress-altered gate tunneling current density can be expressed as a linear function of both the average lon-gitudinal channel stressσxand the average transverse channel stressσy, which was obtained via a triangular potential-based

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530 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 5, MAY 2009

Fig. 2. Relative change of the apparent gate current per unit width atVg=

1 V versus drawn gate width. The lines represent the calculated results. For the narrowest caseW = 0.11 μm, the delta width effect contributes 56%, while the remaining percentage (5.5%) stems from the stress-induced SiO2/Si

barrier lowering. The combination of both effects produces a 65% change in the

apparent gate current density. For sufficiently largeW , however, both effects

become comparable. The inset shows the relative change of the apparent drain current per unit width atVd= 1 V and Vg= 1 V versus drawn gate width,

along with the calculated results. Note that the piezoresistance coefficients used are the typical bulk values, which are close to those of the inversion-layer ones of state-of-the-art strained n-MOSFETs [12], valid only for the channel110 direction on (001) wafer, as studied in this letter. ΔW = 63 nm,

σx= −132 MPa, and k = 160 MPa.

quantum simulation while incorporating the longitudinal and transverse stress dependences of the subbands [11]

Ig(σ) W +ΔW Ig(0) Wref+ΔW Ig(0) Wref+ΔW = axσx+ ayσy. (1) Here, the proportionality constants ax anday are both equal to−1.745 × 10−10 m2/Nt. The same proportionality constant value was also utilized in our previous work concerning the longitudinal channel stress [6], [7]. On the basis of the 2-D STI stress distributions [3], [10], a certain relationship can be found: σy= k log(W/Wref), where k is constant. Since only for sufficiently smallW can the gate current variation be significantly noticed, the transverse channel stress at reference

Wref(= 10 μm) can be reasonably ignored.

By substituting the aforementioned logarithm form into (1), a new analytic model for the apparent gate tunneling current change can be straightforwardly derived

ΔJg,app.(σ) Jg,app.(σref) = Ig(σ) W Ig(σref) Wref Ig(σref) Wref =1+axσx+ayk log W Wref 1+axσx W +ΔW Wref+ΔW Wref W −1. (2) Here, the reference stressσref corresponds to a fixed longitu-dinal stress under which the data were measured. First of all, according to the previous work [6], [7],σxunder the same gate-to-STI spacing (= 0.5μm) was estimated to be −132 MPa. Then, least squares fitting using (2) producedk = 160 MPa and ΔW = 63 nm. The fitting quality is excellent over W , as shown

Fig. 3. Comparison of (symbols) gate current data corresponding to Fig. 2 with the calculated results. ΔW = 63 nm, σx= −132 MPa, and with

k = 0−300 MPa.

in Fig. 2. The extracted ΔW is close to that of the existing simulated device structure (see [3, Fig. 5]). Therefore, in our work, the logarithmic form serves as a good approximation for

W down to 0.11 μm, which is comparable with that (0.15 μm

in the drain current fitting) of [10]. Further calculations were conducted for the two cases: 1) stress only, namely, (2) with ΔW = 0, and 2) delta width only or (2) with σx= 0 and k = 0.

The resulting delta width dominates over the stress in narrow devices, while for the wide ones, they are comparable. Note that both effects are cooperative in constituting gate current variation.

Obviously, ΔW is the principal factor. Thus, under the con-straint of ΔW = 63 nm, we performed additional calculations for different values ofk. The results are shown in Fig. 3. Here, the uncertainty range ofk between 70 and 200 MPa appears to deliver reasonable fitting. Moreover, we changedσxto those between−70 and −200 MPa; however, no noticeable change in the calculated gate current [directly from (2)] can be found (not shown here). Note that ifσxis much larger in magnitude than σy, (2) reduces to the case of delta width only. Further calculation was conducted concerning the possibility that the narrowing action may affectσx. The corresponding gate current change forσxatW = 0.11 μm relative to σx(= −132 MPa) atW = 10 μm is shown in Fig. 4. Fig. 4 reveals that the effect of varying σx due to the narrowing action on data fitting is considerably weak.

IV. CONFIRMATIVEEVIDENCE

The change percentage of the apparent drain current per unit width atVd= 1 V and Vg= 1 V is inserted to Fig. 2. The

exist-ing piezoresistance coefficients were cited for the fractional mobility change [12]: Δμ(σ)/μ(0) = πxσx+ πyσy, where

πx= 3.16 × 10−10andπy= 1.76 × 10−10 m2/Nt. The mea-sured threshold voltage shift was less than 5 mV, and therefore, the gate voltage minus the threshold voltageVth remains un-changed. Then, according to the long-channel saturation drain current expressionIdsat= μCinv(W + ΔW )(Vg− Vth)2/2L, whereCinvis the gate capacitance in inversion, another analytic model, which has the same expression as (2) but withaxand

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HSIEH et al.: DISTINGUISHING BETWEEN STI STRESS AND DELTA WIDTH IN DIRECT TUNNELING CURRENT 531

Fig. 4. Calculated gate and drain current change versusσx(from −70 to

−200 MPa) at W = 0.11 μm relative to the nominal σx(= −132 MPa)

at W = 10 μm. The formulas used are inserted. ΔW = 63 nm and

k = 160 MPa.

ay being replaced by πxandπy, respectively, can be created for the drain current variation. Although the mobility in near equilibrium may not be the same as that in the saturation regime of operation, the same piezoresistance coefficients can essen-tially apply to the relative mobility change due to the applied mechanical stress. This argument remains reasonable for the long-channel devices used in this letter. The calculated results agree with data, as shown in the inset of Fig. 2. Analogous to the gate current case, the measured drain current was separated into the delta width only and the channel stress only. However, these two distinct effects exhibit opposite trends. Again, the effect of varyingσxdue to the narrowing action appears to be weak, as shown in Fig. 4.

V. CONCLUSION

We have systematically examined the delta width and chan-nel stress effects on the gate direct tunchan-neling current of narrow n-MOSFETs under STI compressive stress. Both effects have been decoupled using a new analytic direct tunneling model.

The validity of the extracted transverse channel stress and delta width has been confirmed. The effect of varying longitudinal channel stress due to the narrowing action has been addressed. The corroborating evidence in terms of the drain current varia-tion has been presented.

REFERENCES

[1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., 1999, pp. 827–830.

[2] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electri-cal performance,” in IEDM Tech. Dig., 2002, pp. 117–120.

[3] Y. M. Sheu, C. S. Chang, H. C. Lin, S. S. Lin, C. H. Lee, C. C. Wu, M. J. Chen, and C. H. Diaz, “Impact of STI mechanical stress in highly scaled MOSFETs,” in Proc. Int. Symp. VLSI-TSA, 2003, pp. 76–79. [4] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki,

S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1254– 1261, Aug. 2004.

[5] Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30–38, Jan. 2005.

[6] C. Y. Hsieh and M. J. Chen, “Electrical measurement of local stress and lateral diffusion near source/drain extension corner of uniaxially stressed n-MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 844–849, Mar. 2008.

[7] C. Y. Hsieh and M. J. Chen, “Measurement of channel stress using gate di-rect tunneling current in uniaxially stressed nMOSFETs,” IEEE Electron

Device Lett., vol. 28, no. 9, pp. 818–820, Sep. 2007.

[8] C. Pacha, M. Bach, K. von Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, and R. Thewes, “Impact of STI-induced stress, inverse narrow width effect, and statisticalVTH variations on leakage

currents in 120 nm CMOS,” in Proc. Eur. Solid-State Device Res. Conf., 2004, pp. 397–400.

[9] P. B. Y. Tan, A. V. Kordesch, and O. Sidek, “Analysis of deep submicron CMOS transistor Vtlin and Idsat versus channel width,” in Proc.

Asia-Pacific Microw. Conf., 2005, pp. 1569–1572.

[10] R. Li, L. Yu, H. Xin, Y. Dong, K. Tao, and C. Wang, “A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependentIdsat,” Semicond. Sci. Technol., vol. 22, no. 12, pp. 1292–

1297, Nov. 2007.

[11] Y. T. Lin, “Strained silicon physics in nanoscale MOSFETs,” M.S. thesis, Nat. Chiao-Tung Univ., Hsinchu, Taiwan, 2008.

[12] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: Extending the CMOS roadmap,” IEEE Trans.

數據

Fig. 1. Schematically drawn cross-sectional view of the device in the channel width direction, which can be obtained from the existing simulated device structure in a state-of-the-art manufacturing process [3]
Fig. 3. Comparison of (symbols) gate current data corresponding to Fig. 2 with the calculated results
Fig. 4. Calculated gate and drain current change versus σ x (from −70 to

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