Performance comparison of titanium-oxide resistive switching memories using GeOx and AlOx capping layers for flexible application

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Performance comparison of titanium-oxide resistive switching memories using GeOx and

AlOx capping layers for flexible application

View the table of contents for this issue, or go to the journal homepage for more 2014 Jpn. J. Appl. Phys. 53 061502

(http://iopscience.iop.org/1347-4065/53/6/061502)

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Performance comparison of titanium-oxide resistive switching memories

using GeO

_x

and AlO

_x

capping layers for

ﬂexible application

Kun-I Chou1_{, Chun-Hu Cheng}2_{, and Albert Chin}1_*

1_{Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan, R.O.C.} 2_{Department of Mechatronic Technology, National Taiwan Normal University, Taipei 106, Taiwan, R.O.C.}

E-mail: [email protected]

Received January 4, 2014; accepted March 11, 2014; published online May 19, 2014

To meet the requirements ofﬂexible memory applications, we have compared two capping layers of GeOxand AlOxon a TiOyresistive random access memory (RRAM) at room temperature. A Ni/GeOx/TiOy/TaN RRAM shows a large resistance window of >102, 85 °C retention, a high-resistance-state (HRS) activation energy (Ea) of 0.52 eV, and a good DC cycling of 103cycles, which are signiﬁcantly better than those of a Ni/

1. Introduction

Flexible electronics are attractive for next-generation display technology. One challenge in the fabrication of flexible electronics is the lack of a nonvolatile memory (NVM) for system-on-chip (SoC) function. The conventional floating-gate or charge-trapping flash memory1,2) _{is difficult to}

integrate into ﬂexible substrates owing to the severely degraded gate oxide quality at low temperatures.3,4)

There-fore, several NVM types such as ferroelectric random-access memories (FeRAMs),4) _{magnetic random-access}

memories (MRAMs), and resistive random-access memories (RRAMs)5–17)are being investigated. RRAMs have attracted much attention for next-generation NVM applications owing to their simple structure, small cell size, and high speed. On the other hand, RRAMs have inherent merits of a lower-temperature process and a simpler structure for ﬂexible electronics applications.18–24) However, they require costly noble metal electrodes and poor resistance distribution. Such a poor distribution prevents further memory array realization, in sharp contrast to the existing sub-tera-bit ﬂash memory. To address these issues, we previously developed ultralow-power RRAMs6–8) _{to lessen the dielectric stress. The Ni/}

GeO_x/high-¬/TaN RRAMs show a negative temperature coefﬁcient (TC), opposite to other conductive-ﬁlament-type RRAMs owing to ion migration.

In this paper, we present a room-temperature Ni/GeOx/

TiO_y/TaN RRAM device with 0.28 µW set power, low 25 µW reset power, fast switching (10 µs) and a stable endurance in the 1000 cycling test. For comparison, we also investigate a room-temperature Ni/AlOx/TiOy/TaN RRAM device,

which has a similar switching power but markedly poor endurance and poor switching uniformity owing to the defect-rich AlO_x dielectric processed at room temperature. The present results demonstrate that the room-temperature Ni/GeOx/TiOy/TaN RRAM has high potential for future

ﬂexible memory applications. 2. Experimental procedure

The RRAM devices were fabricated on standard Si wafers. For VLSI backend integration, the process was started by depositing a 200-nm-thick SiO2 layer on the Si substrates.

Then, 100 nm TaN was prepared by physical vapor depo-sition (PVD). After patterning the bottom TaN electrode, a 15-nm-thick TiOy ﬁlm and a 6-nm-thick GeOx layer were

deposited at room temperature to form the stacked structure of GeO_x/TiO_y. Lastly, a 50-nm-thick Ni layer was deposited and patterned to form the top electrode with an area of 11300 µm2 _{in the RRAM device. For comparison, the Ni/}

AlO_x/TiO_y/TaN RRAM device was also fabricated with a 6-nm-thick AlO_xcapping layer on TiO_y. Here, Ni provides a low-cost solution for a high-work-function (5.1 eV) electrode, which has been implemented in high-¬ DRAM capacitors.25)

3. Results and discussion

Figure 1 shows the current–voltage (I–V) switching charac-teristics of Ni/GeOx/TiOy/TaN and Ni/AlOx/TiOy/TaN

RRAM devices on the SiO2 isolation layer. The

forming-free and self-compliance current switching characteristics are measured, which are vital for simplifying the circuit design without the need for a high-current forming process and extra current compliance. The low self-compliance set currents of 78 and 73 µA at 4 V and low reset currents of 2.3 and 5 µA at ¹5 V are measured in AlOx/TiOy and GeOx/TiOy RRAM

devices, respectively. The switching windows at a reading voltage of 0.5 V for AlO_x/TiO_y and GeO_x/TiO_y RRAM devices are 130© and 152©, respectively. From resistive I–V curves, these two RRAM devices show close switching high/low-resistance-state (HRS/LRS) currents and resistance windows. Although the AlO_x/TiO_y RRAM and GeO_x/TiO_y RRAM devices have similar switching characteristics, the AlOx/TiOyRRAM device shows poor endurance

character--5 -4 -3 -2 -1 0 1 2 3 4 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 3 2 ₁ 4 V_read=0.5V Abs.(I) (A) Voltage (V) Ni/GeO

x/TiOy/TaN RRAM

Ni/AlO

x/TiOy/TaN RRAM

Fig. 1. (Color online) SweptI–V curves of Ni/GeOx/TiOy/TaN and Ni/

AlO_x/TiO_y/TaN RRAM devices.

http://dx.doi.org/10.7567/JJAP.53.061502

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istics [Fig. 2(b)] in the 100 cycling test under set/reset conditions of 4 V/¹5 V. The degraded resistance windows after cycling 100 times are about 42% in the AlO_x/TiO_y RRAM device. The step like deteriorations at LRS may be caused by electron trapping near the Ni/AlOx interface,

which results in unstable switching behavior and window shrinking during continued cycling. Unlike the degraded memory window of the AlO_x/TiO_yRRAM device, the GeO_x/ TiO_yRRAM exhibits stable I–V switching at both HRS and LRS currents and large HRS/LRS ratio. In contrast to GeOx/

TiO_y, an unstable HRS current and a gradually reduced LRS current are obtained in AlO_x/TiO_yRRAMs, which indicates that the presence of defect centers in the AlO_x/TiO_ystack or near the electrode interface affects resistive switching char-acteristics. From the endurance results, it is demonstrated that the poor HRS/LRS switching behaviors during cycling are dominated by trap-controlled Frenkel–Poole (FP) conduction through trapping and detrapping effects.

To understand the low switching power, we have analyzed the current conduction mechanism, as shown in Fig. 3. We apply a negative voltage to the top Ni electrode for electron injection for us to measure and ﬁt I–V characteristics under HRS conditions. The good agreement between the measured and ﬁtting HRS currents suggests that the currents are conducted via the FP emission mechanism:

J / E exp ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q3_E=" p kBT ! : ð1Þ

Here,J is the current density; E, the applied electric ﬁeld; q, the elementary charge; ¾, the dynamic permittivity; kB,

Boltzmann’s constant; and T, the temperature. The increasing HRS current with increasing temperature is due to the high hopping emission rate, which increases FP conduction.26) _In

order to reach LRS, a positive voltage is applied to the top Ni electrode, where electrons were injected from the bottom TaN electrode. At a low electricﬁeld, LRS exhibits space-charge-limited current (SCLC) with trap control, since the slopes are proportional toV.

We have further conducted X-ray photoelectron spec-troscopy (XPS) to study the current conduction mechanism. To precisely analyze material bonding, the ﬁlm samples of TiOx, AlOx, and GeOxare pretreated by in situ Ar bombard-ment for 10 s under 6 to 8© 10¹8Torr to remove the native oxide on the sample surface. Figures 4(a) and 4(b) show the Ti 2p, and O 1s, and Ge 2p_3/2 and Al 2p XPS spectra, respectively. The nonstoichiometric TiO dielectric has dif-ferent titanium energy peaks such as Ti 2p_3/2 (Ti4+) and Ti 2p_3/2 (Ti3+), as shown in Fig. 4(a). The different Ti ion chemical states were measured in the TiO dielectric, indicating the formation of charged oxygen vacancies, which is favorable for resistance switching in RRAM devices under appropriate biasing conditions. In Fig. 4(b), the Ge 2p3/2

XPS spectrum reveals that the composition of the room-temperature-processed GeO dielectric is close to stoichio-metric. However, the Al 2p XPS spectrum shows three different binding energies corresponding to different valence bonds, namely, Al2O3 (Al3+= 74.5 eV),27) Al–Al bonds

(Al2+= 71.8 eV), and AlOx(72.5 eV) of the AlO dielectric. The different Al ion chemical states indicate the formation of charged oxygen vacancies and an oxygen-deﬁcient dielectric layer, which may lead to temperature-dependence leakage current even with a large bandgap.

Good uniformity is the fundamental challenge in the fabrication of RRAM devices for NVM array applications. Only few RRAM papers showed the cycle-to-cycle (C2C) distribution in the same device, rather than the NVM-array-required device-to-device (D2D) distribution among different devices.5–21) Figures 5(a) and 5(b) show the C2C and D2D current distributions of the GeO_x/TiO_y and AlO_x/TiO_y RRAM devices, respectively. Because of the different mean

10-9 10-8 10-7

Abs.(I) (A)

Number of Switching Cycles Ni/GeO x/TiOy/TaN SET: +4V RESET:-5V HRS LRS [email protected] (a) 0 200 400 600 800 1000 0 20 40 60 80 100 10-9 10-8 10-7 Abs.(I) (A)

Number of Switching Cycles Ni/AlO x/TiOy/TaN SET: +4V RESET:-5V HRS LRS [email protected] (b)

Fig. 2. (Color online) Endurance cycling of (a) Ni/GeO_x/TiO_y/TaN and (b) Ni/AlOx/TiOy/TaN RRAM devices.

-24 -22 -20 -18 -16 -14 -12 -10 1.2 0.9 0.6 0.3 0.1 1 10 -10 10-9 10-8 10-7 298K 313K 328K 343K 358K ln(I/V) V1/2_(V1/2₎ HRS SCLC Frenkel-Poole Conduction LRS IαV IαV2 Abs.(I)(A) Voltage (V)

Fig. 3. (Color online)I–V curves of the HRS and LRS of Ni/GeOx/TiOy/

TaN RRAM obtained byﬁtting with FP and space-charge-limited current mechanisms.

Jpn. J. Appl. Phys. 53, 061502 (2014) K.-I Chou et al.

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values, the coefﬁcient of variation (CV) was used to evaluate the distribution. The CV is a normalized measure of disper-sion of a probability distribution, deﬁned as the ratio of standard deviation (·) to mean value (®). The C2C current CVs of LRS for AlO_x/TiO_yand GeO_x/TiO_yRRAMs are 25 and 12%, whereas the C2C current CVs of HRS for AlO_x/ TiO_yand GeO_x/TiO_yRRAMs are 15 and 8.3%, respectively. In Fig. 5(a), the AlO_x/TiO_yRRAM shows poor current distri-bution in bulk-limited self-compliance LRS. The unstable resistance switching can be attributed to the defect-rich AlO_x capping layer that affects bulk vacancy control in LRS. Figure 5(b) shows the D2D current distributions of the GeO_x/TiO_yand AlO_x/TiO_yRRAMs. In HRS, the AlO_x/TiO_y RRAM shows the worse D2D distribution, resulting from the poor surface coverage uniformity of the defect-rich AlOx

layer. The only way to improve the poor HRS/LRS distribu-tions in AlO_x/TiO_y RRAM is oxygen annealing to remove defects, but high-temperature annealing is not allowed for ﬂexible electronics.

To study the conduction mechanism, we have measured the temperature-dependent current at LRS and HRS. The LRS activation energy (Ea) of 0.43 eV for GeOx/TiOyRRAM is

close to that of negative TC in highly defective Si governed by hopping conduction,28) which suggests LRS mechanism are related by hopping via defects in GeO_x/TiO_yRRAMs, as shown in Fig. 6(a). Such hopping conduction and negative TC were observed previously in GeO.29) Oxygen vacancies can be formed at a very low temperature, which degrade

GeO2/Ge MOSFETs,30)but they are very useful for RRAMs.

However, a much lower LRS activation energy (0.27 eV) is obtained for the AlO_x/TiO_y RRAM, where the HRS/LRS resistance change may be dominated by electron tunneling via shallow traps in the thin defect-rich AlO_xtunneling barrier.

Good retention and endurance are the essential character-istics for NVM. Figure 6(b) shows the retention of GeO_x/ TiO_yand AlO_x/TiO_y RRAM devices. From the results, the AlO_x/TiO_y RRAM shows a very poor data retention char-acteristic such that the memory window is closed after 104s at low 60 °C retention, compared wuth the GeO_x/TiO_y RRAM. Besides, the degraded HRS current at 60 °C retention can be attributed to theEain HRS (0.4 eV) being lower than

0.52 eV of the GeOx/TiOyRRAM device. This is because a high-temperature annealing for defect removal in the AlOx

dielectric is necessary. The electrons pile up near the Ni/AlOx

interface from the defect-rich AlO_xlayer, leading to window shrinking in LRS. In HRS, the defect-related current leakage from the defect-rich AlO_x layer leads to window shrinking during the high-temperature retention test. Although the Al2O3dielectric has a large bandgap of 8.8 eV, the defect-rich

AlO_x layer processed at room temperature still cannot be prevented from having a degraded HRS current owing to thermally assisted tunneling via a lowered Ni/AlOx barrier

under the high-temperature retention test. 4. Conclusions

The Ni/GeOx/TiOy/TaN RRAM provides good switching

10-9 10-8 10-7 0 20 40 60 80 100 120 AVG:5.2x10-10 STD:8x10-11 CV:15% AVG:2.3x10-8 STD:5.8x10-9 CV:25% AVG:4.8x10-8 STD:5.9x10-9 CV:12%

Ni/GeO_x/TiO_y/TaN RRAM

Ni/AlO_x/TiO_y/TaN RRAM

AVG:5.6x10-10 STD:4.7x10-11 CV:8.3% HRS Cumulative probability (%) Abs. I (A) LRS cycle-to-cycle (a) 10-9 10-8 10-7 0 20 40 60 80 100

120 Ni/GeOx/TiOy/TaN RRAMdevice-to-device

Ni/AlO_x/TiO_y/TaN RRAM

AVG:8x10-10 STD:3.4x10-10 CV:42% AVG:5.7x10-8 STD:1.9x10-8 CV:34% AVG:4.8x10-8 STD:1.7x10-8 CV:35% AVG:9.1x10-10 STD:2.9x10-10 CV:32% HRS Cumulative probability (%) Abs. I (A) LRS (b)

Fig. 5. (Color online) (a) C2C and (b) D2D current distributions of Ni/GeO_x/TiO_y/TaN and Ni/AlO_x/TiO_y/TaN RRAM devices.

0 1x104 2x104 3x104 4x104 5x104 Counts / s T i 2p1/2 (T iO 2 ) T i 2p1/2 (T i2 O3 ) T i 2p3/2 (T i2 O3 ) Counts / s

Binding energy (eV)

Ti 2p Scan T i 2p3/2 (T iO 2 ) 1x104 2x104 3x104 4x104 5x104 6x104 7x104 8x104 9x104 O 1s Scan O 1s (T i-O) O 1s (O-H,O=C) (a) 475 470 465 460 455 536 532 528 0 1x105 2x105 Ge 2p3/2 (Ge-Ge)

Binding energy (eV)

Ge 2p3/2 Scan Ge 2p3/2 (Ge-O) 1224 1216 80 75 70 0 1x104 AlO x Al 2p (Al-O) Counts / s Counts / s Al 2p Scan Al 2p (Al-Al) (b)

Fig. 4. (Color online) XPS spectra of (a) Ti 2p and O 1s, and (b) Ge 2p3 and Al 2p of Ni/GeO_x/TiO_y/TaN and Ni/AlO_x/TiO_y/TaN RRAM devices.

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characteristics with a low self-compliance set current of 73 µA at 4 V and a low reset current of 5 µA at¹5 V, a good switching window of 152©, and stable data retention at 85 °C for 104_{s. Such good RRAM performance characteristics}

compared with Ni/AlOx/TiOy/TaN are related to the

well-bonded GeO_x dielectric deposited by room-temperature fabrication using a very suitable room-temperature ﬂexible RRAM process. The room-temperature Ni/GeOx/TiOy/TaN

RRAM with such good characteristics shows great promise in futureﬂexible memory applications.

Acknowledgement

This work was supported by the National Science Council of Taiwan.

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30 32 34 36 38 10 12 14 16 18 20 22 24 26 28 Ni/GeO