Physics and characterization of various hot-carrier degradation modes in LDMOS by using a three-region charge-pumping technique

Abstract—Degradation of lateral diffused MOS transistors in

various hot-carrier stress modes is investigated. A novel

three-region charge-pumping technique is proposed to characterize

in-terface trap

(N

) and bulk oxide charge Q

creation in the

channel and in the drift regions separately. The growth rates

of

N

and

Q

are extracted from the proposed method. A

two-dimensional numerical device simulation is performed to gain

insight into device degradation characteristics in different stress

conditions. This paper shows that a maximum

I

stress causes the

largest drain current and subthreshold slope degradation because

of both

N

generation in the channel and

Q

creation in the

bird’s beak region. The impact of oxide trap property and location

on device electrical characteristics is analyzed from measurement

and simulation.

Index Terms—Hot-carrier degradation, lateral diffused MOS

(LDMOS), three-region charge pumping (CP).

I. I

I

N RECENT years, multifunction power integrated chips

are strongly demanded for the market of portable devices,

automotive applications, and display drivers [1]. The integrated

bipolar, CMOS, and DMOS (BCD) process has been developed

to realize complex single power ICs [2], [3]. Among the

candi-dates of high-voltage devices, lateral diffused MOS (LDMOS)

transistors are attractive because they can be easily integrated

with standard low-voltage CMOS process [1]–[4]. The LDMOS

has been widely used in today’s high-voltage and high-current

output circuits [4], from a standard 12-V automotive battery [5]

to 100-V plasma display panel drivers [6].

One of the major reliability issues in an LDMOS is

hot-carrier injection and trapping in the oxide [7]. Various

hot-carrier stress modes have been reported. Different stress

conditions result in oxide damage of different types (

N

and

Q

) and locations (channel or drift region). Moens et al.

reported that maximum

I

stress results in the worst

hot-carrier degradation for a gate oxide thickness from 7 nm [7]

Manuscript received April 21, 2006; revised July 19, 2006. This work was supported in part by Taiwan Semiconductor Manufacturing Company (TSMC) under TSMC-NCTU Joint Development Project and in part by the National Science Council, Taiwan, R.O.C., under Contract NSC94-2215-E009-009.

C.-C. Cheng, J. F. Lin, and T. Wang are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: twang@cc.nctu.edu.tw).

T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu are with Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TDMR.2006.883834

Fig. 1. (a) Cross section of an n-LDMOS and flatband (solid line) and threshold (dash line) voltage distributions. The device is divided into three parts, i.e., 1) Lchan (channel region), 2) Lacc (accumulation region), and

3)Lfox(field oxide region). (b) Illustration of a CP measurement waveform.

Vgh= 12 V is fixed, and Vglvaries from+3.6 to −40 V.

Fig. 2. Typical CP current in an n-LDMOS. The three stages of the CP current correspond to the three regions of the device. The flatband voltage of each region is indicated in the figure. The frequency in CP measurement is fixed at 200 kHz.

to 17 nm [8]. Their studies showed that gate oxide damage

occurs in the channel and in the accumulation regions. The

device characteristics degradation is attributed to interface trap

generation [7], [8]. Hefyene et al. [9] and Chen et al. [10]

claimed that maximum

I

stress has more serious degradation,

and again, interface trap generation is the cause of degradation

[9], [10]. Since LDMOS degradation is closely dependent on

trap type and location, the profiling of trap spatial distribution

Fig. 3. Substrate current and gate current versus gate voltage in an LDMOS. Three different stress modes are shown in the figure, i.e., 1) mode A (maximumIb), 2) mode B(Vg∼ (1/2)Vd), and 3) mode C (maximum Ig).

Fig. 4. (a) CP current versusVglbefore and after 1400-s mode A stress. (b) 2-D device simulation of IIG distribution in stress mode A.

and trap behavior is important to the understanding of the

impact of various hot-carrier stress modes.

In this paper, we demonstrate a novel three-region

charge-pumping (CP) technique to probe hot-carrier stress-induced

ox-ide damage in an LDMOS [11]. Each region of the CP current

corresponds to a different part of the device. By comparing

the prestress and poststress CP currents in each region, we are

able to identify the locations of oxide damage in the device

and corresponding trap properties. A two-dimensional (2-D)

device simulation is performed to identify an impact ionization

generation (IIG) region in the device. The dependence of device

degradation characteristic on trap position is also simulated.

II. T

-R

CP M

The n-LDMOS used in this work was processed in a

0.18-

µm CMOS technology with a gate oxide thickness of

100 nm and a field oxide thickness of 500 nm. The operation

voltages are

V

= 40 V and V

= 40 V. Fig. 1(a) shows the

device cross section. The device is divided into three regions.

Fig. 5. (a) CP current versusVglbefore and after 1400-s mode B stress. The shift of the flatband voltage in stage 2 implies the generation of negative oxide charge in the accumulation region. (b) 2-D device simulation of IIG in stress mode B.

Fig. 6. CP results in stress mode B for different stress times.

Region (I) is the channel region. Regions (II) and (III) are the

accumulation region and the field oxide region, respectively.

The length of each region is denoted by

L

(= 3 µm), L

,

and

L

, respectively. The gate width is 20

µm, and the

threshold voltage is 1.5 V. The device flatband voltage (

V

,

solid line) and threshold voltage (

V

, dash line) distributions of

the three regions are illustrated in Fig. 1(a). In the drift region,

the flatband voltage is higher than the threshold voltage because

of the n-type substrate.

The gate voltage waveform in CP measurement is illustrated

in Fig. 1(b) with a fixed

V

= 12 V and a variable V

. For

the 100-nm-thick gate oxide, we can switch

V

from

+3.6

to

−40 V without a significant gate oxide tunneling current.

In this

V

range, all the three regions of the device can be

probed. The measurement frequency is 200 kHz. Typical CP

measurement result is shown in Fig. 2. The CP current

(I

)

exhibits three stages, which correspond to the three regions

of an n-LDMOS. It should be noticed that each stage has

its corresponding threshold and flatband voltages. By

mea-suring the change of

I

and

V

after stress in each stage,

Fig. 7. Region (II) oxide-trapped charge growth rate in stress mode B.

Fig. 8. Linear drain current degradation(Idlin) rate measured at Vg/Vd=

40 V/0.1 V in stress mode B.

device [11], e.g.,

∆N

(channel) = ∆I

(stage 1)/qfW L

,

∆Q

(acc) = ∆V

(stage 2) · C/q, and so on.

Three hot-carrier stress modes, i.e.: 1) mode A (maximum

I

); 2) mode B

(V

∼ (1/2)V

); and 3) mode C (maximum I

),

are investigated. The

I

−V

and

I

−V

of an n-LDMOS are

shown in Fig. 3. The maximum

I

(mode A) stress is applied at

V

/V

= 8 V/50 V, whereas the maximum I

(mode C) stress

is applied at

V

/V

= 50 V/50 V. The bias conditions of the

three stress modes are also indicated in Fig. 3. For each stress

mode, the three-region CP method is performed to investigate

trap type (

N

or

Q

) and growth characteristics. Subthreshold

slope and linear drain current

(I

) are measured to monitor

device degradation.

III. R

D

A. Maximum

I

Stress Mode

Fig. 4(a) shows the

I

in a fresh device and after 1400-s

maximum

I

stress. The poststress

I

in the first stage is nearly

the same as the prestress one, indicating that region (I) oxide

is not damaged by the stress. The poststress

I

in stage 2,

however, exhibits an upward shift, while the flatband voltage

remains the same (no rightward shift in the

I

). This feature

suggests

N

generation in region (II) but no

Q

creation.

Numerical device simulation also shows the maximum IIG rate

in region (II) [Fig. 4(b)]. Although interface trap generation is

observed from the

I

, the subthreshold swing of the device

is not degraded because the generated

N

is distributed in

region (II) rather than in the channel region. In addition,

I

degradation is not observed either.

Fig. 9. (a) CP current before and after 1000-s mode C stress. Upward shift in first-stageIcpindicates interface trap generation in the channel, and rightward shift in second-stageIcpimplies oxide charge creation in the accumulation

region. (b) 2-D device simulation of IIG distribution in stress mode C. Two IIG regions are found: One is in the channel region, and the other is in the accumulation region.

Fig. 10. Subthreshold characteristics before and after mode C stress. The swing degradation is attributed to interface trap generation in the channel region.

Fig. 11. The linear drain current versusVgbefore and after mode C stress.

B.

V

∼ (1/2) V

Stress Mode

The

I

results before and after mode B stress (at

V

/V

=

30 V/50 V) are shown in Fig. 5(a).

N

generation in stress

Fig. 12. Simulated drain current versus gate voltage without and with oxide charges. (a) Oxide charge is placed in the channel. (b) Oxide charge is placed in the bird’s beak region.

Fig. 13. Region (I) interface trap growth rate in stress mode C.

Fig. 14. Region (II) oxide charge growth rate in stress mode C.

substrate current [and a smaller IIG region in Fig. 5(b)], as

com-pared to stress mode A. Unlike stress mode A, a distinct

flat-band voltage shift in region (II) is noticed, which is manifested

by a rightward shift of the

I

in stage 2. An arrow is drawn

in Fig. 5(a) to indicate the flatband voltage shift

(∆V

).

The rightward shift of the slope is caused by negative

Q

creation in region (II). Fig. 6 shows the evolution of the

I

with

Fig. 15. Idlindegradation versus stress time in stress mode C. The degrada-tion is mainly caused by negative oxide creadegrada-tion in the drift region.

TABLE I

SUMMARY OFMAJOROXIDE ANDDEVICEPERFORMANCE

DEGRADATIONS INVARIOUSSTRESSMODES

stress time. As stress time increases, the flatband voltage of the

region (II) continuously shifts to the right. The

Q

generation

rate (Fig. 7) can be extracted from the

∆V

versus stress

time by using the equation in Section II. Because of negative

Q

creation, the resistance beneath the bird’s beak increases.

At a large

V

, region (I) resistance is relatively small, and the

resistance in the bird’s beak region occupies a larger part of the

total resistance. Thus,

I

degradation is observable at a higher

measurement

V

= 40 V (Fig. 8). Numerical simulation for the

dependence of

I

degradation on trap location will be given

later.

C. Maximum

I

Stress Mode

Fig. 9(a) shows the

I

result before and after maximum

I

stress for 1000 s. Two different stress-induced oxide

degra-dation mechanisms are noticed: One is

N

generation in

region (I), and the other is negative

Q

creation in region (II).

These two trap creation processes are reflected by an upward

shift of the first-stage

I

denoted by

∆I

and by a rightward

shift of the second-stage

I

[

∆V

in Fig. 9(a)]. In contrast

to stress mode A, a 2-D device simulation reveals that the IIG

region in maximum

I

stress splits into two parts [Fig. 9(b)]:

One is in the channel [region (I)], and the other is underneath

the bird’s beak. The

N

generation in region (I) results in a

significant subthreshold swing degradation (Fig. 10) in stress

mode C. In addition,

Q

creation accounts for a serious

I

degradation (Fig. 11) in mode C. Fig. 11 shows that the

I

degradation is more apparent at a larger

V

. To explain the

V

dependence, a 2-D device simulation is performed. We

calcu-late the

I

versus

V

by placing the same amount of fixed

oxide charge

(Q

/q = 10

/cm

) in the channel [Fig. 12(a)]

and in the bird’s beak region [Fig. 12(b)]. Fig. 12(a) shows a

larger

I

degradation at a low

V

, whereas Fig. 12(b) shows a

has the worst

I

degradation. Due to oxide charge creation

in region (II), region (II) resistance increases, and the current

flow in region (II) is pushed deeper. Consequently, the electron

mobility exhibits a saturated effect, and thus,

I

degradation

has a tendency to saturate in Fig. 15. This mobility saturation

model is also described in [13] and [14] for MOSFET and in

[8] for LDMOS structure. The LDMOS degradation behavior

and trap properties in the three stress modes are summarized

in Table I.

IV. C

A novel three-region CP technique has been developed to

characterize hot-carrier stress-induced oxide degradation in

each region of an n-LDMOS. The trap location and property

in various stress modes are identified, and their impact on

device characteristics has been analyzed. A correlation between

device degradation and CP and device simulation results has

been established. Our study reveals that the device subthreshold

swing degradation is mainly affected by interface traps in the

channel region, whereas the linear drain current degradation is

dictated by oxide-trapped charge in the drift region. Our study

also shows that maximum

I

stress results in the worst

hot-carrier degradation in an LDMOS, which is attributed to both

N

generation in the channel region and

Q

generation in the

bird’s beak region.

R

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Chih-Chang Cheng (S’04) was born in Yi-Lan,

Taiwan, R.O.C., in 1980. He received the B.S. de-gree in physics from National Central University, Nanjing, Taiwan, R.O.C, in 2002. He is currently working toward the Ph.D. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.

His research interest includes high-voltage power device reliability and SPICE modeling.

J. F. Lin received the B.S. degree in electrophysics

from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2005. He is currently working toward the M.S. degree at the same university.

His research interest includes high-voltage power devices and flicker noise.

Tahui Wang (S’84–M’85–SM’94) was born in

Taoyuan, Taiwan, R.O.C., on May 3, 1958. He re-ceived the B.S.E.E. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980 and the Ph.D. degree in electrical engineering from the Uni-versity of Illinois, Urbana-Champaign, in 1985.

From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., where he is currently a Professor. His research interests include hot-carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices, and nonvolatile semiconductor devices.

Dr. Wang has served as a Technical Committee Member of many inter-national conferences, among them IEDM, IRPS, and VLSI-TSA. He was a recipient of the Best Teacher Award from Taiwan’s Ministry of Education.

T. H. Hsieh received the B.S. and M.S. degrees

in electrical engineering from National Tsing-Hua University, Taipei, Taiwan, R.O.C., in 1986 and 1988, respectively, and the Ph.D. degree in electrical engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1995.

From 1995 to 1999, he was with Vanguard In-ternational Development. In 2000, he joined Taiwan Semiconductor Manufacturing Company, Hsinchu, where he worked on SOI and 90-nm device process development. He is currently the Department Man-ager of the Product Device and SPICE Engineering Department, where he is responsible for the production yield and performance enhancement of device and SPICE engineering.

J. T. Tzeng received the B.S. and M.S. degrees in electrical engineering from

National Cheng-Kung University, Tainan, Taiwan, R.O.C., in 1995 and 1997, respectively.

He has been with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C, since 1999.

Y. C. Jong received the M.S. degree in physics from National Taiwan

Univer-sity, Taipei, Taiwan, R.O.C., in 1997.

He has been with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C., since 1999. His major focus includes nonvolatile memory process integration (1999–2003) and HV power CMOS process integration (2003–2005).

R. S. Liou received the B.S.E.E. degree from National Cheng-Kung University,

Tainan, Taiwan, R.O.C., in 1988.

He has been with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C., since 1990. His major focus includes Si/SiGe BiCMOS process integration (2000–2002) and HV power CMOS process integration (2002–2005).

Samuel C. Pan (S’83–M’87) received the B.S.

de-gree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980 and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois, Urbana-Champaign, in 1984 and 1986, respectively.

From 1983 to 1986, he was a Research Assistant with the Solid State Electronics Laboratory, Uni-versity of Illinois, Urbana-Champaign. In 1987, he joined Intel Corporation as a Senior Device Physicist and worked on 0.8-µm Flash EPROM development and 0.6-µm CMOS process development. In 1995, he became Staff Circuit Designer and worked on 0.25-µm Pentium/Pro microprocessor with the focus on cache memory and PLA design. At the end of 1996, he moved back to Taiwan and joined Macronix International Co., Ltd., as Quality and Reliability Deputy Director. In 1999, he was named Technical Director to lead process development for 0.18- to 0.15-µm Flash and mask ROM memory technologies. In June 2003, he joined Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C., as the Director of Advanced Product Engineering. His current interests include device physics, device/Flash cell reliability, failure analysis techniques, and methodologies for technology development and yield enhancement.

Dr. Pan is a member of Phi Kappa Phi and Eta Kappa Nu.

S. L. Hsu received the M.S. degree in material

science and engineering from National Cheng Kung University, Taiwan, R.O.C., in 1984 and the Ph.D. degree in electrical engineering from National Chiao Tung University, Taiwan, in 1994.

In the last three years, he was Fab-1 and Fab-2 Director of Taiwan Semiconductor Manufacturing Company (TSMC) and led Flip-Chip Division. He is currently Director of Fab-2 and High-Voltage Pro-gram at TSMC, Hsinchu, Taiwan.