A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback
matching network
Fadi Riad Shahroury, Chung-Yu Wu
Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
a r t i c l e
i n f o
Keywords:
Low-noise amplifier (LNA) Noise optimization Low voltage RF
a b s t r a c t
In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0:18-mm1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFminof 4.46 dB. The reverse isolation S12 of the LNA can achieve
40 dB and the input and output return losses are better than 11 dB. The input 1-dB compression point is 11 dB m and IIP3 is 0:5 dB m. This LNA drains 10 mA from the supply voltage of 1 V.
&2008 Published by Elsevier B.V.
1. Introduction
Over the last two decades, the rapid growth of portable wireless communication systems, such as cellular phones, global positioning satellites (GPS), bluetooth, wireless local area network (WLAN), ultra-wideband (UWB), etc., has greatly increased demand for high performance and low cost radio frequency (RF) receivers. This has driven recent effort to implement RF receivers in advanced CMOS technologies in order to increase integration level, reduce power consumption, and reduce chip area. To achieve the above design goals, it is important to design suitable low voltage and low power analog front-end in RF receivers. In the RF receiver front-end design, the low-noise amplifiers (LNAs) play a crucial role since the whole system-sensitivity is mainly determined by the noise figure of the LNA.
In the design of RF-CMOS LNAs, it is known that the key performance parameters are power-gain and noise figure (NF) besides the stability, linearity and isolation. The goal of LNA design is to achieve maximum power-gain and minimum NF simulta-neously at any given amount of power dissipation. To reach this goal, the input impedance Zinof a LNA must be kept close enough to the optimum source noise conjugate impedance Z
n;opt. Conventionally, the inductive source-degeneration technique is used to achieve this goal[1]. However, this inevitably decreases the equivalent transconductance of the LNA at high frequencies, which reduces the power-gain [2]. To retain the power-gain, the power dissipation has to be increased significantly. For the LNAs operated above 10 GHz, an accurate and small
source-degeneration inductor value is required. The variations of the inductance make Zin not close enough to Zn;opt. To realize the accurate and small source-degeneration inductance, microstrip line can be used at frequencies higher than 20 GHz. But it is chip area consuming if being used at frequencies below 20 GHz.
So far, many high-frequency RF-CMOS LNAs have been proposed[3–7]. Among them, the proposed LNA structure at 17 and 24 GHz [3] uses microstrip line to realize accurate source-degeneration inductor. However, the chip area is still large. The multistage common-source amplifiers are used in the LNAs in [4–6]. Each stage is designed with inductive source degeneration. To reach sufficient gain and good stability at frequencies from 8 GHz to Ku-band, high power dissipation is needed [4–6]. Although power-gain match can be achieved by utilizing the inputmicrostrip line in the LNA design[7], Zinis not equal to Zn;opt in this case. Thus the minimum NF and maximum power-gain cannot be achieved simultaneously.
The approach described in this work relies on the introduction of a new LNA design technique, which uses the gate-drain capacitance and output capacitance of the input MOSFET to form the capacitive feedback matching network and bring the input impedance Zin close to the optimum source noise conjugate impedance Z
n;opt. The current of the input MOSFET is then amplified by a RF current-mirror amplifier. It is shown that the proposed LNA has a high power-gain of 13.2 dB, a high reverse isolation of 40 dB, and a good linearity with the input 1-dB compression point at 11 dB m and IIP3 is 0:5 dB m. The NF and NFminof the proposed LNA are 4.56 dB and 4.46 dB, respectively. Therefore, the LNA has good noise performance because NF and NFmin are very close to each other. Besides, the proposed LNA has a small power consumption of 10 mW under the low power supply voltage of 1 V.
The proposed input matching method is discussed in Section 2 and its effect on the noise figure (NF) is presented in Section 3. The
0167-9260/$ - see front matter & 2008 Published by Elsevier B.V. doi:10.1016/j.vlsi.2008.09.007
Corresponding author.
E-mail addresses:[email protected] (F.R. Shahroury), [email protected] (C.-Y. Wu).
details of the designed CMOS circuit of the LNA are presented in Section 4. While in Section 5, it describes the experimental results. Finally, the conclusion is given in Section 6.
2. Proposed input matching method
The input impedance of the LNA is designed to match with the antenna, in order to prevent the incoming signal from reflecting back and forth between the LNA and the antenna. Generally, the antenna has 50-
O
load to the LNA. Unfortunately, the input impedance of a MOSFET device is inherently capacitive, so the matching with 50-O
resistive input impedance is not an easy task. Thus, a capacitive feedback matching technique is proposed to overcome this problem[8].The common-source amplifier as the input stage is shown in Fig. 1, where Zsis the impedance seen from the right node of the input matching inductor Lg, Zinis the input impedance of M1, Cgd is the gate-drain capacitance, Cgsis the gate-source capacitance, Cout is the output loading capacitance which is the input capacitance of the next stage, Rs is the signal-source resistance, and Vsis the input signal voltage source. By using Millers theorem on Cgd, the input impedance Zincan be derived as
Zin¼ Rf ðQ2f þ1Þ þ 1 j
o
oðCgsþCgdÞ 1 Q2 f þ1 ! , (1) where Qf¼o
oðCgsþCgdÞRf, (2) Rf¼ 1 gm Cout Cgd , (3)gmis the transconductance of M1, and
o
ois the operating angular frequency. As it can be seen from the above equations, both Cgd and Cout with gm together providing a real term Rf which contributes to the real input impedance in Zin. They are called the capacitive feedback matching network.3. The noise analysis of the proposed input matching method In the LNA design, input power match is essential but not sufficient. It is also vital for a LNA to satisfy the noise performance requirement, so that the circuit itself does not degrade the output signal-to-noise ratio (SNR) to an unacceptable level. Thus, a careful noise analysis on the capacitive feedback matching technique is developed to establish the principle of operation clearly and find the limits on noise performance. A brief review of the standard CMOS noise sources will facilitate the analysis.
3.1. Noise sources
Fig. 2 shows the small-signal model of the equivalent circuit for the noise analysis. Three noise sources have been considered in Fig. 2. They are the thermal noise of the source resistance in;Rs, the
thermal noise of the channel current in;d, and the gate induced current noise in;g. They can be expressed as[9]
i2n;Rs¼4kT 1 Rs
D
f , (4) i2n;d¼4kTg
gd0D
f , (5) i2n;g¼4kTd
o
2C2 gs 5gd0D
f , (6)where k is Boltzmann’s constant, T is the absolute temperature, Rs is the source resistance, gd0is the zero-bias drain conductance,
g
is the thermal noise coefficient,D
f is the noise bandwidth in hertz, andd
is the gate induced current noise factor.According to [9], there is a correlation between the gate induced current noise in;g and the thermal noise of the channel current in;d. This correlation can be treated by separating in;ginto two parts. in;gcis the part that fully correlated with thermal noise of the channel current in;d, whereas in;gu is the uncorrelated part. Hence, the gate induced current noise can be written as
i2n;g¼4kT
d
o
2C2 gs 5gd0 ð1 jcj2ÞD
f |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} in;gu þ4kTd
o
2C2 gs 5gd0 jcj2D
f |fflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} in;gc , (7)where the correlation coefficient c is defined as[9] jc ¼ in;gi n;d ffiffiffiffiffiffiffiffiffiffiffiffiffi i2n;gi 2 n;d q . (8)
Because of the correlation, special attention must be paid to the reference polarity of the correlated component. The value of c is positive for the polarity shown inFig. 2.
3.2. Capacitive feedback matching network noise analysis
Noise performance is usually evaluated with noise figure (NF) which indicates the noise suppression ability of the circuit. Noise figure is defined as
NF ¼ 10 logðFÞ, (9)
where F is the noise factor which is defined as the total output noise power divided by the noise power at the output due to the input source. F can be expressed as
F ¼i 2 n;o;tot: i2n;o;Rs ¼i 2 n;o;Rsþi 2 n;o;gþd i2n;o;Rs , (10)
where i2n;o;tot: is the mean-squared of the total output noise current, i2n;o;Rs is the mean-squared output noise current due to
Fig. 1. The common-source amplifier as the input stage.
F ¼A 2 i2n;dþ2ReðAB c ffiffiffiffiffiffiffiffiffiffiffiffiffi i2n;gi 2 n;d q Þ þB2i2 n;gu D2i2n;Rs , (12) where A ¼in;o;d in;d ¼1, (13) B ¼in;o;g in;g ¼ RSþSLg RsþSLgþZin Zingm, (14) D ¼in;o;Rs in;Rs ¼ RS RsþSLgþZin Zingm. (15)
Finally, the noise factor for a capacitive feedback matching network is obtained from Eqs. (12)–(13) as
F ¼ 1 þ
g
a
1 gm;Rs jcja
ffiffiffiffiffiffid
5g
s !2 8 < : þ ðR2ss 2 L2gÞ 1 R2fa
2d
5g
ð1 jcj 2 Þs2C2t ! ðsCtRsÞ2 1 þ jcja
ffiffiffiffiffiffid
5g
s " #2 þ2Rs Rf 9 = ;, (16)where Ct¼CgsþCgdand
a
gm=gd0. By taking the derivatives of (16) with respect to Rsand Lgand let the derivatives equal to zero, optimum source noise impedance, Zn;opt¼Rsn;optþjo
Lgn;opt,corre-sponding to minimum noise figure can be written as
Zn;opt¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
a
2d
5g
ð1 jcj 2Þ þ 1 Q2f s þj 1 þa
jcj ffiffiffiffiffiffid
5g
s !a
2d
5g
ð1 jcj 2Þ þ 1 Q2f þ 1 þa
jcj ffiffiffiffiffiffid
5g
s !2 8 < : 9 = ; 1o
ðCgsþCgdÞ . (17)Using (1), (17) can be re-expressed in Z n;optas Z
n;opt¼Re½Zn;opt þ
Z
Imag½Zin, (18)Z
¼ 1 þ 1 Q2f ! 1 þa
jcj ffiffiffiffiffiffid
5g
s !a
2d
5g
ð1 jcj 2Þ þ 1 Q2f þ 1 þa
jcj ffiffiffiffiffiffid
5g
s !2 8 < : 9 = ; . (19)From (18), the imaginary part of Z
n;optis nearly the same as the imaginary part of Zinand expressed as
Z
Imag½Zin.For the circuit in Fig. 1, the condition for maximum input power transfer (thus power-gain) is Zin¼Zs and that for the minimum noise figure is Zs¼Zn;opt. Ideally, we have the condition for maximum power-gain and minimum noise figure is Zin¼Zn;opt. From (1), Eqs. (17) and (18), this condition can be
satisfied by designing suitable device parameters gm, Cgd, and Cgs of the device M1, which are related to gate-source voltage Vgsand transistor size W=L. In other words, the proposed design technique and input stage inFig. 1help to maximize the power-gain and to minimize the noise figure simultaneously by bringing Zinclose to the optimum source noise conjugate impedance Zn;opt. It can be seen from (1) that without the feedback gate-drain capacitance Cgd, the input impedance of the common-source amplifier would have no real part. However, the optimum source noise impedance Zn;optin (17) has a real part. Then it is impossible to satisfy the condition Zin¼Zn;opt. In the proposed technique, Cgd and the capacitive feedback matching network are used to satisfy the condition. Thus the technique is called the technique of capacitive feedback matching network.
4. Circuit implementations
The complete circuit of the proposed LNA with the output stage is shown in Fig. 3 where in the LNA stage, M1 with the input amplifier transistor and M2/M3 form the current-mirror amplifier as the second amplifier stage. The effective transconductance of the two stages is given by
jGeffj ¼ 1 2Rs
o
To
o gm3o
oCout ¼ 1 2Rso
To
o 2x
, (21)where
o
Tis unit gain angular frequency, gm3is the transconduc-tance of M3, Coutis the total capacitance at the drain of M1 which is dominated by Cgs of M3, andx
is a constant approximately equal to 1 under the condition of Coutapproaching Cgsof M3. So using coupling capacitor between M1 and M3 to isolate the bias levels results in serious degradation on the gain due to the parasitic capacitance of the bottom-plate of coupling capacitor. For this reason, M2 is used as the master transistor of the MOSFET current-mirror amplifier along with the slave transistor M3. The size of M2 is chosen to be very small as compared to M1 and M3 to obtain a higher current gain. Moreover, from Hspice noise simulation results, M2 contributes less than 1.5% of over all LNA noise figure. Since the cascode structure is not adopted, the proposed LNA can be operated at a low supply voltage.In order to make the parallel resonance circuit behave like a capacitive load, a parallel resonance circuit composed of L2 and the parasitic capacitance at the drain of M1 resonates at the
frequency below the operating frequency of the LNA. R1 is used to ensure stability. C1 and C2 are dc blocking capacitors. The tank L3 and C3 is used to resonate with the parasitic capacitances of the gate M4. R2 is used to provide the gate dc bias of M1 and chosen large enough that its equivalent noise current is small enough to be ignored.
In the output stage, the output buffer composed of M4, L4, C4, and R3, is designed for the measurement purpose. R3 is used to provide the gate dc bias of M4, C2 and C4 is the dc blocking capacitor. The output inductor L4 is used to resonate with the parasitic capacitances at the drain of M4. The voltage gain of the buffer is unity.
Form (19) and under the condition of the short channel devices, the expected noise parameters of device are
a
¼0:6,d
=g
¼2, jcj ¼ 0:5 and Qf¼2. In the proposed LNA, theZ
is 0.87, while theZ
of the LNA with source degenerative method is equal to 0.82.It is important to notice that some amount of mismatch in the input matching Zin¼Zs has negligible effect on the LNA performance, while the mismatch in Zs¼Zn;optdirectly affects the NF[10]. Thus Re½Zinis designed to be equal to the calculated Rsn;opt. Fig. 4. The measured and simulated S11and S21results of the proposed LNA.
Fig. 5. The measured and simulated S22and S12results of the proposed LNA.
Fig. 6. The measured and simulated noise figure NF and minimum noise figure NFminof the proposed LNA.
Fig. 7. The LNA measurement results of Pinversus Pout.
fabricated LNA circuit was tested through on-wafer probing technique. The measured and simulated S21 and input return loss S11 are shown inFig. 4. InFig. 4the measured S21 is 13.2 dB at 12.8 GHz. The measured and simulated output return loss S22 and reverse isolation S12 are shown inFig. 5. As can be seen from Figs. 4 and 5, the measured reverse isolation S12 of the LNA achieves 40 dB whereas the input and output return losses are
large frequency range. Thus the proposed LNA is insensitive for operating frequency variations. The measured output power versus the input power is shown in Fig. 7 where the input referred 1-dB compression gain is 11 dB m. The measured two-tone test results are shown inFig. 8. InFig. 8the measured IIP3 is 0:5 dB m.
The measured performance parameters are summarized in Table 1where comparisons with other published works are also listed.
In order to compare the performance of our LNA design, three different figures of merit FOMs previously presented in literature have been considered herein. In detail, FOM1 is defined as the ratio between the power-gain (S21) in dB and the power consumption in Watt. FOM2 is defined to include the NF of the LNA. FOM3 takes into account the IIP3 and the operating frequency fcas well. They can be written as[11]
FOM1 ¼ S21 PDC 103 , (22) FOM2 ¼ 10 S21=10 ½10NF=101 PDC 103 , (23) FOM3 ¼ ½10ðS21þIIP3Þ=10 fc 109 ½10NF=101 PDC 103 . (24)
Based uponTable 1, it is clear that the proposed LNA outper-forms all the other LNAs with a higher value of FOM. As expected, the proposed LNA with the technique of capacitive feedback matching network has high power-gain and low-noise figure under low power dissipation. It can be operated at a low supply voltage of 1 V since the cascode structure is not adopted. However, it still has a high reverse isolation.
Fig. 9. The chip photograph of the proposed LNA.
Table 1
The measured performance parameters of the fabricated LNA and comparisons with other published LNAs
This work [5] [6] [6] [7]
Tech. 0:18mm 0:18mm 0:18mm 0:18mm 90 nm
CMOS CMOS CMOS CMOS CMOS
Topology of input matching
Capacitive feedback Source-degeneration inductor Microstrip line
Freq. (GHz) 12.8 14 8 9 20 Gain (dB) 13.2 10.71 13.5 12.2 5.8 NF (dB) 4.57 3.16 3.2 3.7 6.4 IIP3 (dB m) 0.5 1.6 3.2a 1.3a 5.2 Power (mW) 10 28.6 22.4 19.6 10 Supply (V) 1 1.3 1 1 1.5 S11 (dB) 11 10 5.8 5.4 – Chip size (mm2) 0:746 0:885 0:88 0:77 – 1 0:9 0:7 0:8 FOM1 1.32 0.374 0.6 0.622 0.58 FOM2 1.12 0.383 0.92 0.63 0.11 FOM3 12.8 7.2 3.5 4.2 7.4 a
6. Conclusion
A new LNA structure with the technique of capacitive feedback matching network is proposed and analyzed. An experimental chip of 13-GHz LNA has been successfully designed and fabricated. The measurement results have shown that the proposed LNA can achieve minimum noise figure and maximum power-gain simultaneously. In additions, the NF is insensitive to the large operating frequency shift.
Future research will be conducted on the design of LNAs at frequencies of 24-GHz or below using the technique of capacitive feedback matching network. Besides, the integration of LNA with mixers to form receivers will be performed.
Acknowledgments
This work was supported by the National Science Council (NSC), Taiwan, under the Grant NSC-95-2221-E-009-292. The authors would like to thank the National Chip Implementation Center (CIC), National Applied Research Laboratories, Taiwan, for the fabrication of testing chip. The authors would also like to thank the support of CAD tools HFSS from Ansoft Taiwan. References
[1] R.E. Lehmann, D.D. Heston, X-band monolithic series feedback LNA, IEEE Trans. 32 (1985) 2729–2735.
[2] F. Ellinger, 26–42 GHz SOI CMOS low noise amplifier, IEEE Solid-State Circuits 39 (2004) 2259–2268.
[3] L.M. Franca-Neto, B.A. Bloechel, K. Soumyanath, 17 GHz and 24 GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18/spl mu/m logic CMOS technology, in: Proceedings of the 2003. ESSCIRC ’03, September 2003, pp. 149–152.
[4] X. Guan, A. Hajimiri, A 24-GHz CMOS front-end, IEEE Solid-State Circuits (2004) 368–373.
[5] K.L. Deng, et al., A Ku-band CMOS low-noise amplifier, in: Proceedings of the RFIT, November 2005, pp. 183–186.
[6] T.K.K. Tsang, M.N. El-Gamal, Gain controllable very low voltage (1 V) 8–9 GHz integrated CMOS LNAs, in: Proceedings of the RFIC, June 2002, pp. 205–208. [7] M.A. Masud, et al., 90 nm CMOS MMIC amplifier, in: Proceedings of the RFIC,
June 2004, pp. 201–204.
[8] R. Fadi Shahroury, C.Y. Wu, CMOS LNA design using capacitive feedback matching network, in: Proceedings of the IPS, July 2006, pp. 101–103.
[9] A. Van der Ziel, Noise in Solid State Device and Circuits, Wiley, New York, 1990.
[10] T.K. Nguyen, et al., CMOS low-noise amplifier design optimization techniques, IEEE Trans. Microwave Theory Tech. 52 (5) (2004) 1433–1442.
[11] R. Brederlow, et al., A mixed-signal design roadmap, IEEE Des. Test Comput. 18 (6) (2001) 34–36.
Fadi R. Shahroury was born in 1977. He received the B.Eng. (with the highest distinction) degree in Electro-nics Engineering from Princess Sumaya University for Technology, Jordan, in 2000. He is currently working toward the Ph.D. degree at the National Chiao Tung University, Hsinchu, Taiwan. His current research interests are in low-voltage, low-power, and very high-frequency integrated circuits design and analog integrated circuits design in CMOS technology.
Dr. Chung-Yu Wu was born in 1950. He received the M.S. and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung Univer-sity, Hsinchu, Taiwan, ROC, in 1976 and 1980, respec-tively. In addition, he conducted post-doc research at UC Berkeley in summer of 2002. Since 1980, he has served as a consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Associate Professor at National Chiao Tung University. During 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor at National Chiao Tung University. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science on the National Science Council, Taiwan. From 1996 to 1998, he was honored as the Centennial Honorary Chair Professor at National Chiao Tung University. Currently, he is the president and chair professor of National Chiao Tung University. He has published more than 250 technical papers in international journals and conferences. He also has 19 patents including nine US patents. His research interests are nanoelectronics, low-power/low-voltage mixed-signal VLSI design, biochips, neural vision sensors, RF circuits, and CAD analysis. Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He was a recipient of IEEE Fellow Award in 1998 and Third Millennium Medal in 2000. In Taiwan, he received numerous research awards from Ministry of Education, National Science Council, and professional foundations.
