國 立 交 通 大 學
電機學院 電機與控制學程
碩 士 論 文
直流
直流
直流
直流-
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-直流降壓電源轉換器單晶片補償技術
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直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
ON-CHIP COMPENSATION TECHNIQUES FOR
DC-DC BUCK CONVERTERS
研 究 生：李家鈞
指導教授：陳科宏 博士
直流
直流
直流
直流-
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-直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
On-Chip Compensation Techniques for DC-DC
Buck Converters
研 究 生：李家鈞 Student：Jia-Jyun Lee
指導教授：陳科宏 Advisor：Ke-Horng Chen
國 立 交 通 大 學
電機學院 電機與控制學程
碩 士 論 文
A Thesis
Submitted to Department of Electrical and Control Engineering
College of Electrical Engineering
National Chiao Tung University
in partial Fulfillment of the Requirements
for the Degree of
Master
in
Electrical and Control Engineering
October 2013
Hsinchu, Taiwan, Republic of China
直流
直流
直流
直流-
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-直流降壓電源轉換器單晶片補償技術
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直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
直流降壓電源轉換器單晶片補償技術
研究生：李家鈞
指導教授：陳科宏博士
國立交通大學電機與控制工程研究所碩士班
摘 要
本文主要於較深入討論應用在直流-直流降壓電源轉換器的單晶片補償技術，其中 直流-直流降壓電源轉換器的控制方法一般可以分為電壓模式控制及電流模式控制，一 般而言，直流-直流降壓電源轉換器的補償電路都需要外掛元件如大電容得到期望的零 點位置而使系統可以穩定。 關於電壓模式控制的直流-直流降壓電源轉換器，通常使用型式三的補償電路以增 加迴路增益的交越頻率而得到較好的暫態響應，型式三的補償電路多半是由一個主動元 件如運算放大器或者是運算電導放大器以及外接的大電容和電阻完成，對於型式三的補 償電路的了解可以對於單晶片的比例積分微分控制器的設計提供很好的基礎，整合型的 單晶片比例積分微分控制器使用四個運算電導放大器產生兩個零點以補償電壓模式控 制的降壓電源轉換器產生的雙極點系統可以穩定，電路的結果證明單晶片的比例積分微 分控制器和型式三的補償電路的表現是相同的。 至於電流模式控制的直流-直流降壓電源轉換器，其優點在於使用比例積分控制器 即能使系統可以穩定，以補償的角度而言，這個好處是很明顯的，然而，比例積分控制 器仍須使用外接的大電容，這還是在晶片整合上形成障礙，於是對單晶片的電流模式密 勒補償及時間模式密勒補償電路有進一步的介紹、分析及實現，單晶片的電流模式密勒 補償利用電流對可以整合在晶片上的小電容充放電的密勒效應而得到等效大電容值，單 晶片的時間模式密勒補償則利用電路取樣原理在非常短時間內對誤差訊號作積分而得 到整合在晶片上的小電容值等效放大，電路的結果證明單晶片的電流模式密勒補償及時 間模式密勒補償的效能非常接近。On-Chip Compensation Techniques for
DC-DC Buck Converters
Student: Jia-Jyun Lee
Advisor: Dr. Ke-Horng Chen
Department of Electrical and Control Engineering
National Chiao-Tung University
Abstract
This work is discussing the comprehensive concepts of on-chip compensation (OCC) techniques for DC-DC buck converters with voltage mode control and current mode control. In general, the compensator network of DC-DC buck converter needs the external components for the large value capacitors to place the zeros in desired location to stabilize the system. Thus, the compensation of the regular DC-DC converter is completed by an off-chip compensator.
Regarding DC-DC buck converter with voltage mode control, Type III compensator is usually employed to extend the loop gain crossover frequency for better transient response. Type III compensation is often implemented by a single active element such as an OPA or OTA with off-chip large capacitors and resistors, and its insight of compensation provides the fertile background to develop the counterpart PID OCC. The integrated PID OCC takes four OTAs for the creations of two zeros to compensate the double poles from buck converter with voltage mode control. The simulation results show that the performance of PID OCC is comparable to that of Type III off-chip compensation.
As to DC-DC buck converter with current mode control, the advantage is that PI compensator is sufficient to manage the stability issue. The simplicity is obvious from the compensation point of view. However, the large capacitor required for PI compensator remains the problem to its integration on chip. Current mode Miller (CMM) OCC and time mode Miller (TMM) OCC is therefore introduced, analysed, implemented and simulated. CMM OCC by definition utilizes current to charge and discharge the small on-chip capacitor achieving the Miller effect for the large equivalent capacitance. On the other hand, TMM OCC makes use of sampling and hold to integrate the error information within very short period of time, and thus the capacitance amplification of the small on-chip capacitor is obtained. According to simulation results, the performance of CMM OCC and TMM OCC is compatible with current mode control buck converter.
Acknowledgements
First of all I would like to thank my adviser, Prof. Ke-Horng Chen for his assistance,
guidance, and inspiration to bring out the meanings of this work. I am also grateful for the
help provided by the colleagues in the Lab including circuit architecture and simulation
insight sharing. Particularly the supports from Y.J. Tu et al are highly appreciated for the
details in design analysis and problem solving. In addition, I have been so fortunate that
could have the understanding from my family during the years of study in NCTU.
Especially, I would be glad to show my respect and gratitude to the music of Teresa Teng for
her companion and filling my soul with so much love and peace. Finally, I would like to
express the appreciation to college of electrical and computer engineering in National Chiao
Table of Contents
Chapter 1 ... 1
Introduction ... 1
1.1 The Fundamentals of DC-DC Converter ... 1
1.2 Converter Topology ... 3
1.2.1 Open Loop System ... 4
1.3 Compensation Schemes ... 6
1.3.1 Closing the Loop ... 6
1.3.2 Compensation Guideline ... 6
1.3.3 Type III Compensation ... 7
1.3.4 Type I and II Compensation ... 7
1.4 Controller Alternatives ... 9
1.4.1 Voltage Mode Control... 9
1.4.2 Current Mode Control ... 11
1.4.3 Slope Compensation ... 13
1.4.4 Current Sensing ... 14
1.5 Advantages of On-Chip Compensation (OCC) ... 15
1.6 Thesis Organization ... 17
Chapter 2 ... 18
OCC for Voltage Mode Buck Converter ... 18
2.1 Type III Off-Chip Compensation ... 18
2.1.1 Closed Loop with Type III Compensation... 20
2.1.2 Compensation Design Procedure... 22
2.2 PID On-Chip Compensation Technique ... 23
2.2.1 PID OCC Architecture ... 24
2.2.2 Loop Gain Analysis ... 26
2.3 PSIM Implementation ... 29
2.3.1 Compensation Worksheets ... 29
2.3.2 Frequency Response ... 32
2.3.2 Load Regulation ... 34
2.3.3 Line Regulation ... 36
2.4 Type III and PID OCC Comparison ... 38
Chapter 3 ... 39
OCC for Current Mode Buck Converter ... 39
3.2 CMM On-Chip Compensation Technique ... 43
3.2.1 Miller Compensation ... 43
3.2.2 Capacitor Multiplier ... 44
3.2.3 CMM OCC Architecture ... 46
3.3 TMM On-Chip Compensation Technique ... 48
3.3.1 TMM OCC Concept ... 48
3.3.2 Qualitative Analysis of TMM OCC ... 49
3.3.3 Quantitative Analysis of TMM OCC ... 53
Chapter 4 ... 55
Circuit Implementation and Simulation Results ... 55
4.1 Technology Description ... 55 4.2 Circuit Implementation ... 56 4.2.1 CMM OCC ... 56 4.2.2 OTA Amplifier ... 57 4.2.3 Voltage Follower ... 58 4.2.4 TMM OCC ... 59 4.2.5 Three-Input OTA ... 60 4.2.6 Holding Buffer ... 61 4.2.7 Pulse Generator ... 62 4.2.8 Compensation Worksheets ... 64 4.3 Simulation Results ... 66 4.3.1 Frequency Response ... 66 4.3.2 Load Regulation ... 68 4.3.3 Line Regulation ... 70
4.3.4 Track and Hold ... 72
4.3.5 Pulse Generator ... 74
4.4 CMM OCC and TMM OCC Comparison ... 75
Chapter5 ... 76
Conclusions and Future Work ... 76
5.1 Conclusion ... 76
5.2 Future Work ... 77
List of Tables
Table 1 Compensation schemes ... 8
Table 2 Pros and cons of current mode control [10] ... 12
Table 3 Overview of current sensing techniques [13] ... 14
Table 4 Type III off-chip compensation worksheet ... 29
Table 5 PID OCC worksheet ... 30
Table 6 Comparison of Type III and PID OCC ... 38
Table 7 CMM OCC worksheet ... 64
Table 8 TMM OCC worksheet ... 65
Table 9 Schematics and parameters of PI off chip, CMM OCC, and TMM OCC ... 66
List of Figures
Figure 1 Simplified diagram of an ideal DC-DC converter ... 2
Figure 2 Diagram of a practical DC-DC converter ... 2
Figure 3 Converter topologies with controller embedded ... 3
Figure 4 Basic Blocks of Buck converter ... 5
Figure 5 Open loop of Buck converter ... 5
Figure 6 Bode plot of open loop Buck converter ... 5
Figure 7 Voltage mode control buck converter... 10
Figure 8 Voltage mode control duty ratio waveforms ... 10
Figure 9 A general implementation of current mode control... 11
Figure 10 Sub-harmonic oscillation and slope compensation ... 13
Figure 11 Conventional compensation network of power chip ... 16
Figure 12 Lower pin counts after compensation network integrated on chip.[16]... 16
Figure 13 Generic Type III compensation ... 18
Figure 14 Generic Type III compensation [2] ... 19
Figure 15 Closed loop buck converter with Type III compensation ... 20
Figure 16 Buck converter with Type III compensation Bode plots ... 21
Figure 17. Traditional PID controller ... 23
Figure 18 Block diagram of Buck converter with PID compensation ... 24
Figure 19 Buck converter with on-chip PID compensation ... 25
Figure 20 Current sensing network ... 26
Figure 21 PID OCC schematics ... 28
Figure 22 Bode plot of PID OCC ... 28
Figure 23 Buck converter with off-chip Type III compensation implemented by PSIM ... 31
Figure 24 Buck converter with on-chip PID OCC implemented by PSIM ... 31
Figure 25 Buck converter with Type III Off-chip Compensation frequency response ... 32
Figure 26 Buck converter with PID OCC frequency response ... 33
Figure 27 Load regulation of buck converter with Type III off-chip compensation ... 34
Figure 28 Load regulation of buck converter with PID OCC ... 35
Figure 30 Line regulation of buck converter with PID OCC ... 37
Figure 31 Simplified diagram of synchronous buck with current mode control ... 39
Figure 32 PI compensation implemented by OPA ... 40
Figure 33 PI compensation implemented by OTA ... 40
Figure 34 PI compensation Bode plots ... 41
Figure 35 Synchronous current mode Buck with PI compensator ... 42
Figure 36 PI compensated system Bode plots ... 42
Figure 37 Miller compensated two stages amplifier ... 43
Figure 38 Voltage mode capacitor multiplier ... 44
Figure 39 Current mode capacitor multiplier ... 45
Figure 40 CMM OCC schematics ... 46
Figure 41 Synchronous current mode buck with CMM OCC ... 47
Figure 42 DC-DC buck converter with TMM compensation ... 48
Figure 43 TMM OCC only with Cc and Rz ... 49
Figure 44 Interpretation of TMM OCC within a period ... 50
Figure 45 Comparison of PI compensation with TMM OCC ... 50
Figure 46 TS generated by N-bit counter ... 51
Figure 47 TMM OCC operation per 2N switching period ... 51
Figure 48 TMM OCC using small Cz and Rz ... 52
Figure 49 TMM OCC using small Cz with continuous zero ... 52
Figure 50 TMM compensator schematics ... 54
Figure 51 CMM compensator schematics ... 56
Figure 52 OTA schematics and DC gain ... 57
Figure 53 Schematics of voltage follower ... 58
Figure 54 Schematics of TMM OCC ... 59
Figure 55 Schematics of 3-input OTA amplifier ... 60
Figure 56 Holding buffer of TMM OCC ... 61
Figure 57 Schematics of pulse generator ... 62
Figure 58 Short pulse generator... 63
Figure 59 Bode plots of a. PI compensation, b. CMM OCC, and c. TMM OCC ... 67
Figure 61 Load regulation of buck converter with TMM OCC ... 69
Figure 62 Line regulation of buck converter with CMM OCC ... 70
Figure 63 Line regulation of buck converter with TMM OCC ... 71
Figure 64 TMM OCC and operation wave forms of 3-input OTA ... 72
Figure 65 Two track and holds wave forms... 73
Symbol and Abbreviation
OCC On-Chip Compensation
PID Proportional-Integral-Derivative PI Proportional-Integral
CMM OCC Current Mode Miller On-Chip Compensation TMM OCC Time Mode Miller On-Chip Compensation OTA Operational Transconductance Amplifier
OPA Operational Amplifier
DCR DC Resistance of an inductor
ESR Equivalent Series Resistance of a capacitor PWM Pulse Width Modulation
E.A. Error Amplifier T.F. Transfer Function
CCM Continuous Conduction Mode DCM Discontinuous Conduction Mode D Duty Ratio
Q Quality Factor RO Output Resistance
RON On-resistance of MOSFET
MOSFET Metal-Oxide-Semiconductor Field Effect Transistor COX Capacitance of Oxide layer
Chapter 1
Introduction
1.1 The Fundamentals of DC-DC Converter
An electronic circuit that converts a voltage with a dc level in a controllable manner without any energy loss is usually called an ideal DC-DC converter mainly to supply the regulated voltage and improve the power efficiency. As shown in Fig.1, the ideal DC-DC converter in the simplified diagram is controlled by the control parameter ß. For Vin, it could be such as battery, and Vo could be the applications such as CPU, Logic, Memory, or the portable electronic devices etc. When feedback path is applied as shown in Figure 1, the output voltage could be better regulated against the fluctuation in the input voltage or loading current. A vast majority of applications in the leading edge technology actually require an output voltage which is tightly regulated. To meet the demanding specification, the circuits in DC-DC converter including PWM modulation, controller design and its compensation, even the protection mechanisms are also turning complicated, and therefore are categorized in power management unit (PMU).[1]
As shown in Figure 2, the diagram of a practical DC-DC converter essentially has two sections. One is the power stage that is comprised of switch and LC filtering, and the other is the control section including modulator where PWM modulation is doing its work to control the duty ratio of the switch for correct output voltage level, and compensator whose purpose is to stabilize the loop and improve the frequency response for better transient performance. More detailed will be revisited in the following paragraphs.
Figure 1 Simplified diagram of an ideal DC-DC converter
Figure 2 Diagram of a practical DC-DC converter
Power Stage Compensator Modulator Control Section
Switch
Filter
1.2 Converter Topology
This section is to briefly look at the three fundamental converter topologies as illustrated in Figure 3 including buck converter, boost converter, and buck-boost converter. As far as the scope of this thesis is concerned, the buck converter, aka step-down DC-DC converter, will be discussed in more details in the following portions of control schemes and compensations.
Figure 3 Converter topologies with controller embedded
The simplest way to lower the voltage of a DC supply is to use a linear regulator like a LDO, but linear regulator wastes too much energy dissipating power to heat. Buck converters, on the other hand, could easily have much higher efficiency (95% or above for integrated circuits), making them the converter of choice to convert the main voltage in an electronic system such as a desktop or a laptop down to the lower voltage provided to CUP, HD, or Display etc.
A boost converter that has the output voltage higher than the input voltage is also called a step-up converter because it “steps up” the input voltage. The converter topology of boost
differs from Buck in the position of switch if it separates inductor and capacitor. This circuit topology could be in the application of low power battery to have the ability of well using up the remaining energy in a battery. That energy otherwise is wasted as the low voltage of a nearly depleted battery makes it not capable for a normal loading.
A buck–boost converter that has an output voltage either higher or lower than the source voltage actually has two different topologies, the inverting and the non-inverting topology. For the inverting topology, the output voltage of buck-boost is of the opposite polarity to the input, and the circuitry has the similar topology to the boost converter and the buck converter. As for the non-inverting buck-boost, it is a buck followed by a boost, and the output voltage is thus the same polarity with the input. A non-inverting buck-boost is in favour of a single inductor that could be buck inductor and boost inductor depending on the controls of the switches.
1.2.1 Open Loop System
In Figure 4 it represents the basic building blocks of DC-DC buck converter system. Prior to the compensator is included for a closed loop system, a generic open loop system is as shown in Figure 5 and its Bode plot shown in Figure 6. For systems with low DCR and ESR parameters, the phase will experience a sharp slope downward at the double pole while the gain will have a rather high peak. Systems that have such resonant output filters will be more difficult to do the compensation, and typically need a Type III compensation, which will be discussed later in Chapter 2.[2]
Figure 4 Basic Blocks of Buck converter
Figure 5 Open loop of Buck converter
= ∆
1 + ∗ ∗
1 + + +
1.3 Compensation Schemes
The criterion for a stable loop is that the total phase shift must be less than 360◦ at the cross over frequency as gain amplitude is 0 dB. This includes the necessary 180◦ negative feedback connection. The amount by which the total phase shift is less than 360◦ at the crossover frequency is called the phase margin. To ensure a stable loop under worst-case condition for a DC-DC converter, the most common practice is to design for 45◦ to 60◦ phase margin. As the compensation schemes shown in Table 1, the schematics and Bode plots are illustrated, and we would go over the more details in the following sections.[5]
1.3.1 Closing the Loop
As mentioned the compensation schemes are for closing the control loop that allows the regulator to adjust to load perturbations or changes in the input voltage which may adversely affect the output. Proper compensation of the system will allow for a predictable bandwidth with unconditional stability. In most cases, a Type II or Type III compensation network will properly compensate the system. The ideal Bode plot for the compensated system would be a gain that rolls off at a slope of -20dB/decade, crossing 0db at the desired bandwidth and a phase margin greater than 45° for all frequencies below the 0dB crossing. For synchronous and non-synchronous buck converters, the bandwidth should be between 20 to 30% of the switching frequency. In the next section, the compensation options and compensations design procedure will be introduced.
1.3.2 Compensation Guideline
To implement the desired loop gain with sufficient zero-cross over frequency and a safe phase margin, a sound compensation must be taken into consideration.
First step - Follow the specification to collect system parameters such as input voltage, output voltage and switching frequency etc.
Second step - Locate the poles and zeros of open loop that is without compensation.. Third step - Determine the zero crossover frequency and compensation type. The compensation type is determined by the location of zero crossover frequency and characteristics of output capacitor.
Forth step - Calculate the designed locations of zeros and poles for the desired compensator.
Fifth step – Calculate the parameters of compensator components including resistor and capacitor of designed compensator from standard catalogue so that the parameters could be as close to calculated value as we could.
1.3.3 Type III Compensation
Three types of error amplifier compensation schemes are most often used called the Type I, Type II, and Type III in order of the complexity and flexibility as shown in Table 1. As a matter of fact, Type I and Type II are just the subsets of Type III compensator. The transfer function of a Type III error amplifier is given by [8]
As = × ! #$+ 1 #+ 1
$+ 1 + 1
1.3.4 Type I and II Compensation
As shown in the transfer function of Type III compensator, it actually provides one pole-at-zero and two poles and two zeros. Compared with Type III, they are less powerful for Type I which only provides one pole-at-zero, and Type II which provides one pole-at-zero and one pole and one zero.
Table 1 Compensation schemes
Schem
e
Implementation
Bode plot
Type
III
Type
II
1.4 Controller Alternatives
The output characteristics can be modified by means of the control of duty ratio. As a matter of fact, the feedback path will control duty ratio to maintain constant output voltage no matter what conditions of input and output. Generally, there are two major options to control the duty ratio in DC-DC converter, voltage mode and current mode. The following sections are therefore focused on how the duty ratio is well elaborated. [4]
1.4.1 Voltage Mode Control
For voltage mode, as its name implies the output voltage is the parameter feedback loop mainly controls. As illustrated in Figure 7 that is very typical buck converter with voltage mode controller, and it is not difficult to know that voltage mode is a single loop control. In voltage-mode control, a control signal is compared to a ramp wave to control the duty cycle of the power switch. The higher the error voltage, the longer the switch is on. And the error voltage is derived in the feedback loop from the error amplifier that amplifies the difference between the output voltage and the reference voltage. It is applying pulse width modulation (PWM) to regulate the output voltage as shown in Figure 8 how the switching signal is modulated by the control signal which is generated from error amplifier and then compared to a ramp wave.
Voltage mode is a direct duty cycle control as the control signal or error voltage directly drives the duty ratio, and consequently it has a wide range of duty ratio; however the bandwidth of voltage mode control would be limited by the compensation of LC resonant frequency, and then the performance of the transient characteristics is dramatically poor if the bandwidth is not wide enough. In the next chapter, the solution to this problem will be further studied with conventional off-chip and on-chip compensation.
Figure 7 Voltage mode control buck converter
Figure 8 Voltage mode control duty ratio waveforms
Voltage Loop
Compensator
Control
Signal
Ramp
Control
Signal
Switching
signal
1.4.2 Current Mode Control
Current mode control was formally introduced to the power electronics world in 1978 [10]. It was quickly accepted as the common approach to control power supplies. A standard implementation of current-mode control is shown in Figure 9 A general implementation of current mode control Figure 9. Compared to single loop in voltage mode, current mode control features a current loop or the inner loop in Figure 9 and a voltage loop or outer loop. The error voltage is used to directly control the peak of the switch current. (A sawtooth ramp is often used in most cases and is referred to as slope compensation in current mode control.) This dramatically changes the behavior of the DC-DC converter. From the mathematical point of view, the transfer function of voltage mode is the second order which is corresponding to LC double poles, and the control to output with current mode is the first order. The major pros and cons of current mode control are briefly summarized in Table 2.
Figure 9 A general implementation of current mode control
Inner Loop
Table 2 Pros and cons of current mode control [10]
Control to output T.F. of Voltage mode
% & = '( 1 + 1 + %) + ! +ℎ-.- ! =√ 1 012 ) =
Control to output T.F. of current mode
% & = '3 1 + 1 + 45 +ℎ-.- 45 6 0 212 8.2-. 906. 8: 98;- 0< ℎ0;: <ℎ- +6<=ℎ61> :.-?@-1=A CONS PROS 1.Current Sensing:
It takes additional circuits to accurately sense either switch current or inductor current. The current sensing must be very wide band to correctly reconstruct the current signal.
2.Sub-harmonic Oscillation:
Current mode control could be unstable as duty ratio larger than 50%. A compensation ramp is necessary to fix the issue, and this could introduce complication as well.
3.Signal to Noise Ratio
The infamous problem in almost every current mode supply is noise on the current sense signal. In many power supplies there are simply not enough signals to control the converter smoothly over the full range of operation. Solution includes filtering the current wave form in different places for example in buck it would be the output side or leading edge blanking where the most noise in the initial part of the signal is ignored. Even with these approaches, which all increase circuitry complications, current mode control could be not working.
1.Easy Compensation:
With voltage mode, the sharp phase drop requires a type III compensator to stabilize the system. Current mode control looks like a single pole system, and a type II compensator is adequate.
2.RHP Zero Converters:
In a converter where the crossover frequency is restricted by the presence of an RHP zero. Although current mode control could not eliminate RHP zero, it makes the compensation easier.
3 CCM and DCM Operation
When moving from CCM mode to DCM mode, the characteristics with voltage mode control are very different. It is difficult to design a compensator with voltage mode that provides good performance in the two regions.
4 Line Rejection
Closing the current loop gives a lot of attenuation of noise. For buck, it can even be nulled under some specific conditions with proper compensation ramp.
As the pros mentioned in Table 2, the technique how to accurately sense the inductor current or switch current, and the proper slope compensation to prevent sub-harmonic oscillation instability are two major disadvantages for current mode control. The followings are to take a look at the techniques of current sensing and slope compensation.
1.4.3 Slope Compensation
Sub-harmonic oscillation is a well-known problem for current-mode switching converters when the duty ratio larger than 0.5 as shown in Figure 10. To avoid sub-harmonic oscillation, the slope compensation ramp is required to suppress the issue on as illustrated in Figure 10.[3]
1.4.4 Current Sensing
In Table 2, it also reveals that current sensing scheme is also playing a very key role for the converter with current mode control to precisely reconstruct the current signal of inductor. As shown in Table 3, it provides the reference of current sensing techniques for their advantages and the main concerns.
Table 3 Overview of current sensing techniques [13]
# Technique Advantage Main Concern
1 External sensing resistor
High accuracy and common practice
High power dissipation as all the inductor current or drain current of the power transistor must pass through the sensing resistor. Not only suffer from low efficiency, but also require extra off-chip known resistor
2 Sensor less integrator Claimed could be Lose-less
Complexity of design with different topologies, and The exact value of the inductor should also be known. Moreover, the accuracy of this current sensing scheme is influenced by different factors such as the time-constant value tolerance of the filter and manufacturing tolerances on the inductor.
3 On-resistance of
power switch Lose-less
Low accuracy due to that it is also sensed by a resistor, and the on-resistance of switch varies with temperature and different processes and thus affects accuracy.
4 Internal current
sensing Integrated on-chip
Increased the complication of circuit design for accuracy and variation from temperature, process and switch frequency.
1.5 Advantages of On-Chip Compensation (OCC)
As it is well known that the higher level of integration the better performance because it resulted from the reduction of parasitic component such as bonding wires, connections, or package. Unfortunately, off-chip inductors and capacitors take up significant area on PCBs, increase production cost, and make it difficult for system-on-chip (SoC) applications. To reduce the side effects of parasitic elements from wiring and power loss on them, it takes advantages to integrate the circuits on chip as many as we could. High integration is necessary to improve performance and have smaller footprint area. [15]
In Figure 11, the conventional compensation network contains a resistor and capacitors. After the integration of these passive components, pin out number can be minimized and the chip only needs the output filter which contains an inductor and a capacitor as shown in Figure 12. If the integration of the output filter into the chip is needed, the technique of system-in-package (SIP) can be used to implement the large off-chip output filter. For low cost and high integration, on-chip compensation techniques to implement a buck converter with minimized external pins and high performance are presented in the following chapters.
The difficulty of high integration in the design of dc-dc converters is due to the large off-chip capacitors for compensation. The compensator such as PI and PID controllers must generate poles and zeros to counteract the dominant pole or double poles and form a new suitable dominant pole for the desired bandwidth. However, large-valued capacitors needed for compensation would occupy a lot of space of layout if they are on-chip. By means of on-chip compensation techniques, zeros are generated by circuitry or large equivalent capacitance multiplied by current mode Miller compensation or time mode Miller compensation. It means that the minimization of capacitor size can alleviate the tradeoff between cost and performance to maximize the profit and cost down.
Figure 11 Conventional compensation network of power chip F E E D B A C K
Figure 12 Lower pin counts after compensation network integrated on chip.[16] External components
Output filter
1.6 Thesis Organization
This work is introducing the fundamentals of DC-DC converters in Chapter 1 which includes the basic converter topologies, control alternatives, compensation schemes, and the advantages of on-chip compensations. The on-chip compensation techniques such as PID on-chip compensation integrated for voltage mode buck converter, and current mode Miller (CMM) on-chip compensation as well as time mode Miller (TMM) on-chip compensation for current mode buck converter are playing the key roles in the Chapter 2 and Chapter 3. In Chapter 4, the circuit implementations and simulation results are therefore focused on the main building blocks used by CMM and TMM on-chip compensation techniques, following with the circuit level simulations to validate their characteristics and performances. The conclusions and future works are finally put in Chapter 5.
Chapter 2
OCC for Voltage Mode Buck Converter
This chapter focuses on compensation techniques for DC-DC buck converter with voltage mode control. First, generic type III compensator is reviewed in details including its transfer function, circuit schematics, frequency response, and practical design procedure etc. Contrary to type III off-chip compensation due to that it takes the large capacitors to position the desired zero as we would see in the next section, an integrated PID OCC in DC-DC buck converter is then the highlight of this chapter.
2.1 Type III Off-Chip Compensation
The Figure 13 shows a generic Type III compensation, its transfer function and asymptotic Bode plot. The Type III network helps to shape the profile of the gain with respect to frequency and also gives a 180° boost to the phase. This boost is necessary to counteract the effects of an under damped resonance of the output filter at the double pole.[22]
Type III Compensation Transfer Function, BC D =1 ∗ 3 ∗ 11 + 3 +2 ∗ 2 +1 1 + 3 ∗ 31 F + 1 + 22 ∗ 1 ∗ 2G ∗ +3 ∗ 31 1 where L-.81 =2 ∗ 2 , 1 L-.82 =1 + 33 1 N8;-1 = 1 2 F 121 + 2G , N8;-2 =331
2.1.1 Closed Loop with Type III Compensation
In Figure 15 shows a closed loop buck converter with Type III compensation network. Figure 16 depicts the asymptotic Bode gain plot for the close system with Type III compensation. For the transfer function of the compensated system, the gain and phase equation are also listed in the followings.
As with the Type III compensation network, it is recommended that the actual gain and phase plots be generated through the use of a commercially available analytical software package that has the capability to plot. In section 2.2 the general procedure of design flow is briefly described and demonstrated.[2][9]
Figure 15 Closed loop buck converter with Type III compensation
Figure 16 Buck converter with Type III compensation Bode plots
Buck with Type III compensation transfer functions are listed below,
OPQ = RST UBV+ W BV+ BX
PHASET = N^RST UBV+ N^W BV+ N^BX
where: RST UBV= 20 log d∆ e
W BV = 10 logf1 + ∗ ∗ %g − 10log f1 − ∗ + + g
BX = 10log f1 + 22− 20log f 11 + 2g − 10log f1 + 21 + 212
N^W BV= <01i$f ∗ ∗ g + <01i$f + ∗ i$ g
N^BX = −90° + <01i$f ∗ 2 ∗ 2g − <01i$l 21 + 2m + <0112 i$f 1 + 33g
2.1.2 Compensation Design Procedure
The systematic procedure will help calculate the poles and zeroes, and from those the component values to position the poles and zeroes for Type III compensation network. .
1. Choose a value for R1 usually between 2k and 5kohm
2. Pick a gain (R2/R1) that will shift open loop gain up to give the desired bandwidth. This will allow the 0dB crossover to occur in the frequency range where the Type III network has its second flat gain. The following equation will do calculation for an R2 that accomplish this given the system parameters and a chosen R1.
R2 =op4
∆
3q 1
3. Calculate C2 by placing the zero at 50% of the output filter double pole frequency. C2 =s ∗ 2 ∗ 41
4. Calculate C1 by placing the first pole at the ESR zero frequency C1 =2s2242
V− 1
5. Set the second pole at half switching frequency and also set the second zero at output filter double pole. This combination will yield the following component calculations.
R3 = 4 1
t
24 − 1
C3 =s ∗ 3 ∗ 41
t
The compensation gain must be compared to the open loop gain of the error amplifier. The compensation gain should not exceed the error amplifier open loop gain because this is the limiting factor of the compensation. Once the gain and phase plots are generated the system may need to be changed after it is analyzed. Adjust the poles and/or zeroes in order to shape the gain profile and make sure that the phase margin is larger than 45°or in between 45° to 60°.[9]
2.2 PID On-Chip Compensation Technique
This section presents a wide-band compensation that could be implemented by an on-chip integrated PID compensator for buck converter with voltage mode control. The details of the schematics and loop gain analysis will be discussed in the following sections.
The proportional-integral (PI) controller that is sufficient when the process dynamics is essentially first-order, proportional derivative (PD) controller and proportional integral derivative (PID) controller that has the advantages of PI and PD control are widely used in many industrial control systems. The traditional implementation of PID controller by OP-amps is as shown in Figure 17 and the transfer function of a general analog PID controller can be written as follows, [24]
Ts = % 3 = ' + ' + 'S +ℎ-.- ' 6 <ℎ- 9.898.<6810; >061, ' 6 <ℎ- 61<->.0; >061, 012 'S 6 <ℎ- 2-.6u0<6u- >061
Figure 18 shows block diagram of buck converter with PID compensation. The architecture of PID compensation will be presented in the next section. In addition to the voltage feedback, the current of inductor is sensed and summated with error amplifier as a part of compensator. It looks like there are two feedback paths compared to current control, but it is still a voltage mode control. [20] The current sensing network is also shown below.
Figure 18 Block diagram of Buck converter with PID compensation
2.2.1 PID OCC Architecture
The buck converter as shown in the Figure 19 consists of a PID controller that is designed for fully integrated on the chip. The PID controller is including a differential controller, an integral controller and the proportional controller. The overall architecture is similar to the PID controller mentioned in section 2.2.
To meet the fast load transient response and achieve a bandwidth of 200 kHz with phase margin 60°, it needs PID controller for voltage mode control instead of using either dominant pole compensation or PI compensation. The P (proportional)-controller is composed of only
Operational Transconductance Amplifier circuits (OTA2 and OTA3) to avoid large resistors. An error amplifier (OTA1), known as I (integral)-controller, is designed with additional compensation capacitor Cz. The output voltage is differentiated by D controller using the ripple current of the inductor (IL_ac) detected by integrating the voltage difference across the
voltage of the inductor (VL), which is given as
_w& =1 x 2<
Figure 19 Buck converter with on-chip PID compensation
Therefore, the RC-series is connected to the inductor terminals. Then, the voltage across the capacitor (Cl) is detected by OTA4. This technique is an effective method for obtaining AC ripple current information. Current sensing network that senses AC ripple inductor current with passive devices only including one capacitor and one resistor as shown in Figure 20, and the correlation of sensed voltage and network components such as Cl and Rl is also attached below,
Figure 20 Current sensing network
As shown Figure 20 that is a RC low-pass filter to sense inductor current and the voltage across the inductor L is
vz= R{|}+ sLiz ,
And the voltage across capacitor Cl is
v| = 1 sCl Rl + 1sClvz= 1 1 + sClRl vz= R{|}1 + sLR{|} 1 + sClRl iz If SV = ;;, Qℎ-1 u = SV ∗ 6
2.2.2 Loop Gain Analysis
The transfer function of the total loop gain of buck converter with PID compensator is derived in the following equations T(s), [20]
Ts = − 1 R % F 1 !G + F )! !G + 1 $ $+ 1 + %V 1 1 + 1 where )! = ! , % % = 1 %
R 6 <ℎ- Np >061, 6 2@<A .0<68,
V 6 <ℎ- -?@6u0;-1< -.6- .-6<01=- 8: 8@<9@< =090=6<8.
.-9.--1< <ℎ- 90.06<6= =090=6<01=-
The transfer function of PID compensation Gcc(s) as shown in fig
s = + $$d 1 $+ 1e + + 1 1 ;; + 11 + 1V +ℎ-.- N =81<.8;;-. >061 , $$d 1 $+ 1e =81<.8;;-. >061 d + 1 e d 1 ;; + 1e d1 + 1Ve =81<.8;;-. >061 Qℎ@, <.01:-. :@1=<681 8: N .-+.6<<-1 0 s = '+' + ' S
There are two following poles: one which is generated by the inductor current sensor, Rl and Cl, and the other which is generated by Co and RESR. Since 1/( Co·RESR) is a zero in
terms of the control-to-output transfer function, it is canceled out in the total loop transfer function. The compensator contains two zeros as shown in fig. Zero1 is at the point where the magnitude line of I-control meets that of P-control. The zero1 location is calculated in the following equations,
G G = G$R$d 1 sCR$+ 1e Zero1 = $ ∗
The other zero, Zero2, exists at the point where the magnitude line of P-control meets that of D-control. Zero2 position will be known by solving the equations as shown below,
= + 1 1 ;; + 1 Zero2 = ∗ ;;
Figure 21 PID OCC schematics
Figure 22 Bode plot of PID OCC
D
controller
I controller
2.3 PSIM Implementation
2.3.1 Compensation Worksheets
As shown in Table 4 and Table 5, the worksheets of Type III off-chip compensation and PID OCC are to facilitate the calculations of poles and zeros, and are very helpful for the parameters tuning as running the simulations.
Table 4 Type III off-chip compensation worksheet
Converter Parameters Input Voltage: VIN 3.3V Output Voltage: VOUT 2.5V Output Current: 500mA
Switching Frequency: FSW 1MHz
Total Output Capacitance: COUT 44µF
Total ESR: RESR 8mΩ
Inductor: L 2.2µH
Inductor DCR: DCR 18mΩ Control scheme: Voltage mode Compensation : Off-chip Type III Reference Voltage: VREF 1V
Error Amp DC Gain 80dB
Desired Bandwidth: DBW 200kHz Phase Margin: 60° R1= 7 kΩ R2= 70 kΩ R3= 100 Ω C1= 1 pF C2= 400 pF C3= 600 pF Zero1= 5.7 kHz Zero2= 37.4 kHz Pole1= 23 MHz Pole2= 2.65 MHz Buck converter
Type III compensator
Poles and zeros positions, Zero1 = 2π ∗ R2 ∗ C2 1 Zero2 =2π ∗ R1 + R3C3 1
Pole1 = 1
2π ∗ R2 F C1C2C1 + C2G Pole2 = 2π ∗ R3 ∗ C31
Table 5 PID OCC worksheet
Converter Parameters
Input Voltage: VIN 3.6V Output Voltage: VOUT 2.5V Output Current: 500mA Control scheme: Voltage mode Compensation : On-chip PID Reference Voltage: VREF 1V
Switching Frequency: FSW 1MHz
Total Output Capacitance: 44µF COUT 44uF (22uF X2)
Total ESR: RESR 8mΩ
(16mohm // 16mohm)
Output Inductance: Lout 2.2uH Inductor DCR: DCR 18m Desired Bandwidth: DBW 200kHz(f0) Phase Margin: 60° Gm1= 20µ A/V Gm2= 20µ Gm3= 400µ Gm4= 20µ Cz= 40 pF Rz= 50 MΩ Cl= 20 pF Rl= 200 kΩ Zero1= 4 kHz Zero2= 820 kHz ESR zero @ 452 kHz LC double poles @ 16.2 kHz Buck converter PID OCC Zeros positions Zero1 = $ ∗ Zero2 = ∗ ;;
Figure 23 Buck converter with off-chip Type III compensation implemented by PSIM
2.3.2 Frequency Response
As shown in Figure 23 and Figure 24 are buck converters with Type III and PID compensator implemented by PSIM. The total loop gain of buck converter with Type III is in the following Bode plots in Figure 25 showing that the system has phase margin 60°as cross over frequency is at 200 kHz.
Figure 25 Buck converter with Type III Off-chip Compensation frequency response
fc=200kHz PM=60°
The frequency response of buck with PID on-chip compensation is in Figure 26 for its loop gain amplitude and phase Bode plot. The phase margin and cross over frequency is the same as that of Type III off-chip compensator that requires the large compensation capacitors C2 equal to 400pF and C3 600pF to cope with the system stability.
Figure 26 Buck converter with PID OCC frequency response
fc=200kHz PM=60°
2.3.2 Load Regulation
The load regulation is defined as the percentage of steady state output voltage variation when the load current changes. The load regulation of buck with Type III compensator as loading current from 500mA to 1A within 1 µsec is 48 mV/A as shown in Figure 27 (a) and the enlarged view in (b), respectively.
(a) Enlarged view of load regulation shown below
(b)
Figure 27 Load regulation of buck converter with Type III off-chip compensation
Load regulation = 48 mV/A
Loading current rises from 500mA to 1A and returns.
As shown in Figure 27 (a) and the enlarged view in (b) with the same condition loading current from 500mA to 1A within 1 µsec, the drop voltage is 33 mV and the load regulation of buck converter with PID compensator is 66 mV/A.
a. Enlarged view of load regulation shown below
b.
Figure 28 Load regulation of buck converter with PID OCC
Load regulation = 66 mV/A
Loading current rises from 500mA to 1A and returns.
2.3.3 Line Regulation
Line regulation is expressed as ratio of change in the output voltage relative to the change in the input line voltage. The line regulation of buck with Type III is 33mV/V at the condition that input voltage changes from 3.3V to 4.3V within 1 µsec as shown in Figure 29 (a) and (b) that is the enlarged view.
(a) Line regulation of buck with Type III compensator
(b)
Figure 29 Line regulation of buck converter with off-chip Type III compensator
Input voltage rises from 3.3V to 4.3V and returns.
Figure 30 (a) and (b) shows the regulation of buck with PID compensator is 21mV/V as input voltage changed from 3.3V to 4.3V. Compared with that of Type III, it is 10mV better, but for load regulation, buck with PID is 15mV worse than that of Type III.
(a) Line regulation of buck with PID OCC
(b)
Figure 30 Line regulation of buck converter with PID OCC
Line regulation = 21 mV/V Input voltage rises from
2.4 Type III and PID OCC Comparison
. As listed in Table 6, it summarizes the comparison between DC-DC buck with voltage mode control compensated by off-chip Type III and on-chip PID and the performance of transient and frequency response for them are quite comparable.
Table 6 Comparison of Type III and PID OCC
Compensation Type III PID
Power Stage
Supply Voltage 3.3V Output Voltage 2.5V Switching Frequency 1MHz
Control Scheme Voltage Mode LC Filter Inductor-DCR 2.2µH-18mΩx2
Capacitor-ESR 22µF-16mΩx2
Compensator
Technique Off-Chip On-Chip
Components OPA1 OTA1 R1 7kΩ OTA2 C1 1pF OTA3 R2 70kΩ OTA4 C2 400pF Rz 50MΩ R3 100Ω Cz 40pF C3 600pF Rl 200kΩ Cl 20pF Zero1 1 22 $ Zero2 1 1 + 33 ;; Crossover Frequency 200kHz Phase Margin 60° Line Transient Comparable Load Transient Comparable
Chapter 3
OCC for Current Mode Buck Converter
Chapter 3 presents the concepts of current mode synchronous buck converter with on-chip compensations. The simplified diagram of the system is as shown in Figure 31. As far as the compensators are concerned in this chapter, first as it is discussed in the Chapter 1 that PI compensation is sufficient to stabilize the current mode buck, PI compensation will be reviewed in short. Second, following Miller compensation and capacitor multiplier, they pave the way for the application of current mode Miller (CMM) OCC in section 3.2. Then, the current mode counterpart is thus named time mode Miller (TMM) OCC that will be discussed in section 3.3.
3.1 PI off Chip Compensation
Figure 32 illustrates PI compensator realized by OPA that is actually taken away one capacitor and one resistor from PID compensator as mentioned in chapter two. Thus, it only has one pair of zero and pole. In the PI compensator, the ripple of the output voltage (Vo) is filtered by the integrator during the full period comparison process, in which the error between the average value of Vfb and Vref is integrated in a large C2. From circuit point of view, PI compensator by OPA could be correspondingly implemented by OTA. [2][9]
Figure 32 PI compensation implemented by OPA
The transfer function and the formula of pole and zero positions for PI compensator are shown in the following equations 2-1 to 2-3. From Figure 34, it shows the Bode plots and the phase boost that is 90°for PI compensation.
BX = K + 122
+ 1 + 2212 2 − 1 L-.81 = 2 ∗ 2 2 − 21
N8;-1 = 1
2 121 + 2 2 − 3
It would help get the picture of a buck converter with PI compensator from Figure 35 and the overall Bode plots of PI compensated system as illustrated in Figure 36.
Figure 35 Synchronous current mode Buck with PI compensator
3.2 CMM On-Chip Compensation Technique
In this section, the technique named current mode Miller (CMM) OCC is described for its application of on-chip integration compared with that of off chip compensation in section 3.1. The background of Miller compensation and capacitor multiplier are also introduced in the followings for better appreciation of CMM OCC.[23]
3.2.1 Miller Compensation
As illustrated in Figure 37 a two-stage amplifier circuit is applied the common technique to use Miller capacitor for compensating amplifier feedback circuits. The poles of a two-stage amplifier are split, one toward low frequencies and the other toward high frequencies. The pole at the output of the first stage becomes dominant. Transconductors Gm1 and Gm2 are assumed to be ideal, and R1 and R2 resistors model the effective impedance to ground at their corresponding nodes, CL and Cc are the load capacitor and the compensating capacitor, respectively. The dominant low-frequency pole is located at node n1 and is defined by [12]
Nq$ ≈2s11 +ℎ-.- = 2 -Gm1
R2
Cc
CL
R1
Vo
-Gm2Vin
n1
3.2.2 Capacitor Multiplier
As illustrated in Figure 38 the voltage mode capacitor multiplier that takes advantage of Miller effect discussed in section 3.2.1. The equivalent capacitance to ground at node is derived from the displacement current flowing through capacitor. The current is
& = ∆ && = q$− %& = q$1 + &
+ℎ-.- & 6 <ℎ- u8;<0>- 0=.8 <ℎ- =090=6<8.
& =L &
&, L& 6 <ℎ- 69-201=- 8: <ℎ- =090=6<8.
The equivalent capacitance to ground Ceq is
D= &
q$= 1 + &
Figure 38 Voltage mode capacitor multiplier = −∗ q$
In Figure 39, on the other hand, shows the concept of the current-mode capacitor multiplier. The essence of the idea is to sense the current through the capacitor, multiply it by a factor greater than one (k > 1) and put it back to the same node by means of a current-controlled current source. The amplification could be realized by current mirrors. The equivalent capacitance seen at node n1 is [11][12]
D = &D q$= + q$ = 1 + q$ = 1 + k
Figure 39 Current mode capacitor multiplier
6 = C2u2<
k + 1 ∗ 6 = + 1 ∗ 2u2<
3.2.3 CMM OCC Architecture
When the operation condition of a MOSFET is VDS << 2(VGS-VTH), one would have
S ≈ q%p − B S
The linear relationship can be also represented by a linear resistor equal to
= 1
q%p − B
If two MOSFETs operating in linear region have the same VGS and VDS, the equivalent impedances are inversely proportional to their aspect ratios. The principle can be the implementation of current mode Miller capacitor multiplier discussed in section 3.2.2. As shown in Figure 40, it is to integrate current mode Miller capacitor multiplier into PI compensation for the application in DC-DC buck converter, and therefore is named current mode Miller (CMM) on-chip compensation (OCC). [15][16][17][18]
The equivalent impedances of MOS transistors in triode region are modeled as R and KR as shown in Figure 40. If high frequency components are neglected, the transfer function of current mode Miller compensation is
As ≈ −> $1 + '1 + '##
##+ 3 − 1
Then, if RO is much larger than RZ, the zero and pole generated by CMM OCC can be
written as,
Zero ≈ −'1
##
Pole ≈ −'1
#
As shown in Figure 41 synchronous current mode DC-DC buck converter with TMM compensation, we could be easier to assign the parameters of compensator using the worksheet as Table 7 that will be introduced in circuit implementation in next chapter.
3.3 TMM On-Chip Compensation Technique
This section presents the on-chip compensation technique of current mode synchronous DC-DC buck converter named TMM OCC, which decreases the charging or discharging time of the capacitor in order to obtain the capacitance amplification that resembles to the Miller effect. In the following passages the concept of TMM OCC will be addressed. [21]
3.3.1 TMM OCC Concept
Figure 42 consists of a TMM path, a continuous zero and a noise filter. Gm1, Cc and switch form TMM path generating integral information. Gm2 and Rz form the continuous zero path. It features a pre-determined short time (TS) defined in one switching period. As the switch is turned on during TS, control voltage is changed within TS. For the rest of a period, switch is OFF and holding buffer keeps the output of Gm1 to Vc. If TS is short enough, Vc changes slowly. Thus, a capacitance amplifying similar to Miller effect is obtained.
3.3.2 Qualitative Analysis of TMM OCC
TMM OCC in Figure 43 shows the operation of TMM OCC integration that is very similar to that of PI compensator except for the switch added. Compared with conventional integration in PI compensation as the illustration in Figure 44 and Figure 45, for conventional integration, Vc2 changes slowly and continuously during the switching period. On the other hand, TMM OCC integration path, Vc1 changes discontinuously during only TS and holds in the rest of the switching period. The point here is that the total change of both vc1 and vc2 is exactly the same. The relation between the capacitances Cc1 and Cc2 is
$∙ ∆u = ∙ uD ∙ Q
∙ ∆u = ∙ uD∙ QND
→ = QNQ ∙ D $
From this operation, the equivalent Miller capacitor of TMM OCC is as
D = QNQ D &
Where TPe is one switching period
Figure 44 Interpretation of TMM OCC within a period
(a) PI compensation
(b) TMM OCC
Figure 45 Comparison of PI compensation with TMM OCC
∆
ViMiller gain is the ratio of TPe and TS. To have a larger gain, a shorter TS or longer TPe is necessary, but it is limited to make TS significantly short. TPe also cannot be changed because it is determined by the switching frequency. However, as shown in Figure 46 TS can be generated per 2N switching periods by using an N-bit counter. In Figure 47, the total
change (∆vi) controlled by (∆vc) is equivalent to that of the conventional compensator. By this operation, the miller gain of TMM OCC is multiplied by 2N. The equivalent capacitance
is
D =2 ∙ QN
D
Q &
Figure 46 TS generated by N-bit counter
Figure 47 TMM OCC operation per 2N switching period
2N▪TPe
2N▪TPe
In PI compensator, the zero is simply obtained by connecting Rz with Cc in series. However, in the TMMC the zero is not obtained even if Rz is connected with Cc in series as in Figure 48 with Bode plot that is without any zero. It is due to a simple resistor is not suitable for the TMMC since the resistor cannot reflect the phase lead information in a very short period. Therefore, an additional continuous path is connected to Rz in order to pass the proportional signal of the Vfb to Vc. This proportional signal of the Vfb is divided by the ratio of Cc and Cc + Cf and added to the Vc signal to generate the zero as shown in Figure 49 with Bode plot that is the same as that of PI compensator.
Figure 48 TMM OCC using small Cz and Rz
3.3.3 Quantitative Analysis of TMM OCC
As mentioned by TMMC concept, the Vc signal generated from the sum of the TMMC signal and the continuous zero signal is interpreted by the superposition method. So does for transfer function of TMMC as shown in Figure 50. The transfer function of the TMM compensator is the sum of the transfer functions of the TMMC path and continuous zero path which are derived in this section, respectively.
The error voltage (Ve) which is the difference between Vfb and Vref, is converted to current by Gm1 and the switching TS. The current flows into or from the equivalent output impedance of compensator to generate Vc. The transfer function of the TMMC path is
$
D ≈
> $%$
1 + 2Q QN- + %$
The Ve is also converted to current by Gm2. The current is divided by the ratio of impedance of Rz and the series connection of Cc and Cf. This divided current flows into or from Cf to generate Vc. The transfer function of the continuous zero path is
D ≈ > + 1+ 1 ∙1
By superposing the transfer function of TMM path and the one of continuous zero path , the total transfer function of the TMM OCC is
D = $ D + D
D ≈ > $%$ f1 + g l1 + $m l1 + m pℎ-.- => 1 > $ 2 QN-Q $ =2QN- 1 Q + $ = 1 +
As shown above, ωp1 and ωz are placed at the low frequency range because of the miller
effect of TMM OCC; however, ωp2 not affected by the miller effect of TMM OCCC is located
at a high frequency. This pole-zero locations are corresponding to those of the conventional PI compensator that needs large capacitance whose value equals to (2N·TPe /TS)*Cz.
Chapter 4
Circuit Implementation and Simulation Results
In this chapter, the details of the key sub circuits for CMM OCC and TMM OCC in chapter 3 are presented. The circuit analyses and HSPICE simulations for these sub blocks are also discussed in this chapter. In the beginning the technology information will be provided.
4.1 Technology Description
The device models such as CMOS, MiM Cap, HR, BJT etc. in this integrated circuit simulation are based on VIS 0.25um CMOS Mixed-Signal 1P5M (single poly, 5 metal layers), silicide, Al technology. The node actually is a TSMC-like process that is compatible with industry standard. [25][26]
Key features of frond-end of line are including shallow trench isolation (STI) for active isolation to reduce device pitch, retrograde twin well for a low well sheet resistance, enhancement of latch-up behavior, and for a better control of parasitic field transistor, and self-aligned Ti-silicided drain, source and gate that significantly reduces gate and S/D serial resistance. For high value resistors offered in this technology are 1kΩ per square and 1.5kΩ per square.
For back-end key features, they include Tungsten contact and via for connecting metal layers, chemical mechanical polishing (CMP) to enhance planarization of STI, contact, via, and inter-metal dielectric. The metal insulator metal (MiM) capacitor provided in this process is with 1.15fF per square unit capacitance.
4.2 Circuit Implementation
The section is to present the circuit implementations of CMM OCC and TMM OCC including the major building blocks such as OTA, voltage follower, 3-input OTA, short pulse generator etc.
4.2.1 CMM OCC
The schematic of CMM OCC is as shown in Figure 51. By means of control for the transistors working at linear regions, the current ratio of I1 flowing through left side in CMM OCC and I2 through right side is K. As described in section 3.2.3, the equivalent capacitance Ceq is equal to (1+k)*Cz.
Figure 51 CMM compensator schematics I1
I2
OTA
4.2.2 OTA Amplifier
The error amplifier used in Figure 51 is constructed by an OTA. The frequency response of OTA is as shown in Figure 52. The DC gain of OTA is designed to be 72.6 dB and bandwidth is over hundreds of MHz.[6]
(a) OTA Schematics
(b) OTA DC gain
Figure 52 OTA schematics and DC gain
4.2.3 Voltage Follower
The gate terminals of transistors MZ1 and MZ2 as shown in Figure 51 are connected to voltage source Vdd and the voltage level of output node of OTA is designed smaller to ensure that the transistors of MZ1 and MZ2 work in linear region. When capacitor Cz is discharged, the source voltage of MZ1 is higher than its drain voltage. When capacitor Cz is charged, the source voltage of MZ1 is lower than its drain voltage. To count with these two circumstances, it is necessary to use a voltage follower to sink and source current to transistor MZ2 according to the drain-source voltage of MZ1. The circuit of voltage follower is as shown in Figure 53 that is a two-stage amplifier and C1, C2 and Rcomp are to compensate the frequency response of the amplifier.
4.2.4 TMM OCC
The schematic of TMM OCC shown in Figure 54 consists of a TMM path, a continuous zero and a noise filter. The Gm1, Cz and transmission gate (TG) generating the integral
information also obtain the large equivalent compensation capacitance through the sampling and hold procedure of TS. The Gm2 and Rz form the continuous zero path generating the
proportional gain information as discussed in section 3.3.2. to have the zero similar to that in PI compensator frequency response.
Figure 54 Schematics of TMM OCC
For TMM OCC the comparison time is limited to TS, but the error amplifier has to locate the center value of feedback voltage during this short period to integrate the difference between reference voltage and feedback voltage. Because of the ripple voltage it is not easy to know the moment if feedback voltage is at the center value.
