Sub-1 V Input Single-Inductor Dual-Output (SIDO) DC-DC Converter With Adaptive Load-Tracking Control (ALTC) for Single-Cell-Powered Systems

Sub-1 V Input Single-Inductor Dual-Output (SIDO)

DC–DC Converter With Adaptive Load-Tracking

Control (ALTC) for Single-Cell-Powered Systems

Ming-Hsin Huang, Yu-Nong Tsai, and Ke-Horng Chen, Senior Member, IEEE

Abstract—In this paper, a sub-1 V input single-inductor

dual-output (SIDO) dc–dc converter with an adaptive load-tracking control (ALTC) technology is proposed for single-cell-powered portable devices. Having a minimal number of switches and an optimum current sequence, the proposed ALTC technique adap-tively and accurately adjusts storage energy in the form of inductor current according to the actual load condition, without wasting sur-plus charge and without increasing cross regulation. Moreover, a current-mode ring oscillator with a self-bias current source circuit, in place of the conventional start-up ring oscillator, is proposed to produce a nearly constant system clock for the requirement of sub-1 V start-up procedure. Because the proposed current-mode ring oscillator operates between the start-up process and steady state of the SIDO dc–dc converter, its simplified design efficiently addresses the high switching frequency losses at sub-1 V start-up procedure, reducing chip area and power consumption. The proposed sub-1 V input SIDO dc–dc converter was fabricated via Taiwan Semiconductor Manufacturing Company 0.25 µm 2.5 V/ 5 V Bipolar-CMOS-DMOS process, and the experimental results show high efficiency of 92% with a good cross regulation smaller than 10 mV.

Index Terms—Adaptive load-tracking control (ALTC)

tech-nique, dc–dc converter, single-inductor dual-output (SIDO) self-bias current source (SBCS) circuit, single-cell-powered systems, sub-1 V input.

I. INTRODUCTION

M

INIATURIZATION and low-power consumption are es-sential features of portable devices; these devices are ex-pected to have small volume and long battery life [1]. To achieve these advantages, single-cell-powered systems that scale down the supply voltage is one effective solution. In particular, the AA- and AAA-size nickel-based rechargeable batteries, having

Manuscript received July 16, 2009; revised October 14, 2009. Date of current version June 18, 2010. This work was supported by the National Science Coun-cil, Taiwan, under Grant NSC 97-2221-E-009-172. Recommended for publica-tion by Associate Editor R.-L. Lin.

M.-H. Huang is with the Department of Electrical Engineering and Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan.

Y.-N. Tsai is with the Department of Electrical Engineering and Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with Richtek Technology Corporation, Chupei City 30288, Taiwan.

K.-H. Chen is with the Department of Electrical Engineering and Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu.edu.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2042073

Fig. 1. Applications of a low-voltage input power converter.

high capacities and 1.2-V terminal potentials, are widely and conveniently applied for use in portable devices. However, the terminal potential decreases below 1 V when the battery deliv-ers its stored energy to a portable device. Small-input battery voltage swings cause analog circuitries to become more sensi-tive to noise, signal perturbation, and ground bounce [2], [3]. For example, all load conditions detected from multiple output terminals can determine the exact inductor current level. The accuracy deteriorates, thus the output-regulation further wors-ens. Furthermore, the headroom voltage of the control circuit is limited by the battery and becomes a critical design issue in the single-cell-powered system. As illustrated in Fig. 1, a portable device commonly composed of a variety of submodules can pro-vide several functions, such as LED backlight, liquid crystal dis-play (LCD) monitor, and several signal-processing utilities. For basic power management, the distributive voltage and current-control methodology are needed to increase power efficiency in order to extend the battery life. As a result, the design of power management IC needs to contain several switching converters with different conversion ratios and some low-dropout (LDO) regulators to provide multiple output voltages to address the re-quirements of portable devices. Unfortunately, several external inductors and capacitors are needed and occupy a large area on the printed circuit board (PCB). These are not consistent with the features of miniaturization and low-power consumption of portable devices [4].

In order to effectively reduce the number of external induc-tors, the design of a single-inductor multiple-output (SIMO) dc–dc converter was presented for application to portable de-vices [4]–[6]. The design challenges of the SIMO converter include the reduction of the number of power switches, conduc-tion loss, switching loss, and cross regulaconduc-tion. A lesser number

Fig. 2. Operating current paths of SIDO dc–dc converter.

of power switches can reduce the silicon area and switching loss. Less conduction and switching losses can improve the power-conversion efficiency. Having reduced cross regulation ensures a minimized crosstalk effect between these output ter-minals through the use of a single inductor. There are many design methodologies proposed to achieve some of these re-quirements; however, it is difficult to address all the require-ments at the same time. Particularly, the design needs to involve the sub-1 V characteristic in the single-cell-powered system.

Woo et al. [5] proposed a freewheeling current feedback as a current-control method to regulate multiple boost output volt-ages without any buck output voltvolt-ages. The freewheeling cur-rent level is dynamically adjusted cycle by cycle according to the load condition. Since the freewheeling current is monitored and compared to a reference in order to increase or decrease energy in the inductor, the main control loop of converter can indirectly detect an instantaneous load condition of each output without sensing each output load condition. As a result, the in-ductor current can be kept at a level adequate enough to react to any transient load response. Furthermore, the PI compensation only needs to be applied on the current loop of the freewheeling adjustment, thereby reducing the external compensation com-ponents. Unfortunately, the transient response is slowed down due to the slow adjustment of the freewheeling current, and thus, the cross regulation becomes worse due to low system bandwidth.

In order to provide different output types simultaneously, the conventional single-inductor dual-output (SIDO) dc–dc con-verter, which is shown in Fig. 2, uses five switches and one external inductor to provide one buck output and one boost out-put. Therefore, the power management IC of portable devices can simultaneously provide power sources higher or lower than the battery voltage with a small PCB area [6]. Furthermore, the SIDO dc–dc converter, proposed in [6], reorganizes the pos-sible inductor current paths in conventional SIDO converter design to constitute an adaptive current-control sequence, and

simultaneously provides buck and boost output voltages with the minimum number of power switches. Since the adaptive current-control sequence, proposed in [4], reorganizes the in-ductor current sharp and does not affect the regulation of each output, the number of power switches can be reduced to about three, as compared to five in the conventional design. Here, the small freewheeling power switch is not counted. Having a reduced number of power switches decreases the conduction and switching losses, thus increasing the power-conversion ef-ficiency to about 90%. Although this design increases power efficiency, it also induces other problems. The serious cross regulation that occurs in the delivery power of buck output is larger than that of boost output and the complex control circuit becomes the major issue. In this respect, the design challenge of the SIDO converter becomes more difficult, aiming to en-sure minimized cross regulation and provide multiple buck and boost output voltages with small output ripples in the single-cell-powered system.

This paper presents a sub-1 V SIDO dc–dc converter with the proposed adaptive load-tracking control (ALTC) technique to provide one buck and one boost output voltages, which oper-ates with AA- and AAA-size rechargeable batteries. Minimized cross regulation can be ensured without being affected by small input voltage headroom. The conduction and switching losses, large start-up current, and disordered power-on sequence can be further reduced due to the low-voltage operation. As a result, the proposed SIDO converter can still operate under sub-1 V input battery voltage; therefore, miniaturization and low-power consumption can be achieved in a single-cell-battery-powered system. The organization of this paper is as follows. Section II describes the structure and the controlling sequence neces-sary to achieve high efficiency and guarantee system stability. Section III describes the proposed ALTC technique for mini-mum cross regulation. Section IV describes the implementation of the proposed SIDO circuit. Section V shows experimental results, and finally, conclusions are made in Section VI.

TABLE I

SPECIFICS OFOPERATIONCURRENTPATHS

II. CURRENT-CONTROLLINGSEQUENCEWITHMINIMIZED

SWITCHES FORHIGHPOWEREFFICIENCY ANDSYSTEMSTABILITY

Only one cell serves as the energy supply source in single-cell-powered portable devices. In order to propose an energy delivery topology that can produce one buck and one boost output volt-ages with minimum power loss, the structure of the conventional SIDO dc–dc converter, as depicted in Fig. 2, is usually used to analyze the inductor current paths, segment current slope, and fundamental control methodology [6]. Because the inductor cur-rent IL of the SIDO converter indicates the energy delivery and

transfer status, six current delivery paths listed in Fig. 2 and Table I can be used to constitute the desired inductor current waveform during one switching cycle. As shown in Fig. 2, when the high-side (HS) MOSs SW1and SW4turnON, current Path

1 is created and the output terminal VO A is connected to supply

the voltage. In the meantime, energy is delivered to the out-put terminal VO A and the current slope can be calculated by the

equation (VIN–VO A)/L. If output VO Ais lower than supply

volt-age VIN, then the converter is a buck converter, and the current

slope is positive. On the contrary, if output VO A is higher than

supply voltage VIN, then the converter is a boost converter, and

the current slope is negative. Moreover, the power dissipation PD can be determined by the combination of two HS-switching

loss PH S and two conduction losses PC. In comparison with

the behavior of current Path 1, current Path 4, which delivers energy to output terminal VO B, exhibits the same

characteris-tics. Once the output terminals get enough energy from a supply source, current Path 1 expires. Then, as shown in Fig. 2, the HS-MOS SW4and the low-side (LS) MOS SW2 turnON. Path

2 is created to transfer storage energy to output terminal VO A.

Since the current paths connect the output terminals to ground, it has a negative current slope, as determined by the equation (VO A)/L. The LS-switching loss can be ignored because the

crossover voltage of LS-MOS is zero during the switching tran-sient. Therefore, the power dissipation of Path 2 is counted as one HS-switching loss and two conduction losses. Similarly, Path 4 exhibits the same performance for output terminal VO B.

As illustrated in Fig. 2, there are two special current paths Path 3 and Path 6, which are used to rapidly store and hold energy. When the output terminals of the SIDO converter require more energy from the supply source to boost output voltage level, the

HS-MOS SW1 and LS-MOS SW3are turned on to connect the

inductor with supply source and ground. It generates a positive current slope VIN/L and rapidly stores energy in the form of

inductor current. If the output terminals have a reduction in de-manded energy, current Path 6 keeps the storage energy of the inductor in. The LS-MOSs SW2and SW3are turned on to form

an inner current loop in the SIDO converter without delivering energy to output terminals. Therefore, the power dissipation is only in the two conduction losses of LS-MOSs.

Six current delivery paths can be simply classified into two categories. Current delivery paths that can increase the inductor current level belong to the first category. Current delivery paths that can decrease the inductor current level belong to the sec-ond category. This classification is shown by the symbols “+” and “−” in Table I. Depending on the increase or decrease of the inductor current level, the system stability can be guaran-teed if the inductor current level can be kept constantly below the desired current peak current level Ip eak. As a result, the

combination of the six current delivery paths can determine the current-controlling sequence. Furthermore, in order to react to fast load-transient response, the energy in the inductor will not be decreased to zero through the freewheeling path. With the ex-istence of the freewheeling stage, which is composed by Path 6, the system order is reduced to one and the compensation can be simplified to PI compensation. Therefore, the system band-width can be extended without being limited, unlike in previous literature [7], [8].

According to the demand of one buck and one boost out-put voltages in the SIDO converter, it follows that Paths 1, 3, and 4 must be kept in the structure [4]. Therefore, the transis-tors SW3, SW4, and SW5 are necessary. The transistors SW1

and SW2 can be removed to reduce the number of the power

switches. The freewheeling path disappears with the removal of transistor SW2. Therefore, a small transistor SW6 is added to

connect the two terminals of the inductor to form a freewheel-ing path. Accordfreewheel-ing to the reorganized structure, the function of current paths needs to be clearly defined. Paths 1 and 4 can respectively deliver energy from supply source to output termi-nals VO A and VO B. Path 1 increases the inductor current level,

but Path 4 decreases the inductor current level, as we let VO Abe

the buck terminal and VO Bbe the boost terminal. The difference

between Paths 1 and 3 is the increasing rate of the inductor cur-rent level. Path 3 works better than Path 1 if the inductor needs to rapidly increase without affecting output terminals. As a re-sult, the current-controlling sequence becomes Path 1, Path 3, Path 4, and Path 6, as shown in Fig. 3(a).

The adaptive controlling sequence of the previous work [4], as shown in Fig. 3(b), is used to properly regulate two output voltages. At the beginning of the switching period, Path 1 turns

ONand delivers energy to buck output VO A. The inductor current

simultaneously increases according to the listed current slope of Table I. Once the VO A gets enough energy QO A from the

supply source, the controller ends Path 1 and turnsONPath 3. This is to increase inductor current to the load-dependent peak-current control (LDPCC) level Ip eak, which is proportional to

the load condition of two output terminals and is determined by the LDPCC circuit in [4]. For the demand of boost output,

Fig. 3. (a) LDPCC controlling sequence in [4] and (b) the inductor current waveform of LDPCC controlling sequence.

Path 3 expires when inductor current is higher than the LDPCC level Ip eak, and Path 4 turnsONto deliver the required energy

QO B to boost output. As the boost output acquires enough

energy, Path 4 expires and the extra inductor current is reserved by Path 6. Overall, the current sequence properly delivers the required energy to each output terminal and effectively controls the inductor current without unexpected value [9] to regulate output terminals. Therefore, the cross-regulation issues can be minimized. Besides, if the current-decreasing capability due to Path 4 is smaller than the current-increasing capability due to Path 1, the inductor current will continuously increase, thus causing the SIDO converter to become unstable. In order to minimize this risk, the output loading of the boost terminal must be kept higher than that of the buck terminal. The supply voltage of the controller is thus connected to the boost terminal to increase its output loading. As a result, the risk of being unstable, which has been analyzed in [4], is reduced. However, the situation of unbalanced loading certainly exists in various load application, and the risk of instability cannot be avoided if we only depend on the energy demand of the controller. The hysteresis mode, which has been proposed, simultaneously turns

ONthe transistors SW1and SW6to avoid increasing the inductor

Fig. 4. Proposed LPDCC circuit in [4].

current with unbalanced loading. Furthermore, the buck terminal is regulated by a hysteresis voltage window at the cost of a large voltage ripple. The proposed method in this study, which increases the loading of boost terminal, alleviates the design constraint of the previous design [4], thus, further reducing the output ripple.

III. PROPOSEDALTC TECHNIQUE FORREDUCEDCROSS

REGULATION ANDPOWERCONSUMPTION

As discussed earlier, the surplus energy stored in the induc-tor affects the performance of cross regulation and power con-sumption. The LDPCC circuit, which was proposed in [4], can dynamically adjust peak current level Ip eak to determine the

surplus energy in the inductor. However, the inductor current level is not well defined due to the function of summation in the design of the LDPCC circuit. In this respect, an ALTC technol-ogy is proposed to accurately predict the peak current level and minimize cross regulation and power consumption. The detailed analyses of LDPCC and ALTC technology are described in the following sections.

A. LDPCC Circuit

In accordance with the proposal of previous work [4], the LDPCC level Ip eakneeds to follow the load variation and then

achieve high power efficiency. At light loads, a value of bias cur-rent IB ensures the small freewheeling current level, in order

not to waste energy. The LDPCC circuit, as depicted in Fig. 4, uses two error amplifiers E1and E2to monitor two output load

conditions. As a result, the error amplifiers’ output signals EO A

and EO B are converted to two current signals by the

voltage-to-current (V –I) converters. The summation current, which is composed by the two current signals and one bias current IB,

is converted by resistor Rp eakto a converted-signal Vp eak. And

then, the converted-signal Vp eak determines the LDPCC level

Ip eakand varies with load conditions. A minimum LDPCC level

can be set by IB to avoid zero-inductor current. For instance,

a dip in one of the output terminals due to an increase in load current will increase the duty ratio and indirectly cause an in-creasing LDPCC level. As we know, once the disappearance of the freewheeling stage happens when a sudden load current rises from light to heavy and the load current exceeds the maximum power limitation, the stability and output regulation will be dete-riorated, since the system order becomes two. The system stabil-ity cannot be guaranteed through the use of the PI compensation. Fortunately, the LDPCC technique can adaptively store suitable energy in the inductor to prevent the output from having a too

Fig. 5. Behavior of the proposed ALTC technique.

large transient dip voltage and ensure high power-conversion efficiency at light loads. Besides, the freewheeling period can be maintained in case of load variation after the adoption of the LDPCC technique. However, the LDPCC level is obviously not well defined due to the different weight of output voltage levels. As illustrated in Fig. 4, the LDPCC level Vp eakdirectly converts

from the output signals EO A and EO B of error amplifiers. In

order to compare with the same reference voltage Vref, there

have been different weight of the feedback ratios βAand βB in

the SIDO converter. As discussed earlier, the directly converted information will induce an exceeding current level to control the storage energy. It contradicts the purpose, which achieves high power efficiency, of SIDO converter. In this respect, the ALTC technique has been proposed to solve this problem in the following section.

B. ALTC Technique for Solving the Exceeding Current Problem In a nutshell, the SIDO converter uses two different ratios of feedback-divided resistors to regulate the two streams of output as one buck and one boost output voltages. The values of error amplifiers’ output EO Aand EO Bindicate the load conditions of

two output terminals and directly convert them to LDPCC level. Therefore, the problem of having an exceeding current occurs in the previous design. This easily causes higher freewheeling cur-rent, thus contradicting the requirement for power-conversion efficiency. Moreover, once the loading of buck output becomes higher than that of boost output, the increasing current level of Path 1 becomes higher than the decreasing current level of Path 4. The increasing inductor current causes serious cross regulation at the output terminals. A power detector circuit and delta-voltage generator in [4] has been proposed to address the current crowding issue and to switch on the hysteresis mode. At the hysteresis mode, Path 6 is used instead of Path 1 to regulate the buck output and output terminal VO A regulated by a

hys-teresis voltage window. Therefore, the increasing current can be addressed. Although the current crowding issue is addressed, the complex design of the power detector and delta-voltage gen-erator has a large chip area and high-power consumption. In this study, we take on the challenge of simultaneously addressing both the issues of exceeding current and current crowding, pro-viding a simple and adaptive solution.

Fig. 5 illustrates how the load condition at the buck output changes from heavy to light, while the load condition at the boost output changes from light to heavy. The output signals

EO A and EO B of error amplifiers reacts to the original load

condition without correction. The summation of signal VLD PC C

always keeps at the same level and even increases slightly to a higher level. Obviously, the LDPCC level is over defined to control peak current level. In order to solve the problem of exceeding current, the ALTC technique is proposed to automat-ically determine the inductor current level through the weight of error amplifiers’ output EO A and EO B. Therefore, a weighted

value mEO A is proposed to redefine the inductor current level,

since the output voltages VO A and VO B have different values.

The proportional ratio m is defined as the ratio of VO A/VO B.

The weighted value mEO A shifts the original crossover point

P1 to a new crossover point P2 and indicates an accurate and

suitable transition point of operation mode. Moreover, if the hysteresis mode is turned on, the buck output is regulated by a hysteresis window, thus not increasing the inductor current. The ALTC level thus needs to follow the demand of the boost output when operating in the hysteresis mode. Since the stored energy needs to be delivered to the boost output VO B, the ALTC

cur-rent adjusts according to the weight of error amplifiers’ output EO B. Once the required energy of the boost output is higher

than that of the buck output, the operation mode of the SIDO converter switches to the pulsewidth modulation (PWM) mode. As a result, the ALTC current follows the two weights of error amplifiers’ output mEO A and EO B, since the energy stored in

the inductor needs to be delivered to the two output terminals VO A and VO B. Furthermore, the storage current of buck output

VO A can be delivered to the boost output VO B. The

summa-tion current level between output signals mEO A and EO B is

switched to indicate the ALTC level. Therefore, the real load condition can be indicated by the signal VA LT C, which will not

result in an exceeding inductor current. Above all, the corrected weight of error amplifiers’ output mEO A and EO B reflects the

actual load condition. The crossover point P2can be used to

de-fine the boundary of hysteresis and PWM mode. This is easily implemented by a simple comparator circuit.

IV. IMPLEMENTATION OFPROPOSEDSUB-1 V SIDO CONVERTER

The block diagram of the proposed sub-1 V SIDO dc–dc converter with the ALTC technique is illustrated in Fig. 6. Tran-sistors MN, MF, MA, and MB constitute the minimum-switch

structure in order to reduce the power loss and chip area. Output voltages are directly monitored by the ALTC controller and con-vert the load condition to the proposed ALTC level. The output signals of the ALTC controller connect to a charge reservation circuit, which was proposed in [4], to generate the duty cycle of each output terminal and detect the inductor current level. The charge reservation circuit synchronously records the deliv-ered energy on the inner capacitors and uses this to compare with output signals of error amplifier and current sensor. The digitized control signal, which is converted by charge reserva-tion circuit, is connected to a sequence controller. The output of the sequence controller is then converted by a fixed dead time driver to eliminate shoot-through current in case of switch-ing issues and drives the power MOSFETs. Durswitch-ing dead time

Fig. 6. Proposed structure of sub-1 V input SIDO dc–dc converter with ALTC technique.

operation, the voltage level of node VX will be higher than the

input voltage VIN and the two output voltages VO A and VO B.

It will result to a potential latch-up issue if the bulk voltage of p-type power MOSFETs does not connect to the highest voltage of its drain or source voltage. Hence, an adaptive body switch (ABS) circuit is proposed to decrease the possibility of leak-age current and the potential latch-up problem of p-type power MOSFETs [6]. Once the input voltage VINis lower than 1 V at

the start up of the SIDO converter, a reliable, stable, and low-quiescent current power-on sequence is required to judge the start-up performance. In this respect, a self-bias current source (SBCS) circuit is proposed to bias a current-mode ring oscillator in order to generate a nearly constant clock with the character-istic of high power supply rejection ratio (PSRR). The start-up procedure and design consideration of each block in the sub-1 V SIDO dc/dc converter are described in the following section. A. Start-up Procedure for the Sub-1 V Operation

In order to achieve the sub-1 V operation, a low-voltage power-on procedure has been proposed, as shown in Fig. 7. The power-on procedure is divided into four stages: Stage 0 to Stage 3. In Stage 0, the converter is disabled, unless the supply voltage VINhas been charged to the minimum operating voltage

of SBCS circuit. When the condition of Stage 0 is satisfied, the power-on sequence then turnsONthe power MOSFETs MF and

MB to deliver energy to output terminal VO B. The voltage of

output terminal VO B is ramped up to 90% of the supply voltage

VIN during Stage 1. Then, power-on procedure enters Stage 2,

which turns ONthe starter, the SBCS circuit, and the ring os-cillator, according to priority. The generated clock signal Clock is used in boost terminal VO B until the regulated voltage level

reaches the 90% of the predefined voltage. At Stage 2, only the ring oscillator and driver are enabled; the open-loop control is used to regulate output voltage. In order not to exhibit an over-shot voltage during start-up transition, the clock has a duty cycle of 50%, with a limitation of twice the necessary supply voltage. When the voltage level of terminal VO B is higher than

Fig. 7. Power-on procedure of sub-1 V input SIDO dc–dc converter with ALTC technique.

1.65 V, which is the 90% voltage level of the predefined voltage, the ALTC controller is enabled and added into the control loop to form a closed-loop control. At this time, the ring oscillator behaves as a system clock generator. The output terminals VO A

and VO B are finally regulated by the ALTC controller to the

defined voltage level. Therefore, the power-on sequence prop-erly controls the converter to be modulated by the power-on procedure circuit and the ALTC controller until two output volt-ages successfully ramp up to the regulated levels. The power-on sequence is therefore an important part of sub-1 V operation. B. Start-up Circuit and the Ring Oscillator With a SBCS

During the start-up period, an auxiliary ring oscillator neces-sary to generate a clock signal can initiate the operation, since the ramp-up input voltage is not high enough to ensure the correct closed-loop operation. In a conventional sub-1 V con-verter, the oscillating frequency of the auxiliary ring oscillator depends highly on the supply voltage deviation and operates at several megahertz, sometimes even at tens of thousands mega-hertz. Such a high switching frequency increases the possibility of latch-up and induces too much switching loss and may cause the start-up procedure to fail. Besides, the closed-loop normally operates when the main ring oscillator takes over the character of the auxiliary ring oscillator after the start-up procedure is fin-ished. This shows that two oscillators are needed, and thus, the cost and the silicon area are increased. As depicted in Fig. 8, the proposed start-up circuit can solve certain design problems and guarantees the success of start-up procedure. In order to address

Fig. 8. Proposed SBCS circuit and ring oscillator.

latch-up and switching loss issues, as well as to simplify the design of oscillator, an SBCS circuit drives a current-mode ring oscillator to generate a nearly constant clock CLK. Transistors S1–S5 and capacitor CS constitute a starter. At the beginning

of Stage 2 of the power-on sequence, the voltage VS is too low

to turnONthe transistors S3–S5, the SBCS circuit starts when

the supply voltage is higher than the threshold voltage of p-type MOSFET. A simple current mirror that is composed of tran-sistors M1–M4 and a resistor R1 is used to define the biasing

current IB. Transistors M5–M7 and the resistor R2 constitute

a self-bias loop to provide a preregulated voltage to supply the simple current mirror. Since the preregulated voltage VB

is clamped to a value of VT + VG SP and the threshold voltage

VT is independent of the supply voltage, a nearly constant bias

current IB is therefore generated to bias the current-mode ring

oscillator without being affected by the supply voltage devi-ation. Furthermore, the oscillation frequency of current-mode ring oscillator depends on the bias current IB and the threshold

voltage VT of the n-channel MOSFET (NMOS). Therefore, the

SBCS circuit and the ring oscillator can attain high PSRR. The oscillation frequency will not increase to a higher value and switching loss can be reduced. The start-up procedure can also be guaranteed without being affected by the high-switching loss. Once bias current IB is generated, a mirrored current IS flows

through the transistor S2, pulls the value of VS to a high level,

and the start-up procedure ends. Here, the problems associated with a ring oscillator operated at high frequency and an extra regular oscillator are addressed and serious problems that were never pointed out in conventional designs can be solved [1]–[3]. The sub-1 V SIDO converter can be started and operated with low-power consumption.

C. ABS Circuit

A voltage spike still appears at node VX in Fig. 6 even if a

well-defined dead time is inserted during the switching transi-tion. As a result, the voltage level at node VX may be higher

than the input voltage VIN and the two output voltages VO A

and VO B. Unfortunately, this will induce a potential latch-up

issue because the bulk voltage of the p-type power MOSFETs is not connected to the highest voltage. The latch-up phenomena may damage the chip and cause function failure. Thus, an ABS

Fig. 9. Proposed ABS circuit in [10].

circuit is needed to connect the bulk terminal to the highest volt-age. In previous ABS circuits [10], the complex circuit is used to distinguish which terminals have the highest voltage. This has the disadvantage of lowering the converter’s performance and immunity to the latch-up phenomena, while at the same time inducing higher power consumption. In this paper, the ABS cir-cuit depicted in Fig. 9 is proposed to address the possibility of current leakage and the potential latch-up problem of p-type power MOSFETs [6]. The ABS circuit with the simplest struc-ture provides low-power consumption, high decision speed, and high accuracy of voltage comparison even if the source and drain voltages are nearly equivalent. In Fig. 9, transistors M1

and M2are used to bias transistors M3and M4 at the boundary

of cutoff and inversion regions to improve the capability in order to determine which terminals has the highest performance. The transistors M3 and M4 work as two common-gate amplifiers.

Once node VX is higher than output terminal VO, the transistor

M4 enters the inversion region and fully turns ON. The

tran-sistor M3 enters the cutoff region and turnsOFFentirely. The

n-well voltage VB of the p-type power MOSFET connects to

node VX. Contrarily, when output terminal VO is higher than

node VX, the transistor M3fully turnsONand the transistor M4

enters the cut-off region. The bulk node VB is connected to

out-put terminal VO. Therefore, the ABS circuit can automatically

select the highest voltage level between the drain and source terminals of a p-type power MOSFET. The potential of latch-up occurrence can be completely eliminated. Interestingly, the power consumption merely involves two biasing currents. The advantage of low-power consumption is achieved as compared to previous ABS circuits [10], [11].

D. ALTC Controller

According to the functionality of ALTC technique as shown in Fig. 5, the implementation of the ALTC circuit is illustrated in Fig. 10. The operational transconductance amplifier (OTA) gm Aconverts the difference between the output voltage VO Aand

the reference voltage Vref to a current signal IA. The weighted

factors βA and βB come from the feedback-divided resistors.

Similarly, current signal IB is converted from the difference

between the output voltage VO B and reference voltage Vref

through the OTA gm B. Current signals IAand IB can therefore

be expressed as follows:

IA = (βAVO A − Vref)gm A (1)

Fig. 10. Proposed ALTC Circuit.

Equations (1) and (2) indicate the load conditions of two out-put terminals VO Aand VO B, respectively. Assume that the gmA

is equal to gmB because of good layout matching

considera-tions. The corrected ratio m defined as (3) can then be used to represent the relationship between the output voltages VO Aand

VO B. The bias current I1is used to define the minimum inductor

current level and to avoid the negative current. Therefore, the converting currents IA 1 and IB 1 can be expressed as (4) and

(5), respectively. The inductor current level VA LT C is defined

by (6), which is converted by the current mirrors and the resistor RA LT C βAVO A = βBVO B ⇒ βB βA = VO A VO B = m (3) IA 1= I1− IA = I1− (βAVO A − Vref) gm A (4) IB 1= I1− IB = I1− (βBVO B − Vref) gm B (5) VA LT C = RA LT C
1 mIA 1+ IB 1 

when boost energy > buck energy

VA LT C = RA LT CIB 1when boost energy < buck energy. (6)

The weighted current IA 1/m is used to adjust the energy of

the buck output and relate to that of the boost output. At PWM operation, the energy of the boost output is larger than that of the buck output. The ALTC circuit selects the summation value as the storage energy in the inductor, which is shown in (6). As a result, the value of VA LT Chas a step wherein the SIDO converter

enters PWM operation to ensure sufficient stored energy in the inductor. On the other hand, the hysteresis operation addresses the current crowding issue in the inductor. Thus, the buck output acquires energy through the turning-ONtransistors MF and MA

shown in Fig. 6, and will therefore not increase inductor current. The ALTC level is therefore necessary to determine the energy demanded of boost output; the value of VA LT C is merely

calcu-lated by the product of IB 1 and RA LT C. In Fig. 10, the current

comparator is used to decide the operation mode, instead of the power comparator and delta-voltage generator in [4]. If IA 1/m

is larger than IB 1, M D is set to high state and VA LT Cis decided

only by IB 1. Contrarily, if IA 1/m is smaller than IB 1, M D is

equal to low state, then VA LT C is decided by the summation of

Fig. 11. Current sensor and the charge reservation circuits in [4] for controlling duty cycle of each output terminal.

IA 1/m and IB 1. Therefore, the crossover point P2, as shown in

Fig. 5, can indicate an accurate load condition. The boundary condition of the hysteresis mode is easily defined by the pro-posed ALTC technique without using numerous analog circuits. The exceeding current problem can also be improved.

E. Charge Reservation Circuit and the Current Sensor As shown in Fig. 6, the charge reservation circuit receives the output signals of the ALTC circuit and current sensor. It then digitizes the received signal to the sequence controller to generate related inductor current. The current sensor is depicted in Fig. 11, and the sensing resistor RSENis set to 0.5 Ω to reduce

power consumption. A large resistor RS, which is N times the

sensing resistor RSEN, is used to reduce the power consumption

of current sensor [4]–[6]. In the ALTC technique, since the current sensor cannot be turned off during the whole switching period, the freewheeling switch MF is connected between the

input power source and the node VX. This ensures that the

operation of the current sensor can be maintained during entire switching period. However, the consequence of this is that the small sensing resistor RSENslightly decreases power efficiency

during the switching period. Moreover, the ALTC technique can dynamically adjust the peak inductor level, and thus, improve power efficiency. According to the sensing resistor ratio, the sensing current ISEN has 1/N times of the inductor current

IL. It is mirrored to charge the inner capacitors C1 and C2 of

the charge reservation circuit, which is shown in Fig. 11. The voltage VR S converts from sensing current ISENand the resistor

RI L is compared with the ALTC level VA LT C to determine the

operation period of Path 3. As a result, the energy stored in the inductor will be increased to the peak value defined by the ALTC technique. Moreover, the sensing current ISEN is

also used to determine the individual operation periods of the buck and boost output terminals. The inner capacitors C1 and

C2 are used to monitor the buck and boost output voltages,

respectively. The sensing current ISEN flows into capacitor C1

or C2, to indicate the energy delivery condition of the buck

or boost output voltage when the voltage level of SA or SB

is changed from high to low. The voltages VC 1 and VC 2 on

capacitors C1 and C2 are compared with the output signals

Fig. 12. PWM control logic generator and the mode switch controller.

period for related current path. Once the voltages VC 1and VC 2

are respectively larger than output signals EO A and EO B, the

driving signals SA and SB, change from low to high and the

inner capacitor is fully discharged. Thus, the charging time of inner capacitors C1and C2indicates the operation period of the

related current path. As a result, the duty cycle of each output terminal can be determined by the voltages VC 1and VC 2on the

inner capacitors C1 and C2, and the output signals EO A and

EO B. The digitized-values CMN, CMA, and CMBare used to

decide the operation period of each energy delivery path through the use of the sequence controller and the dead time driver. F. Sequence Controller and the Dead Time Driver

The sequence controller depicted in Fig. 12 is used to gener-ate the current-controlling sequence for energy delivery to each output terminal. The operation of the sequence controller can determine four durations, which are Paths 1, 3, 4, and 6, cor-responding to the four energy delivery paths in Fig. 3. At the beginning of Path 1, the sequence controller is triggered by a positive edge of clock signal CLK that has duty cycle of 90%. The energy can be delivered to the buck output through Path 1. Once CMA, which is determined by charge reservation circuit,

is set from high to low, the energy delivery Path 1 is ended and Path 3 is triggered to store enough energy to the inductor. During the interval of Path 3, the inductor current rapidly increases to the ALTC level. When the current-sensing signal VR S is higher

than the ALTC level VA LT C, the signal CMN, is set from high

to low by the charge reservation circuit, and the energy delivery path changes to Path 4. According to the duty cycle of Path, 4 which is determined by the charge reservation circuit, Path 4 properly delivers energy to the boost output terminal VO B. Once

the voltage VC 2 is higher than error the signal EO B, CMB is

set from high to low and the energy delivery of Path 4 ends. Consequently, the controlling sequence enters Path 6, which is the freewheeling stage. In other words, the surplus energy is reserved in the form of inductor current. All the output signals DA, DN, DB, and DF of the sequence controller are converted

by the dead time driver, as shown in Fig. 13, to the gate driv-ing signals SA, SN, SB, and SF, respectively. The dead time

driver contains a level shifter, which raises the boost output voltage for fully turningOFFthe power MOSFETs. The driver is composed of a nonoverlapping circuit, which helps to avoid the shoot-through issue during the switching transition of differ-ent currdiffer-ent paths. These gate-driving signals are used to switch

Fig. 13. Dead time driver.

Fig. 14. Micrograph of proposed sub-1 V SIDO dc–dc converter with ALTC technique.

the power MOSFETs MA, MN, MB, and MF. The hysteresis

mode addresses the current crowding issue by having a struc-ture with the least switches and is triggered by the hysteresis mode selector. The signal M D generated by the ALTC circuit in Fig. 10, and an AND gate AND3shown in Fig. 12, constitute

the hysteresis mode selector. When the load condition of buck output VO A is larger than that of boost output VO B, the output

signal M D is set to a high state for entering the hysteresis mode. Inversely, if the signal M D is in the low state, the PWM mode is selected. At hysteresis mode, the switches MF and MAdirectly

connects the power supply to VO A, with a slightly increased

output ripple to ensure system stability. However, the important issue is that the power source of the controller comes from the boost output, i.e., the possibility of the buck energy being larger than the boost energy is reduced. The converter seldom enters the hysteresis mode after the deliberated power consideration.

V. EXPERIMENTALRESULTS

The chip micrograph of the proposed sub-1 V SIDO dc–dc converter with the ALTC technique, as shown in Fig. 14, was fabricated via 0.25 µm 2.5 V/5 V process. The threshold voltages of NMOS and PMOS are 0.48 and −0.6 V, respectively. The

Fig. 15. Step load condition at buck output VO A.

Fig. 16. Step load condition at boost output VO B.

Fig. 17. Line-transient response at IO A = IO B = 10 mA.

chip area is 1312× 1590 µm2_{. The input supply voltage is 1 V}

and the two output voltages are set to 0.6 V as buck output and 1.8 V as boost output.

In Fig. 15, a load current step of 100 mA is applied to the buck output VO Ato measure the load-transient performance and

cross regulation of the two output terminals. The value of VO B

is merely affected by the load change at the output VO A, since

the ALTC technique can dynamically adjust the inductor current level. According to the hysteresis mode operation, the current crowding issue is addressed when the buck energy is larger than the boost energy. On the other hand, Fig. 16 shows a 100-mA step load condition at the boost output VO B. The cross

regula-tion at the output VO Ais worse than the result shown in Fig. 15,

since the power of the controller comes from the boost output. As a result, the cross regulation becomes worse in cases of load variation. Fig. 17 shows the measurement results of the line-transient response. A stepping voltage, which changes from 1 to 1.5 V, is applied to the sub-1 V SIDO converter and vice versa. As illustrated in Fig. 17, the output terminal VO B shows a good

performance during line transient. However, the output termi-nal VO A has a slight drop in voltage level. The voltage drop is

caused by the resolution of the charge reservation circuit, since the different supply voltage level causes the different conver-sion ratio. Therefore, there is a tradeoff with voltage headroom, output ripple, and cross regulation.

Fig. 18 shows the stable inductor current waveform of the ALTC technique in steady state. Obviously, the controlling

se-Fig. 18. Inductor current-control sequence in steady state.

Fig. 19. Measurement results of the proposed ABS circuit in steady state.

Fig. 20. Proposed power-on sequence.

quence is consistent with the desired inductor waveform to re-duce output ripple, cross regulation, and power loss. The mea-sured load regulations of the output terminals VO A and VO B

are 0.24 and 0.39 mV/mA, respectively. The voltage at the node VX has a large voltage swing in the design of sub-1 V SIDO

converter. The proposed ABS circuit can ensure that the bulk of the p-MOSFET always can be tied to the highest voltage. Thus, the leakage due to the parasitic diode can be avoided and the efficiency can be improved.

Fig. 19 shows the measurement result of ABS circuit. In com-parison with the performance of the ABS circuit with the previ-ous works [10], [11], we used a triangular waveform as an input to compare with a constant reference voltage of 2 V. We found that the output waveforms contain undershoots/overshoots in voltage during the switching regions due to the slow response of the previous designs. The crossover point of test waveforms of the proposed ABS circuit exhibited smooth transition to the

Fig. 21. Power efficiencies of (a) the conventional SIDO converter and (b) the proposed SIDO converter with the ALTC technique. TABLE II

PERFORMANCE OFPROPOSEDSIDO DC–DC CONVERTER

maximum voltage between the input terminals. Furthermore, the measured quiescent current of 6 µA is proposed in an ABS circuit, while the previous designs in [10] and [11] needed 56 and 15 µA, respectively. Furthermore, the circuit complexity in [11] occupies a large silicon area. Therefore, the proposed ABS circuit alleviates potential leakage and latch-up, which oc-curs at the bias of the N -well that needs to connect to the highest supply voltage, in order to design on-chip power switches. Cer-tainly, fast response and low-power consumption are achieved in this design.

Fig. 20 shows the power-on procedure when the proposed start-up mechanism is adopted. The power-on procedure is di-vided into four stages. At Stage 0, the supply voltage ramps up to the p-MOSFET threshold voltage VT H P. The sub-1 V

SIDO dc–dc converter is disabled since the supply voltage is not high enough. When the supply voltage is larger than VT H P,

the power-on procedure starts to directly deliver energy to the boost output VO B through the power MOSFETs MF and MB

at Stage 1. At Stage 2, the ring oscillator is enabled to generate the switching clock CLK with a 50% duty cycle. The fixed clock boosts the output terminal VO B to about 1.65 V, which is 90%

of the regulated output voltage. Then, the closed loop takes over the rest of the task of boost regulation at Stage 3. Simultane-ously, the power-on procedure also starts to regulate the buck output voltage VO A.

Fig. 21(a) represents the measurement result of the conven-tional SIDO converter illustrated in Fig. 2. It shows poor power efficiency at light load condition. Since the conventional struc-ture has two power MOSFETs in the energy delivery path, the

measurement result only presents with a 90% maximum effi-ciency. Fig. 21(b) shows the measurement results of the pro-posed sub-1 V SIDO dc/dc converter with ALTC technique. A comparison of the power efficiency between the conventional and the proposed SIDO converters shows a power efficiency im-provement from 65% to 85% at light load condition. Moreover, the proposed sub-1 V SIDO dc–dc converter shows more than 90% efficiency in all load conditions except in the hysteresis mode. As the energy delivery path does not flow through the inductor in hysteresis mode, the conversion efficiency drops to 85%. The performance of the proposed sub-1 V SIDO dc–dc converter with the ALTC technique is summarized in Table II.

VI. CONCLUSION

In this paper, an effective ALTC technique is proposed. In the proposed ALTC technique, the ALTC current level VA LT C

properly stores enough energy in the inductor current. Hence, the sub-1 V SIDO dc–dc converter achieves high conversion efficiency without over storage of energy. Moreover, the ALTC technique also minimizes cross regulation during the load tran-sitions of two output terminals. A current-mode ring oscillator with the proposed SBCS circuit simplifies the design of power-on sequence. It generates a nearly cpower-onstant clock to simplify the design of the internal oscillator. The test chip was fabricated via Taiwan Semiconductor Manufacturing Company 0.25 µm 2.5V/5V Bipolar-CMOS-DMOS process, and experimental re-sults showed efficiencies of 85% and 92% at light and heavy loads, respectively, with a cross regulation smaller than 10 mV.

ACKNOWLEDGMENT

The authors would like to thank Chunghwa Picture Tubes, Ltd., for their help.

REFERENCES

[1] A. P. Chandrakasan, D. C. Daly, J. Kwong, and Y. K. Ramadass, “Next generation micro-power systems,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2008, pp. 2–5.

[2] C. Y. Leung, P. K. T. Mok, and K. N. Leung, “A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies,” IEEE J.

[5] Y.-J. Woo, H.-P. Le, G.-H. Cho, G.-H. Cho, and S.-I. Kim, “Load-independent control of switching DC–DC converters with freewheeling current feedback,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2798– 2808, Dec. 2008.

[6] M.-H. Huang and K.-H. Chen, “Single-inductor dual buck-boost output (SIDBBO) converter with adaptive current control mode (ACCM) and adaptive body switch (ABS) for compact size and long battery life in portable devices,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2009, pp. 164– 165.

[7] D. Ma, W.-H. Ki, and C.-Y. Tsui, “A pseudo-CCM/DCM SIMO switching converter with freewheel switching,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1007–1014, Jun. 2003.

[8] D. Ma, W.-H. Ki, C.-Y. Tsui, and P. K. T. Mok, “Single-inductor multiple-output switching converters with time-multiplexing control in discontin-uous conduction mode,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 89–100, Jan. 2003.

[9] S.-C. Koon, Y.-H. Lam, and W.-H. Ki, “Integrated charge-control single-inductor dual-output step-up/step-down converter,” in Proc. IEEE Int.

Symp. Circuit Syst., May 2005, vol. 4, pp. 3071–3074.

[10] D.-S. Ma, “Automatic substrate switching circuit for on-chip adaptive power-supply system,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 54, no. 7, pp. 641–645, Jul. 2007.

[11] M.-H. Huang, P.-C. Fan, and K.-H. Chen, “Low-ripple and dual-phases charge pump circuit regulated by switched-capacitor based bandgap refer-ence,” IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1161–1172, May 2009.

Ming-Hsin Huang was born and raised in Kaohsiung, Taiwan. He received the M.S. degree in the Department of Electrical Engineering from the National Changhua University of Education, Taiwan, in 2002 and the Ph.D. degree in the De-partment of Electrical and Control Engineering Na-tional Chiao Tung University, Hsinchu, Taiwan, in 2009.

He is currently with the Taiwan Semiconductor Manufacturing Company, Hsinchu. His research in-terests include the power management integrated cir-cuits (PMICs), light emitting diode (LED) drivers, television (TV) backlights, switching-mode power supplies (SMPS), and high/low voltage integration process.

poration, Chupei City, Taiwan. He is a Member of the Mixed Signal and Power Management IC Lab-oratory, National Chiao Tung University. His research interests include the power-management-integrated circuit design and the analog-integrated circuits.

Ke-Horng Chen (M’04–SM’09) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.

From 1996 to 1998, he was a Part-Time IC De-signer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power management integrated circuits (ICs). He is currently an Associate Professor in the Department of Electrical Engineering and Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 85 papers published in journals and conferences and also holds several patents. His research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display TV, red, green, and blue color sequential backlight designs for optically com-pensated bend panels, and low-voltage circuit designs.