Guest Editorial: Special Issue on Design and Programming
of Signal Processors for Multimedia Communication
Yen-Kuang Chen&David W. Lin&John V. McCanny&
Edwin H.-M. Sha
Published online: 12 January 2008
# 2008 Springer Science + Business Media, LLC. Manufactured in the United States This special issue addresses some of the technical
chal-lenges in the design and programming of signal processors for multimedia communication. The past decade has witnessed astonishing growth in Internet usage, penetration of mobile phone service, and proliferation of communica-tion-ready portable devices. All these are whetting the appetite of the populace for more convenient and ubiqui-tous access to multimedia information, at a higher quality than previously available. The development of terminal equipment to meet such demand presents a significant technical challenge, considering that it is highly desirable that the equipment be cost effective, power efficient, versatile, and extensible for future upgrades. Over time, signal processors have become an indispensable part in such equipment. For example, a recent study shows that 90% of the SoC products in 130 nm technology have at least one programmable processor. Nonetheless, there are challenges in the design and programming of signal processors for
multimedia communication, in particular, (1) general-purpose signal processor design, (2) application-specific signal processor design, (3) operating systems and program-ming support, and (4) application programprogram-ming. To address the concerns, six papers are included in this special issue.
This issue opens with two general-purpose signal processor designs. To meet the diverse computing require-ments while achieving high computational and energy efficiencies, the system architectures presented here provide desired features via two different approaches: (1) novel micro-architecture in the DSP cores and (2) reconfiguring computational circuits.
& In “Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications,” Lin et al. present a novel signal processor design for high computational efficiency and low cost. It has a ping-pong register file design where 16 data registers are dynamically partitioned into ping and pong banks. The ping-pong register file design saves significant silicon area and access time over a traditional centralized design. The design also has a hierarchical instruction encoding scheme which could further reduce the code size. & In “Implementation of a Coarse-Grained
Reconfigura-ble Media Processor for AVC Decoder,” Mei et al. describe a special kind of signal processor architectures, which combines a reconfigurable architecture and a VLIW engine. Additionally, the paper presents a comprehensive solution, including a C-based compila-tion flow, VLSI design evaluacompila-tion and FPGA-based emulation. Detailed performance analysis of an H.264 video decoder design is conducted to illustrate its capability. The paper demonstrates the benefit of coarse-grained reconfigurable processor and the feasi-bility of a C-based design flow.
J Sign Process Syst (2008) 51:207–208 DOI 10.1007/s11265-007-0159-1
Y.-K. Chen (*) Intel Corporation, Santa Clara, CA, USA
e-mail: firstname.lastname@example.org D. W. Lin
National Chiao Tung University, Hsinchu, Taiwan, Republic of China e-mail: email@example.com J. V. McCanny
Queens’ University Belfast, Belfast, Northern Ireland, UK e-mail: firstname.lastname@example.org E. H.-M. Sha
University of Texas at Dallas, Richardson, TX, USA e-mail: email@example.com
In addition to high flexibility to a broad domain of application, an alternative approach is to build an applica-tion-specific signal processor. In this case, it can deliver the required performance with the lowest cost or highest efficiency.
& In “An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor,” Wang and Li describe an area-efficient design of a variable-size FFT processor. The size of FFT is programmable so that it can be used for various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting- handheld (DVB-H). To make the proces-sor area-efficient, it reduces the number of non-trivial multipliers and optimizes the realization by substructure sharing.
Beyond the underlying hardware and software to run on the hardware, it is also important to have operating systems and programming support.
& In “Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch,” Hsieh et al. propose a mechanism for reducing the context switch overhead. The proposed optimization scheme imple-ments a probability cost model in the compiler to partition the registers based on the life range informa-tion. When the contexts are divided into several sets, the OS can just save and restore part of the registers instead of the whole context when performing task switching.
& In “Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores,” Lin et al. discuss the compiler design for the PAC DSP. The clustered architecture design and distributed ping-pong register files in the PAC DSP raise new challenges of code generation. Thus, the authors develop a new register allocation scheme based on simulated annealing and other retargeting optimiza-tion phases that achieve effective code generaoptimiza-tion. This issue concludes with one application case study to illustrate the application programming issues and solutions on a modern DSP.
& In “Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP,” Lee et al. discuss the design and programming of variable block size motion estimation for H.264 on Texas Instruments’ DSP. The authors demonstrate several techniques, e.g., loop length in-crease, non-aligned memory load reduction, and pack/ unpack minimization, to optimize the performance by one order of magnitude. Software engineers, who work on media processing, can use these techniques to improve the implementation.
In short, we hope that this Special Issue provides enlightening information to the community in a timely fashion on the design and programming of signal proces-sors for multimedia communication. We would like to thank the authors for their excellent contribution. We also appreciate the reviewers for their constructive comments.