A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 11, NOVEMBER 2010 2227

A DVS Embedded Power Management for High

Efficiency Integrated SoC in UWB System

Yu-Huei Lee, Student Member, IEEE, Yao-Yi Yang, Student Member, IEEE, Ke-Horng Chen, Senior Member, IEEE,

Ying-Hsi Lin, Shih-Jung Wang, Student Member, IEEE, Kuo-Lin Zheng, Po-Fung Chen,

Chun-Yu Hsieh, Student Member, IEEE, Yu-Zhou Ke, Yi-Kuang Chen, and Chen-Chih Huang

Abstract—The proposed power management module with a typ-ical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can pro-vide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm2silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.

Index Terms—DC-DC converter, dynamic voltage scaling, low-voltage operation, power conversion efficiency, power man-agement, transient response, UWB system.

I. INTRODUCTION

V

ARIOUS multimedia and portable devices claim low power consumption, high performance, compactness, and robustness all at the same time. These claims force IC de-signers to encounter several challenges that must be overcome in system-on-chip (SoC) integration, especially in power man-agement. There are two important issues in the conventional design of power management module [1]–[6] for portable communication SoC applications such as ultra-wideband (UWB). One is low power consumption for extending battery lifetime [7], and the other is a demanding requirement in both steady state and transient response. The SoC design follows the trend of integrating an embedded power management module [8], [9] in order to reduce print-circuit-board (PCB) area and enhance power conversion efficiency. Recently, the new integrated technique for SRAM of Sub- microcontroller in 65 nm technology tailored for very high digital density

Manuscript received January 25, 2010; revised March 08, 2010; accepted June 01, 2010. Date of current version October 22, 2010. This paper was ap-proved by Guest Editor Mototsugu Hamada.

Y.-H. Lee, Y.-Y. Yang, K.-H. Chen, S.-J. Wang, K.-L. Zheng, P.-F. Chen, C.-Y. Hsieh, and Y.-Z. Ke are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan (e-mail: khchen@cn.nctu.edu.tw).

Y.-H. Lin, Y.-K. Chen, and C.-C. Huang are with Realtek Semiconductor Corporation, Hsinchu, Taiwan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2010.2063610

and mixed-signal integration applications was presented in [10] with a switched-capacitor structure. However, in contrast to the inductor-based structure, switched-capacitor structure with low driving capability is not suitable for UWB system applications [11], [12]. The inductor-based structure in the conventional power management module [1]–[6] has good driving capability. To further reduce the silicon area and attain a compact integration size with the UWB system, the proposed power management module, which is fabricated by 65 nm tech-nology, adopts low-voltage core devices in the controller design under low-voltage operation. Inevitably, the implementation of deep-submicron devices for analog circuit results in more design challenges.

As conceptually illustrated in Fig. 1, the embedded power management module in the UWB system contains two in-dividual power sources, and , to supply radio frequency (RF) and digital circuits, respectively. This proposed architecture minimizes the demand for high-voltage I/O devices by means of a low-voltage PWM (LV-PWM) controller with an on-chip compensation method. Moreover, a self-biasing mechanism is implemented in the proposed power management module to effectively improve efficiency and extend battery life. Furthermore, a linear regulator is adopted in the power source of RF circuits to suppress the switching noise from DC-DC converter. For the consideration of performance and layout flexibility, the linear regulator for RF blocks is not included in this power management.

Dynamic voltage scaling (DVS) function is an effective so-lution to reduce the power consumption of the digital systems especially in the low-power circuit design or the SoC integra-tion [13]–[15]. In the UWB system, if the throughput constraint is cycling between different operating modes, then dynamically adjusting the supply voltage can achieve efficient power saving. As reported in [15], the silent mode and the transmission mode of the wireless sensor node and SRAM need the DVS function. In UWB system operation depicted in Fig. 2, there is no data in the vacant transmission time slot during the data transmis-sion procedure. The DVS function can lower down the supply voltage to minimize power consumption and return it to the stan-dard value before data transmission. Thus, the DVS embedded power management is a good solution to achieve the different power request from the UWB system and consequently derive a suitable power source. The specifications of the power manage-ment for UWB system is illustrated in Table I.

In this paper, the structure of the proposed power manage-ment module with the LV-PWM controller is described in 0018-9200/$26.00 © 2010 IEEE

Fig. 1. The architecture of the proposed embedded power management module in UWB systems.

Fig. 2. The DVS function in UWB system operation.

Section II. The detailed circuit implementation of the pro-posed power management module is shown in Section III. Experimental results and the chip prototype are presented in Section IV. Finally, a conclusion of the proposed power management module is given in Section V.

II. POWERMANAGEMENTMODULEWITH THELOW-VOLTAGE PWM CONTROLLER

The proposed power management module is shown in Fig. 3. It contains the pre-regulator, the low-voltage PWM (LV-PWM) controller, the dynamic voltage scaling (DVS) function and the post-regulator. In this proposed structure, a step-down DC-DC converter is utilized to transfer the input voltage to the first output , typically 1.8 V, for RF and mixer circuit in the UWB system. In addition, the post-regulator, which is imple-mented with the low-dropout regulator, is placed behind the to generate the second output voltage , typically 1.2 V, for digital function blocks in the UWB system.

The pre-regulator, composed of the switched-capacitor (SC) converter and a low-dropout regulator (LDO) circuit, supplies a stable, noiseless, and regulated voltage to the LV-PWM controller from the input high voltage supply. The LV-PWM controller is implemented by core devices in the 65 nm tech-nology and supplied by 1.2 V from the pre-regulator. More-over, a power-efficient handover circuit in the pre-regulator can

achieve the self-biasing mechanism in order to reduce power dissipation of the pre-regulator when the second output voltage

is regulated after the start-up period.

The LV-PWM controller betters the embedded power man-agement module in terms of cost and performance. A compensa-tion enhancement multistage amplifier (CEMA) is proposed as the error amplifier to provide high gain and stabilize the closed-loop system without any external compensation component. To overcome the design difficulties due to the small voltage head-room when using low-voltage core devices, the multistage struc-ture is adopted to derive high gain and achieve good regulation. The CEMA can replace an error amplifier in low-voltage de-sign to obtain a performance similar to that of a cascode error amplifier under a high supply voltage. However, the cascaded structure will induce some unwilling non-dominant poles that would deteriorate the phase margin. Thus, the closed-loop com-pensation has to be contemplated discreetly.

DVS function in the proposed power management module can provide a suitable and competitive solution for the UWB in-tegration. The embedded DVS function would receive the power request from the UWB processer through the two-bit signal,

, which would indicate an adequate voltage value of from 1 V to 1.3 V in order to get superior UWB system perfor-mance.

In the system operation of the proposed power management module, the error signal , which is generated by the CEMA, can reflect the load condition from the output voltage and decide the duty ratio through a comparison with the summing signal, , which is a summation of the current sensing signal

and the slope compensation . Additionally, the signal generated by the sawtooth generator synchronizes PWM modulation in the current-mode DC-DC converter and carries out a duty ratio signal, , with the comparator. The dead-time control can also avoid the occurrence of shoot-through cur-rent when the two power switches, and , turn on simul-taneously.

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Fig. 3. Full structure of the proposed power management module.

Fig. 4. The proposed pre-regulator design in power management module.

III. CIRCUITIMPLEMENTATION

A. Pre-Regulator

In the proposed power management module implemented by the 65 nm technology, the high input voltage cannot directly connect to low-voltage core devices since the reliability issue. Basically, using the high-voltage I/O device to implement the whole controller in the power management module is simple, but it occupies a large silicon area and increases cost. There-fore, an appropriate solution is to convert the high input voltage to a low voltage to drive the LV-PWM controller. To supply a regulated and noiseless power to the LV-PWM controller, a high efficiency pre-regulator is the design object.

1) The SC Converter With Cascaded LDO Circuit: In

gen-eral, the pre-regulator is served by a LDO circuit. The advan-tages are simple structure and small silicon area, but a serious drawback is poor efficiency at low output level [16]–[18]. The SC converter can provide a large step-down conversion ratio without the need of a complicated structure for high conversion efficiency. The cascaded LDO circuit is chosen to suppress the

noise generated from the SC converter in order to ensure a stable and regulated supply voltage to drive the LV-PWM controller. Fig. 4 shows the proposed pre-regulator design. The SC con-verter with the cascaded LDO circuit is controlled by the power conditioning circuit and the phase generator to guarantee a low output voltage .

Fig. 5 illustrates the detailed configuration of the SC verter with cascaded LDO circuit controlled by the power con-ditioning circuit and the phase generator. In Fig. 5(a), the power conditioning circuit can decide the conversion ratio of the SC converter according to the high input voltage, . and are 400 K and 100 K , respectively. The reference signals of and , which are generated from the bandgap ref-erence circuit, are 0.5 V and 0.6 V, respectively. The adaptive conversion ratio aims for high power conversion efficiency. The decoder can generate the gate control signals, , for the SC converter through the factor control signals, and , and the phase clocks. The phase generator generates the phase clocks that contain , , and . Owing to the power con-ditioning circuit, high input voltage can be scaled down

Fig. 5. (a) The structure of the SC converter with cascaded LDO circuit and the power conditioning circuit. (b) The phase generator in the pre-regulator. to a low voltage through the automatically

predeter-mined factors of or . Moreover, to maintain a high pre-regulator efficiency, the auto-bypass function would disable the SC converter and directly connect to

when input voltage is lower than 2.5 V. Under different con-version ratios, the table in Fig. 5(a) lists the operation of SC converter for gain and common phases. This mechanism allows the pre-regulator to enhance conversion efficiency over a wide input voltage range. The conversion efficiency of the pre-regu-lator can be shown in (1), where represents the conversion ratio of the SC converter.

(1) The LDO circuit in the pre-regulator is compensated with a small on-chip capacitor of 0.1 pF. It would also increase the power supply rejection (PSR) from the high input voltage for the LV-PWM controller.

The phase generator is depicted in Fig. 5(b). The phase clock generated by the ring oscillator is designed with the dead-time mechanism produced by simple logic scheme to prevent leakage

in the SC converter. The multiplexer would decide the gate trol signal for the switches in the SC converter by the factor con-trol signals, and . That is, all switches in the SC con-verter are kept at off state to eliminate leakages of charge sharing during the phase-exchanging period. Consequently, conversion efficiency of the pre-regulator can be further enhanced.

2) Handover Technique: The proposed handover technique

is activated after the second output voltage is regulated. Through the handover decision circuit in Fig. 4, would take over the job of the SC converter with cascaded LDO cir-cuit to supply the LV-PWM controller. Accordingly, the pre-regulator can be shutdown to reduce power consumption and achieve an imperative predominance in the highly integrated SoC system.

During the start-up period, is connected to since is still smaller than a rated value. Once is acti-vated and regulated to supply the UWB system, the handover technique will disconnect from and connect to through the handover decision circuit. Moreover, the pre-regu-lator would be fully shutdown for power saving. Fig. 6(a) shows the proposed handover decision circuit. When exceeds the

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Fig. 6. (a) The handover decision circuit in the pre-regulator design. (b) Time diagram of the handover procedure.

Fig. 7. The simulation results of the pre-regulator efficiency by LDO, SC con-verter with cascaded LDO circuit, and the handover technique.

predefined reference voltage of , which is 0.9 V in this design, the handover decision circuit starts to switch the low supply voltage from to in order to activate the self-bi-asing mechanism. On the other hand, the digital delay counter can avoid the abnormal operation due to switching noise while the handover procedure. After a delay decided by the digital delay counter, is directly conducted to to supply

the LV-PWM controller through the transmission gate. Further-more, the pre-regulator will be shutdown subsequent to the dover to reduce power dissipation. The time diagram of the han-dover procedure is illustrated in Fig. 6(b).

For safety operation, the pre-regulator needs to wake up when the UWB system enters the silent mode and disables . When the UWB system enters the silent mode, the UWB pro-cesser will send a message to the power management module to inform the SC converter and the LDO circuit to supply the LV-PWM controller again. That is, the regulated voltage would supply the LV-PWM controller immediately to ensure correct operation of the power management. Fig. 7 shows the simulated efficiency comparison of the different pre-regulator designs. With automatic adjustment of the conversion factor for the SC converter, efficiency can be kept at 50% to 80%. However, the efficiency finally decreases to the same value as that of the pre-regulator implemented by only one LDO cir-cuit. Fortunately, the handover technique can achieve the self-bi-asing mechanism and fully shutdown the SC converter to reduce power dissipation. Thus, efficiency can be obviously enhanced over a wide input supply voltage range.

Fig. 8. The single-stage error amplifier with a PI compensator in low-voltage operation.

Fig. 9. The proposed CEMA structure expressed by the open loop format.

B. Compensation Enhancement Multistage Amplifier (CEMA)

The LV-PWM controller features the advantages of small sil-icon area and low power consumption compared to the conven-tional design utilizing only high-voltage I/O devices. However, there are some design challenges due to the deep-submicron de-vices that need to be overcome. Low supply voltage, typically 1.2 V in the core device of 65 nm technology, restricts the use of a conventional cascode structure. The cascode structure is used in a single-stage error amplifier in the conventional design under high supply voltage to increase the output impedance for high gain [2]. Thus, voltage gain of the error amplifier would be lim-ited in low-voltage operation, which implies a deteriorated reg-ulation performance.

Fig. 8 shows the single-stage error amplifier without the cas-code structure that can be utilized under low supply voltage. The transfer function, , of the single-stage error amplifier is ex-pressed in (2). The proportional-integral (PI) compensator can generate two poles, and , and one zero, . The low-frequency pole acts as the system dominate pole. The

zero is used to cancel the effect of the output filter pole in the current programmable control DC-DC buck converter. In addition, the high-frequency pole can filter out the switching noise of the error signal. However, this single-stage structure cannot derive high gain and needs a large compensa-tion capacitor to maintain system stability. The large is difficult to implement in the chip owing to the tremendous sil-icon cost of the advanced technology.

(2)

Therefore, the structure of the error amplifier should be mod-ified to achieve high voltage gain under low-voltage operation. To increase DC voltage gain of the error amplifier for further en-hancing the loop gain, the proposed CEMA is utilized in Fig. 9. Owing to the cascaded structure [19], [20], voltage gain of the multistage amplifier can be increased in low-voltage operation. The structure is basically composed of three gain stages for high gain and one feed-forward gain stage for the generation of one compensation zero. The is the transfer function of the CEMA and is expressed in (3), shown at the bottom of the page. The open loop gain of the CEMA is increased by the mul-tistage structure compared to the single-stage error amplifier. Moreover, the generated low-frequency pole-zero pair, and , can guarantee system stability. Following Miller’s theorem, the pole, , given by (4) through the use of a

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small on-chip capacitor of 5 pF, is treated as the system dominant pole. The compensation zero, as expressed in (5), is generated by the feed-forward gain stage in the CEMA and the on-chip compensation resistor which can further push toward low frequencies for the sake of an adequate phase margin.

(4) (5) , , and are the compensation components of the CEMA structure in Fig. 9. According to the transfer function in (3), assuming that the flying capacitor, , would not be in-serted to compensate for the system, high-frequency complex poles that come from the parasitic capacitance of gain stages will cause a gain peaking to affect the stability of power man-agement. Furthermore, the additional will also further move the complex poles toward the right-half plane (RHP) when is not implemented by (6), and would induce a higher gain peaking in frequency response than that in without using and

. Thus, system stability will worsen.

(6) As mentioned above, the utilization of is necessary es-pecially for applying the compensation resistor in the pro-posed CEMA. The capacitor of 2 pF is used to separate the high-frequency complex poles to two real poles in the frequency domain [21], [22] as illustrated in Fig. 10. Consequently, gain peaking can be eliminated by the pole-splitting result. From (3), the insertion of guarantees the non-complex poles as ex-pressed in (7). Therefore, the magnitude response with this com-pensated cascade amplifier, CEMA, of the DC-DC converter can approach 0 dB with a slope of only 20 dB/dec without being affected by the non-dominant poles.

(7) A comparison of these three different type error amplifiers in the frequency domain is shown in Fig. 10. The from the single-stage error amplifier has a DC voltage gain smaller than 40 dB, which cannot guarantee a regulated output driving voltage in the power management module. Meanwhile, from the proposed CEMA due to the multistage structure can effectively provide a high voltage gain even in a low supply voltage operation of 1 V. That is, DC voltage gain can be raised higher than 80 dB to achieve good regulation performance, which is required in UWB systems. In addition, the compensa-tion zero enhancement and the non-dominant pole splitting in CEMA are also indicated. The location of the output filter pole of DC-DC converter is also indicated in Fig. 10. The system phase margin varies from 55 to 80 degrees under different load condition.

Fig. 10. The comparison of the three different error amplifiers in frequency response.

Fig. 11 depicts the schematic of the CEMA circuit. The tran-sistors and constitute the first gain stage. The second stage is composed of the transistor with a current mirror to obtain a positive gain. Additionally, constitutes the third gain stage. The feed-forward stage is composed of the tran-sistors and . The equivalent resistance in Fig. 9 is composed of the diode-connected transistor and has an equivalent resistance of . The schematic of the CEMA is supplied by , which is generated from or and has a wide range from 1.0 V to 1.3 V owing to the han-dover technique. Thus, the proposed CEMA structure operates in the low-voltage supply to overcome the small voltage head-room in analog design and achieve the on-chip compensation by utilizing two small capacitors simultaneously. Moreover, com-pared to the single-stage error amplifier in low-voltage opera-tion, fast transient response and good regulation are achieved by the CEMA owing to its enhanced loop gain and optimum system compensation. This feature of the power management is suitable for the SoC applications.

C. Dynamic Voltage Scaling (DVS) and Post-Regulator

The DVS function is implemented with the post-regulator, which is a low-dropout regulator with an impedance attenuation buffer stage as shown in Fig. 12. The dominant pole of the post-regulator is at the output node due to the large output capacitor . The non-dominant poles, which appear at of the error amplifier output node and at of the gate of power transistor , degrades the phase margin [23]. The buffer stage, which contains and , can separate the non-dominant

Fig. 11. Schematic of the proposed CEMA.

Fig. 12. The schematic of the post-regulator with DVS function.

poles by reducing the output impedance at node given by (8):

(8) Owing to the flipped voltage follower structure in the buffer stage, is greatly decreased [24]. The is designed to achieve a correct biasing path for . Thus, the non-dominant pole generated by the parasitic gate capacitance of power tran-sistor and would be pulled to high frequency, which has no deterioration to the phase margin.

Moreover, the open-loop transfer function of the post-reg-ulator is given by (9). The is the transconduc-tance of the error amplifier in the post-regulator, while and are the parasitic capacitances at node and , respec-tively. The is the equivalent resistance at . is the equivalent resistance of , and is the load resistance of the post-regulator. Furthermore, owing to the flipped voltage

follower structure in the buffer stage, the required quiescent cur-rent and the aspect ratio of can be minimized simultane-ously.

where (9)

is dynamically adjusted from 1 V to 1.3 V for the DVS function. The two-bit signal, , generated from the UWB pro-cesser indicates the power request. In the DVS operation, the processer in UWB is the master unit and the post-regulator in power management is the slave unit. The DVS function can scale down the supply voltage to minimize power consumption and return it to the standard value before data transmission. Ad-ditionally, the LV-PWM controller is designed to operate under a 1 V supply voltage since the handover technique would di-rectly connect the supply voltage of LV-PWM controller from

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Fig. 13. Measured result of load transient response with a load step of 200 mA. (a) The load current changes from 200 mA to 400 mA. (b) The load current changes from 400 mA to 200 mA.

IV. MEASUREMENTRESULTS

The proposed power management module with the LV-PWM controller was fabricated by 65 nm CMOS technology. Fig. 13 shows the load transient response from 200 mA to 400 mA and vice versa. The first output voltage is 1.8 V with the voltage ripple about 15 mV. The undershoot voltage is 40 mV (2.2%) and the recovery time is 8 when load current changes from 200 mA to 400 mA. On the other hand, the overshoot voltage is 50 mV (2.7%) and the recovery time is 9 when load current changes from 400 mA to 200 mA.

Owing to the design of CEMA, which provides high system loop gain in the low-voltage operation, the load regulation of is 25 mV/A @ . The internal IR voltage drop across the bond-wire and Quad Flat Non-leaded (QFN) substrate routes may also cause regulation error in test chip. Moreover, the variation of is about 12 mV when has a 0.6 V voltage step as shown in Fig. 14. The line regulation of

is 20 mV/V when load current is 200 mA. The measured output voltage of the SC converter

and the output voltage of the cascaded LDO circuit are shown in Fig. 15. The output ripple of the pre-regulator is sup-pressed to 10 mV by the LDO circuit. As a result, a nearly con-stant voltage of 1.2 V can supply the LV-PWM controller. In addition, the pre-regulator efficiency is always kept higher than 50% owing to the power conditioning circuit. Fig. 16 shows the handover technique. When the second output voltage is enabled from the UWB system and exceeds over the

pre-Fig. 14. Measured result of line transient response whenV has a 0.6 V voltage step.

Fig. 15. Measured result of the pre-regulator: Output voltage of the SC con-verter,SC V , and the SC converter with cascaded LDO circuit,V (typi-cally 1.2 V).

defined voltage value of 0.9 V, the handover technique would be activated. The can be connected to the directly to supply the LV-PWM controller for self-biasing mechanism. Meanwhile, the SC converter and the cascaded LDO circuit in the pre-regulator will be shutdown. A small output variation of 150 mV at may be induced during the handover period. On the other hand, the SC converter and the cascaded LDO circuit in the pre-regulator would be reactivated when is below 0.9 V. This indicates that the UWB system probably enters the power-saving mode and disables the second output voltage of the power management module. Thus, the handover technique can reduce power dissipation of the pre-regulator and ensure the correct operation of the integration with the UWB system.

Fig. 17 shows the measured result of the DVS function. When the UWB system sends the two bit power request message, , to the power management, the second output voltage can be adjusted immediately to supply the UWB system. The range of would vary from 1 V to 1.3 V. Thus, the LV-PWM controller has to ensure correct operation at 1 V supply for matching up the handover technique. This DVS function also demonstrates the high integration between the power manage-ment and the UWB system.

Fig. 18 shows the power conversion efficiency of the pro-posed power management module. The handover technique can

Fig. 16. Measured result of the handover technique.

Fig. 17. Measured result of the DVS function.

enhance efficiency at all light and heavy loads. Fig. 19 shows the chip micrograph of the complete UWB system with the embedded power management module. The chip photo of the power management module is emphasized at the left side, which occupies 0.356 mm . The active area is effectively reduced by 30% owing to the LV-PWM controller compared to the conven-tional design [2] with high-voltage devices (3.3 V I/O devices)

Fig. 18. The measured power conversion efficiency.

only. Besides, a LDO is placed near the RF circuit to suppress the voltage ripple from the DC-DC converter. The detailed de-sign specification is shown in Table I.

V. CONCLUSIONS

The proposed power management module with low-voltage PWM controller and DVS function was fabricated by 65 nm CMOS technology to integrate with the UWB system. The high efficiency pre-regulator with power conditioning circuit can provide a regulated supply voltage to the LV-PWM controller, which is implemented by low-voltage core devices of 65 nm technology. Additionally, the handover technique can achieve the self-biasing mechanism to further enhance the efficiency. Even under low supply input voltage, the proposed CEMA can increase the loop gain and stabilize the system without using large external compensation components. Experimental results demonstrate the good performance of voltage regula-tion and transient response. Owing to the DVS funcregula-tion, the proposed power management can meet the UWB system’s power request. The fabricated power management module

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Fig. 19. Chip micrograph with the UWB system and the enlarged proposed power management module. occupies a 0.356 mm silicon area and has the qualification to

be integrated in SoC applications.

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Yu-Huei Lee (S’09) was born in Taipei, Taiwan. He

received the B.S. and M.S. degrees from the Depart-ment of Electrical and Control Engineering, Nation Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively. He is currently pursuing the Ph.D. degree in the Institute of Electrical Control Engineering of Nation Chiao Tung University.

He is a Faculty Member at the Mixed Signal and Power Management IC Laboratory, Institute of Electrical Control Engineering, National Chiao Tung University. His current research interests include the power management integrated circuit design, light-emitting diode driver IC design, and analog integrated circuits.

from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.

From 1996 to 1998, he was a part-time IC De-signer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power management ICs. He is currently an Associate Professor in the Department of Electrical Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 80 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue (RGB) color sequential backlight designs for optically compensated bend (OCB) panels, and low-voltage circuit designs.

Ying-Hsi Lin received the B.S. degree from National

Chiao-Tung University, Hsinchu, Taiwan, in 1993, and the M.S. degree in electrical engineering from National Taiwan University in 1995.

He joined Computer & Communication Re-search Lab at ITRI, as a reRe-searcher in 1995, and became project leader of CMOS RF and high speed mixed-signal circuits design in 1998. Since joining ITRI CCL, he has been working on CMOS radio frequency integrated circuits and mixed-signal circuits IC design for computer and communication application. In October 1999, He joined Realtek Semiconductor Corp., as a RF manager, where he was responsible for several R&D CMOS RF projects including Bluetooth, WLAN 802.11abg, 802.11n, WLAN CE and UWB, and also involving CMOS RF IC mass production planning. In the circuits design, his activities ranged are RF synthesizer, LNA, Mixer, modulator, PA, filter, PGA, mixed-signal circuits, ESD circuits, RF device modeling, RF system calibration and communication system design. In 2006, he became the Director of the R&D Center, and led the Research & Design Center of Realtek. He holds more than 30 patents in the area of mixed-signal and RF IC design.

Shih-Jung Wang (S’09) was born in Taipei, Taiwan.

He received the B.S. and M.S. degrees from the De-partment of Electrical and Control Engineering, Na-tional Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively.

He is a member of the Mixed Signal and Power Management IC Laboratory at National Chiao Tung University. His research interests include the design of power management circuit, LED driver ICs, and the analog integrated circuit designs.

Kuo-Lin Zheng was born in Taipei, Taiwan, in 1978.

He received the B.S. degree in electrical engineering from Southem Taiwan University, Tainan, Taiwan, in 2004, and the M.S. degree in electrical and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008.

He was with G-Time Electronic Co., Ltd, Hsinchu, Taiwan, from 2004 to 2006. His research interests clude power management system designs, analog in-tegrated circuits for portable devices, and familiars with low dropout linear regulator.

Chun-Yu Hsieh (S’08) was born in Taichung,

Taiwan. He received the B.S. degree in electrical and control engineering from National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2004, and is currently pursuing the Ph.D. degree in the Department of Elec-trical Engineering and Institute of ElecElec-trical Control Engineering, National Chiao Tung University.

His research area contains many projects of LED driver ICs and power management ICs at the Low Power Mixed Signal Laboratory. His interests include power management circuit designs, LED driver ICs, and analog integrated circuit designs.

Yu-Zhou Ke received the M.S. degree in electrical

and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008.

He is a member of the Mixed Signal and Power Management IC Laboratory at National Chiao Tung University. His research interests include the power management circuit and the analog integrated circuit designs.

Yi-Kuang Chen received the B.S. and M.S. degrees

from National Cheng Kung University, Tainan, Taiwan, in 2003 and 2005, respectively.

He joined Realtek Semiconductor Corporation in September 2005 as a circuit designer. He is currently involved in analog and mixed-signal circuits design. His research interests include line drivers and switching regulators for SoC.

Chen-Chih Huang received the B.S. degree from

National Chiao-Tung University, Hsinchu, Taiwan, in 1990, and the M.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan. in 1992.

He joined Mosel Vitelic Inc., Hsinchu, as an en-gineer in 1994. In 1995, & joined Realtek Semicon-ductor Corp., Hsinchu, as an analog circuit design engineer. During 1995–2010, he was responsible for several projects including fast Ethernet/Gigabit Eth-ernet network interface controller/PHYceiver/switch controller, clock generator, USB, ADSL router, gateway controller, and more. He is currently the Senior Manager of the Analog_CN design team of the R&D Center.