2.4-GHz Low-Noise Direct-Conversion Receiver
With Deep N-Well Vertical-NPN BJT
Operating Near Cutoff Frequency
Jin-Siang Syu, Student Member, IEEE, Chinchun Meng, Member, IEEE, and Chia-Ling Wang
Abstract—A 2.4-GHz low-power low-noise direct-conversion re-ceiver is demonstrated using parasitic vertical-NPN bipolar junc-tion transistors (BJTs) in a standard 0.18- m CMOS process. The current switching operation of a Gilbert mixer with finite tran-sistor cutoff frequency( ) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor , the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has con-version gain of 51 dB and noise figure of 3.2 dB with 70-kHz1 noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.
Index Terms—Direct-conversion receiver (DCR), polyphase filter (PPF), symmetric 3-D inductor, vertical-NPN (V-NPN).
I. INTRODUCTION
B
IPOLAR junction transistors (BJTs) have ultra-low noise, better device-to-device matching, and also larger transconductance than MOS devices. Therefore, many RF transceiver chips have been fabricated using BiCMOS processes where the high-performance SiGe HBT is used for the RF circuit and CMOS for the logic circuits [1], [2]. However, the cost is high and access to the foundry process is quite limited. Contin-uous advances in CMOS technology provide both good RF cir-cuits and digital very large scale integration (VLSI) at very low cost. For wireless communication applications, a direct-conver-sion receiver (DCR) has the highest integration level. However, a CMOS DCR has inherently serious problems of noise and dc offset because the MOS device has a very high noise corner and large mismatch. Conventionally, a passive mixer is widely chosen for a DCR due to its low noise property be-cause no dc current flows through the switching core [3]–[10]. However, the conversion loss of the passive mixer core results in an urgent need of higher gain (i.e., higher power consump-tion) at the preceding low-noise amplifier (LNA) tocompen-Manuscript received April 02, 2011; revised August 28, 2011; ac-cepted September 12, 2011. Date of publication October 24, 2011; date of current version December 14, 2011. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC 98-2221-E-009-033-MY3, Contract 99-2221-E-009-049-MY3, and Contract NSC 98-2218-E-009-008-MY3, and by the Ministry of Education (MoE) Aim for the Top University (ATU) Program under Contract 95W803.
The authors are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jssyu.cm95g@nctu. edu.tw; [email protected]; [email protected]).
Digital Object Identifier 10.1109/TMTT.2011.2169421
sate for the mixer loss to achieve a low noise figure (NF) for the receiver. In the previous literature [4], [5], a preceding cell was placed between the LNA and passive mixer to com-pensate for the passive mixer loss, while the noise corner is kept low. Further, if an advanced technology is available [3], [4], e.g., 90- or 65-nm CMOS process, excellent noise perfor-mance can be easier to be achieved at a higher cost. Although a CMOS active mixer has sufficient gain due to the additional RF stage, the several-megahertz noise corner is a crit-ical weakness for a DCR, especially in a narrow IF band appli-cation. A longer gate length is chosen to guarantee sufficiently low noise, which is inversely proportional to the gate area [11]. The flicker noise leaks to the IF port at the local oscillator (LO) zero-crossing intervals from the LO switching device. Thus, the dynamic current injection method [12] allevi-ates the direct mechanism of the noise contribution [11] by drawing out the biasing current of the LO switching de-vices at the zero-crossing. A CMOS current-reuse stage can also be employed as a current bleeding topology with additional transconductor gain [13]. Further, the parallel inductors placed at the push–push nodes of the mixer switching core tune out the parasitic capacitance, and thus reduce the indirect mechanism of the noise contribution to mixer outputs [14].
A vertical-NPN (V-NPN) BJT can be obtained in a deep n-well CMOS process without an extra mask [15], [16] and its low noise performance is especially suitable for a DCR. As a result, V-NPN BJTs are used in this paper to directly eliminate the device noise source. However, the V-NPN BJT has a relatively low cutoff frequency . Thus, the current switching operation of a Gilbert mixer is fully analyzed, especially when the operating frequency is near or even higher than the transistor . Besides, the LO polyphase filter (PPF) loss due to the capacitive load of the following mixer is also addressed. Finally, a pair of the fully symmetric 3-D inductors are used to improve both the mixer conversion gain (CG) and reduce the PPF loss.
The dc and RF performance of the parasitic V-NPN BJT in a standard low-cost 0.18- m CMOS process are described in Section II. Circuit design of a low-power low-noise DCR using V-NPN BJTs is described in Section III, while Section IV reports the measurement results. Finally, conclusions are pre-sented in Section V.
II. V-NPN BJTINDEEPN-WELLCMOS
Today, most of the state-of-the-art CMOS foundries pro-vide deep n-well technology, which can propro-vide excellent
Fig. 1. Cross-section view of the V-NPN BJT in deep n-well 0.18-m COMS process.
Fig. 2. Current cutoff frequency (f ) and maximum oscillation frequency (f ) of the V-NPN BJT with two shapes, but the same emitter area of 4 m .
isolation against the substrate coupling noise among and between digital baseband logic circuits and RF circuits. Be-sides, the V-NPN BJT can be obtained without extra cost from this deep n-well CMOS technology. The V-NPN BJT is composed of the source–drain diffusion as the emitter, the p-well diffusion as the base, and the deep n-well as the collector, as shown in Fig. 1. A deep-n-well V-NPN BJT provides not only lower collector resistance, but also thinner p-base thickness, both of which can lead to good BJT performance. The and maximum oscillation frequency obtained from -parameter measurements are drawn
in Fig. 2. Two devices [(i) m ,
(ii) m with identical emitter
areas of 4 m ] are implemented and measured, where , , and represent the emitter stripe width, emitter length, and number of emitter fingers, respectively. Fig. 2 indicates that the four devices with different layout shapes have sim-ilar because of the same base thickness. On the other
hand, , where ,
, , and are the intrinsic base resistance and collector capacitance per unit area. Thus, can be rewritten as
(1) which indicates the importance of emitter stripe width on [17]. Thus, a V-NPN BJT with a rectangular emitter shape has a higher than a V-NPN BJT with a square emitter, as shown in Fig. 2. Here, (or ) is noted in this paper be-cause it affects the LO power loss, which will be described in Section III-C.
Fig. 3. (a) Block diagram of the DCR including LNA, I/Q mixers, I/Q VGAs, and an LO quadrature generator. (b) Schematic of the single-ended-input LNA with tuning transistorM and a single-to-differential transformer.
III. CIRCUITDESIGN
Fig. 3(a) shows the block diagram of the DCR consisting of a single-in-differential-out LNA, in-phase/quadrature (I/Q) Gilbert mixers with the V-NPN BJT switching core, I/Q vari-able-gain amplifiers (VGAs), and an LO quadrature generator. A. RF LNA and IF VGA
Many low-frequency ( 2 GHz) LNAs have outstanding NF performance because the bond wires with high quality factor ( ) are used for off-chip matching [18], [19]. However, the wire-bonding has significant percentage error and it is difficult to mass produce. On the other hand, a receiver with fully inte-grated inductors can avoid the time-consuming off-chip tuning for every chip. However, the effect of the series resistance in low- inductors should be considered for NF optimization [20]. A parallel , as shown in Fig. 3(b), can be placed to somewhat reduce the inductance of at the cost of voltage gain [19]. A tuning transistor is used to achieve gain reduction and avoid signal compression when a large RF signal is applied. The transistor acts as a current switch that reduces the output signal by shunting the RF current away from the inductive load, as shown in Fig. 3(b). Note that the gain tuning approach using tunable and fixed-biased is a prototype. The cascode device can be broken into more branches with weighted sizes (not only and ), and a more gentle slope of the tuning curve can be achieved by digitally switching on/off the bias of each branch [21]. In addition, a transformer is employed at the load of the cascode LNA to transform the single-ended input current to differential output voltage. The gate dc voltage of the stage in I/Q mixers is fed from the center tap of the sec-ondary coil in the transformer. Instead of a stacked transformer,
Fig. 4. Output noise current spectral density of V-NPN BJT and MOS devices. The dc current is 250A for the devices.
an interleave transformer is selected using both ultra-thick metal (UTM) layers with 2.34- m thickness for low passive loss and a high . Thus, the turn ratio should be . After op-timization for gain and NF, a 5:4 transformer is utilized with linewidth, line spacing, and outer diameter of 9, 2, and 290 m, respectively.
On the other hand, an IF VGA with 20-dB linear-in-decibel tuning range is implemented using an attenuation method [22], [23]. In addition, the V-NPN BJTs are used at the input transconductance stage for excellent noise performance (in-cluding noise) and also a larger transconductance under the same dc current consumption when compared with nMOS transistors.
B. Gilbert Mixer Using V-NPN BJT in Switching Core Fig. 4 shows the device input-referred noise voltage spec-tral density, measured by an Agilent 35670A dynamic signal analyzer, for pMOS devices [(i) m m, (ii)
m m, (iii) m m] and V-NPN BJT with m . The noise corner ranges from 10 to 100 kHz for (i)/(ii)/(iii) devices and a wider gatewidth leads to a lower noise corner. By contrast, the V-NPN BJT has only around 200-Hz noise corner, while the advanced 0.18- m nMOS device has around several-megahertz corner frequency under the same dc current of 250 A. Thus, V-NPN BJTs are used in the LO switching core to guarantee a low noise corner, as shown in Fig. 5(a). Instead of a pure resistive load (without noise contribution), pMOS devices with a 2- m gate length is applied for a more constant dc bias against process variation and still allowable noise performance. On the con-trary, the high-performance, but high noise corner nMOS device can be used in the RF LNA and the RF stage of the mixers because the low-frequency noise at the RF stage will be upconverted to the odd harmonics of the LO signals, not base-band, after the switching operation. Note that if there is dc offset in the mixer core, the noise of the stage will still appear at the output [11]. However, in fact, the BJT core has good de-vice matching and low dc offset [15]; thus, this phenomenon is not serious.
Although the V-NPN BJT in the mixer core has a 200-Hz noise corner, it has a relatively low . Here, we stress
Fig. 5. (a) Schematic of the Gilbert mixer with V-NPN BJT in LO switching core. (b) LO switching function with infinite/finitef in large LO region.
the effect of the transistor on the switching function. The BJT-based Gilbert cell has an exact mathematical expression of current switching function [24]
(2)
where .
The small-signal CG of the current switching function can be computed as the mean dc output current when the input signal is
(3)
The current switching function can be simplified for two ex-treme cases as follows:
(large LO)
(small LO) (4)
That is, the switching function of the mixing core in the large-LO (fully switching) region can be approximated as a square wave, drawn by the dotted line in Fig. 5(b). Therefore, the CG of the switching function in the large-LO region is [25]. On the other hand, when the LO power is small, the CG can be calculated as
(5)
That is, the CG is proportional to the LO voltage swing . The simulated CG of a Gilbert mixer [see Fig. 5(a)] is shown in Fig. 6(a) with different of the BJT switching core, while a two-stage PPF is applied as an LO generator. The of the simulated BJT is changed by modifying the model parameter TF (forward base transit time). Fig. 6(a) clearly shows that the CG increases as the LO power increases when the LO power is small. Gradually, the CG reaches a wide flat-gain response (i.e., in the large-LO region). The wide LO power range with a flat-gain response covers typically more than 5 dB.
In the large-LO region, the switching function replaces , as indicated via a solid line in Fig. 5(b), when a finite
Fig. 6. (a) CG with respect to LO power at different for differentf . (b) CG degradation as a function of relative cutoff frequency(f = f =f ). (c) NF, IIP , and IIP as a function of f .
is considered and can be expressed as
(6)
That is, the whole current charges the capacitance of in the positive LO period while and are
charged in the negative LO period. Thus, after the detailed derivations summarized in Appendix A, the CG of is
(7) where represents the relative cutoff frequency. It is evident that a lower results in a lower CG, as shown in Fig. 6(a).
As a result, the gain degradation of the mixer due to the finite transistor can be represented as
(8) where is defined as the CG when is infinite.
In fact, the low of the switching transistors also results in an LO voltage loss because of the loading effect of the LO PPF [26]. The flat gain region corresponding to the fully switching function becomes smaller for a lower , as shown in Fig. 6(a). Thus, the LO voltage loss is tolerable in the large-LO region.
On the other hand, the CG degrades much more seriously in the small-LO region than in the large-LO region, as shown in Fig. 6(a). Since the CG is proportional to when the Gilbert mixer operates in the small-LO region, the degradation of the LO voltage directly leads to CG degradation. As a result, the GD due to LO loss should be included and the overall GD can be approximated as
(9) can be expressed as follows:
(10) where is the transconductance of the switching device and is the resistance at the stage (last stage) of the PPF. The complete derivation is also summarized in Appendix A.
For a more clear observation of the GD, Fig. 6(b) shows the GD with respect to the relative cutoff frequency at different LO power levels and the data is directly taken from Fig. 6(a). The line with the square symbol represents the calculated GD in the large-LO region (i.e., ) while the GD with small LO input is indicated by triangular symbols (i.e.,
). Two lines successfully represent the upper and lower bounds of the GD at different LO power levels while the solid lines represent the simulated GD at different LO power and are thoroughly located within the two calculated boundaries.
It is noteworthy that this phenomenon is also suitable for an MOS switching core. However, a larger LO power is re-quired to commute the tail current from one side to the other because a MOS differential pair requires a LO voltage swing while only around V is required for a BJT core. As a result, the fully switching region of the LO power range is relatively narrow and even disappears if a low-supply voltage is applied. For a clear comparison between MOS and BJT mixers, two MOS mixers are also simulated and indicated in Fig. 6(a) with the core device sizes ( ) of 80 m 0.18 m and 80 m 0.5 m, respectively, while the RF stage and
IF load stage are the same as those in the BJT mixer. As a re-sult, the LO power requirement for the flat-gain response of both devices are around 2–5 dBm while the LO power requirement of the BJT mixer is below 0 dB even at the low- operation. More importantly, the noise corner is 2 MHz/600 kHz for the MOS mixer with gate length of 0.18/0.5 m, respectively, while the noise corner of the BJT mixer is much lower than 100 kHz.
Besides, the NF and linearity degradation are also simulated as shown in Fig. 6(c). Straightforwardly, the NF increases as the CG degrades. On the other hand, as the decreases, the performance is degraded due to the node capacitance at the switching core [27], while the performance has only a slight change.
C. PPF With Inductive Peaking Technique
Instead of a divide-by-2 divider and/or LO buffers with extra dc power consumption, the pure passive PPF can be directly used because the BJT mixer inherently has low LO power requirement even at a low- operation when com-pared with MOS active/passive mixers. The multistage PPF is widely used in single-sideband upconverters, image-rejection downconverters, and I/Q downconverters [26], [28] since the quadrature phase error of the -stage PPF can be expressed as where is the designed center frequency. In other words, for a given tolerable phase error , the ratio bandwidth becomes
where . That is, more stages of the PPF result in less phase error within the target bandwidth or a wider tolerable bandwidth for a given phase error. In addition, the phase accuracy is independent of loading, but the loadings affect the overall voltage loss, as mentioned in [26]. The PPF has a certain voltage loss due to both the inter-stages and the last loading stage. The loss between every stage at the center frequency was fully discussed in [26] and can be directly calcu-lated using the voltage division , while is the -stage resistance of the PPF. However, in this study, we especially emphasize the loss due to capacitive loading (i.e., the mixers) at the last stage because it is the sole term related to the mixer transistor .
As proposed in [26], the voltage division at the output node can be expressed as
(11)
where .
Conventionally, is typically a capacitive load due to an active/passive mixer. Thus,
(12) A large loading capacitance results in an incredible loss. In this study, parallel inductors are employed to optimize the LO voltage loss, as shown in Fig. 7(a). A simple model of a real in-ductor consists of a series resistor and an inductor with a quality factor defined as . Generally, the
Fig. 7. (a) Schematic of the two-stage PPF with original capacitive load and ad-ditional inductive load. (b) Calculated optimal voltage division (VD) as a func-tion of inductor quality factor (Q) for different capacitive loadings.
is proportional to the geometric length, and thus also pro-portional to . In fact, the parasitic capacitance should be included for each inductor, which can be merged to for simplicity.
After detailed derivations summarized in Appendix B, the maximum and its corresponding are
(13)
where .
Fig. 7(b) shows the as a function of with different . The without peaking inductors is also indicated in the same figure. It reveals that when the loading capacitance is small, an inductive peaking tech-nique has no improvement. Further, when reaches infinity, dB, which is the same as the result in an open-load situation. However, in practice, degrades due to a finite .
For the double-balanced structure of a Gilbert mixer, the peaking inductor parallel between the PPF and mixer core should be symmetric to maintain a fully differential perfor-mance. Besides, the differential inductor can provide size reduction and a better than separate inductors [29]. In this study, a 3-D symmetric inductor realization is employed for further area saving. Fig. 8(a) shows the multilayer structure
Fig. 8. (a) 3-D view and (b) top view of the pseudo-two-turn layout of the fully symmetric stacked inductor. (c) Top view and (d) simulated inductance and quality factor of the proposed pseudo-four-turn (equivalent 11 turns) fully symmetric stacked inductor.
of a pseudo-two-turn symmetric 3-D inductor proposed in [30]. The top view and cross-section view of this 3-D inductor are shown in Fig. 8(b). A pseudo-two-turn layout can pro-vide, at most, six turns of an inductor in a 1P6M 0.18- m CMOS process. However, the inductance is not enough. Using the basic idea of interleaving the inner and outer turns, this structure can be extended to a pseudo-four-turn formation, as illustrated in Fig. 8(c). As a result, a 3-D inductor with 11 turns is achieved with 8- m linewidth, 2- m line spacing, and an outer diameter of only 100 m. The electromagnetic (EM)
Fig. 9. Schematic PPF loadings including 3-D inductor and mixer with para-siticR .
Fig. 10. Simulated CG as a function of LO power with different transistorR .
simulated differential inductance and quality factor are 7.2 nH
and with of 3.6/8.2 GHz, as shown
in Fig. 8(d). Here, we emphasize that the of the inductor degrades by the parasitic capacitance, but this is not included in the used in (13). In fact, after extraction, the 3-D inductor has a differential inductance of 7.2 nH and a series resistance of 23.6 . That is , not 3.7, as indicated in Fig. 8(d). Moreover, additional parasitic capacitance should be added to when calculating (13).
In this study, pF , pF,
and . As a result, the loss due to the pure capacitive load (i.e., without inductive peaking) is around 4.31 dB. Around 3-dB improvement is obtained when using the inductive peaking technique, as shown in Fig. 7(b).
Further, all the above discussions are concerned about the pure capacitive mixer load. However, it is noteworthy that the series of the V-NPN BJT is important for the LO power loss, especially for the parasitic devices, even though the cur-rent switching mechanism is dominated by the transistor . As indicated in Fig. 9, not only decreases the load impedance (at resonance) of the PPF (i.e., increases the PPF loss due to the loadings), but also reduces the voltage delivered to by a factor of . The simulated CG with respect to LO power for different is shown in Fig. 10. Thus, a small re-sults in a lower LO power requirement, but the maximum CG are almost the same with different . As discussed in Section II, is a criterion for the parasitic resistance ; thus the
de-vice of m is chosen for its lowest
Fig. 11. Die photograph of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
Fig. 12. CG and NF with respect to RF frequency of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
IV. MEASUREMENTRESULTS
The die photograph of the 2.4-GHz low-power low-noise DCR is shown in Fig. 11 and the die size is 1.15 1.05 mm . On-wafer measurement facilitates the RF performance. The current consumption of the LNA is 2.5 mA, while the I/Q mixers and VGAs consume 1.4 and 0.6 mA, respectively. Fig. 12 shows the CG and NF as a function of the RF fre-quency. The peak CG is 52 dB at 2.45 GHz with a 1-dB gain-flatness bandwidth ranging from 2.4 to 2.55 GHz. The minimum NF is 3.2 dB at 2.4 GHz and less than 4 dB within 2.3–2.6 GHz. Fig. 13 shows the CG with respect to the LO power at GHz of three designs. The first design (the main design) uses two parallel inductors and the BJT
size is m . Compared to the
first design, the second and third designs have the BJT size of m (with lower ) and the former has parallel inductors, but the latter does not. As a result,
Fig. 13. CG as a function of LO power of a DCR using V-NPN BJT in a stan-dard 0.18-m CMOS process.
Fig. 14. CG with respect to: (a) RF tuning voltage and (b) IF tuning voltage of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
only 3-dBm LO power is used to reach the maximum CG of 51 dB at 2.4 GHz for the main design. As shown in Fig. 13, using a higher transistor results in around 2-dB less LO power requirement while the peak gain is similar, as predicted. On the other hand, the mixer without resonance inductors (the third design) requires around 2.5-dB larger LO power to reach the peak gain than that with inductors (i.e., the second design). As a result, using both a better device selection and an inductive peaking technique, the overall LO power is reduced by around 4.5 dB. Note that when the LO voltage swing increases, the dc voltage of the push–push point in the BJT switching core also increases. Thus, the BJT devices are gradually forced to operate in a saturation region and then the CG degrades. Due to the noise corner requirement, 2- m gate length of the pMOS loads is chosen. Thus, the resulting high pMOS drain–source voltage drop makes the flat-gain region of the mixer core narrower. Fig. 14(a) shows the CG as a function of the LNA RF tuning voltage , while Fig. 14(b) indicates the CG with respect to the VGA IF tuning voltage . An over 20-dB tuning range is achieved by both RF and IF tuning schemes. Fig. 15 shows the NF when GHz at different LNA gain. The NF is around 3.2/6/10 dB when dB, respectively, while the noise corner is around 70 kHz.
TABLE I PERFORMANCECOMPARISONS
Off-chip input matching No LNA With LO buffer
Differential LO; no LO quadrature generator Integrated PLL/VCO/divider Excluding off-chip baseband circuits Including the LO generator
Fig. 15. NF with respect to IF frequency of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
Fig. 16. Power performance, includingIP ,IIP , and IIP of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
Besides, the NF is kept below 4 dB when the IF VGA gain is reduced by over 20 dB while the LNA is on the maximum gain condition.
Fig. 17. (a) I/Q waveforms atRF = 2:4 GHz. (b) I/Q amplitude imbalance and phase error of a DCR using V-NPN BJT in a standard 0.18-m CMOS process.
Fig. 16 shows the power performance, including , , , at different gain conditions. The I/Q output waveforms are showninFig.17(a)with 0.077-dB gaindifferenceand 0.04 phase error when GHz and GHz. Since the RC
values of the PPF are random due to process variation, the am-plitude/phase mismatch of five random-selected chips are mea-sured to verify the balanced I/Q outputs, as shown in Fig. 17(b). Thus, the amplitude imbalance is below 0.15 dB and phase error is below 0.3 covering 2.2–2.7 GHz. The input return loss is greater than 10 dB covering 2.2–2.6 GHz. The circuit perfor-mance is summarized and compared with state-of-the-art DCRs in Table I. The in this study at the high-gain mode ( 50-dB gain) is relatively low; however, at similar gain condition ( 30 dB) by tuning the VGA, the of this study is still compatible to that of other studie. The passive mixer realizations typically have worse noise performance, but the off-chip input matching induc-tors and off-chip baseband circuits results in a very low NF and also a very low noise corner [5], [8]. On the other hand, ac-tive mixer realizations [23], [31], [32] suffer from a serious noise problem (i.e., noise corner is typically higher than 1 MHz). However, both the pMOS mixer core [33] and the current bleeding technique [13] can reduce the noise corner. In [34], a low-noise high-gain receiver was proposed using BiCMOS tech-nology to directly avoid the noise problem at a higher cost. As a result, the proposed receiver has excellent RF performance using low-cost 0.18- m CMOS process.
V. CONCLUSION
Parasitic V-NPN BJTs in a standard CMOS process are used in the LO switching core of the Gilbert mixer because of their ultra-low noise corner. Both the current switching operation and PPF loss due to finite of the following mixers are fully analyzed. Thus, an inductive peaking technique is proposed to enhance the overall performance. Further, a new fully symmetric 3-D layout realization is proposed in this paper for die size reduc-tion. As a result, the demonstrated 2.4-GHz DCR has a CG of 51 dB and an NF of 3.2 dB with noise corner of around 70 kHz, while the current consumption is 4.5 mA at a 1.8-V supply.
APPENDIXA
DERIVATION OFCG WITHFINITECUTOFFFREQUENCY AND
GAINDEGRADATIONDUE TOLO LOSS
The Fourier series coefficient at of the switching function can be calculated by
(A1)
where and .
As proposed in [24], the voltage division due to capac-itive loading can be expressed as
(A2)
where and .
As a result, the maximum is (i.e., 3-dB gain) when reaches infinity. Thus, the gain degradation due to LO loss is defined as
(A3)
APPENDIXB
DERIVATION OFOPTIMALINDUCTANCE FOR ANINDUCTIVE
PEAKINGBETWEENLO PPFANDMIXERCORE
The load impedance of series with parallel can be expressed as
(B1)
where .
As a result, at the output node of the LO PPF is
(B2)
where and .
Taking the absolute value,
(B3)
By setting the first-order differential equation to zero, is obtained as follows:
(B4)
Substituting (B4) back into (B3),
(B5)
If reaches infinity (i.e., without an inductor), becomes
(B6)
which is the same as the case of the pure capacitive loads pro-posed in [26].
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Jin-Siang Syu (S’09) was born in Taoyuan, Taiwan,
in 1984. He received the B.S. degree in communi-cation engineering from National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2006, and is currently working toward the Ph.D. degree in electrical engi-neering at National Chiao Tung University.
His current research interests are in the areas of RF integrated circuits (RFICs).
Mr. Syu is a member of Phi Tau Phi.
Chinchun Meng (M’02) received the B.S. degree in
electrical engineering from National Taiwan Univer-sity, Taipei, Taiwan, in 1985, and the Ph.D. degree in electrical engineering from the University of Cali-fornia at Los Angeles (UCLA), in 1992.
He is currently a Full Professor with the Depart-ment of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. His current research interests are in the areas of RF integrated circuits (RFICs) and microwave and millimeter-wave inte-grated circuits (ICs).
Chia-Ling Wang was born in Tainan, Taiwan, in
1986. She received the B.S. and M.S. degrees in communication engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008 and 2010, respectively. Her M.S. research concerned low-power low-noise receivers and low-costV -band Schottky diodes in a standard CMOS process.
