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System Architecture and AFE Designs of DMT Transceiver
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! ! DMT DMT ! ! ! ! AbstractThis project is for the 2nd of the
three-year project that develops DMT-based xDSL transceiver architecture and explores analog front-end circuit design techniques including two key blocks in analog front-end, namely, tunable filter and magnitude control, will be designed. During the first period, the techniques of DSL transmission are studied. The architecture of the DMT-based xDSL transceiver is designed. The issues of VLSI circuit, namely, architecture and specifications, are investigated. Besides, practical circuit design considerations on low voltage and low power are taken into account. In the second period, the transceiver architecture is validated on a
basis of computer simulation in conjunction with theoretical analysis. Moreover, analog front-end circuits are designed and simulated. The issues of bandwidth-tunable filtering and magnitude control are both investigated. Keywords: Dual-loop, Automatic Gain Control (AGC), Programmable Filter, VDSL, DMT
I. INTRODUCTION
AGC is usually configured as a negative-feedback closed-loop structure with variable gain stage on the signal path and magnitude detection/gain control on the feedback path. The acquisition time of conventional AGC is rather long due to its narrow loop bandwidth. Dual loop architecture can be employed for fast acquisition with small steady state error. The closed-loop magnitude dynamic behavior of a VDSL is much slower than the input signal, which enables the usage of lower frequency digital circuitry and thus lower power consumption. A dual-loop mixed-mode AGC architecture that utilizes analog forward signal path and digital feedback control path is devised.
II. ARCHITECTURE
The AGC as shown in Fig.1 consists of a variable gain amplifier(VGA), a shaping filter, a gain-and-buffer(G/B) and a digital feedback part. The VGA adjusts the gain to maintain the received signals magnitude. The shaping filter refrains from the out-of-band
noise and performs anti-alias filtering for analog-to-digital conversion. The G/B amplifies the signal and provides adequate driving capability of AGC. The feedback path includes a magnitude detector, a subtractor and a dual-loop bandwidth regulator. To extract the received signal amplitude, the output of ADC is rectified, integrated and dumped. Since the integrate-and-dump length is 32, a pre-filter is introduced to reduce the effects of pattern noise and to extract a DC-like control voltage. A dumped value is subtracted from Vref
which is employed to setup the desired level. An error voltage is thus generated for the dual-loop filters. A 1-bit quantizer functions as a switch and sets the threshold voltage to determine the loop filter paths. When the quantizer is in the ON state (Q=1), the wideband integrator dominates the regulator response. This results in faster convergence though it induces more in-band noise. Gradually, the output signal level approaches the reference voltage Vref and the quantizer
turns off (Q=0). The regulator bandwidth is immediately shrunk by the first loop filter. This narrow loop bandwidth provides a better noise rejection. The AGC possesses a wide loop bandwidth for fast tracking in the initial acquisition and a narrow loop bandwidth for good jitter performance during steady state, which mainly employs a digital loop regulator arranged in feedback magnitude control.
Figure 1. Block diagram of the dual-loop mixed-mode AGC
III. CIRCUIT DESIGN A. VGA
Exponential VGA is required for a stable AGC loop bandwidth. CMOS transistor does not possess an exponential characteristic as a BJT does. Hence, pseudo
exponential approximation transfer curve can be used. Fig.2 shows the circuit with the property of pseudo exponential.
Figure 2. The pseudo-exponential VGA circuit
In the circuit schematic, the CMOS VGA consists of three parts, namely a gain cell, gain control and common mode feedback. The gain cell is composed of an input source-coupled pair (SCP) M1-M2 and
a pair of diode connected loads M3-M4 whose
bias currents are controlled by the current mirrors, M5-M14 and M6-M13, respectively.
Different control voltages applying to the SCP M11-M12 change the transconductances
of M1, M2, M3 and M4.
Figure 3. Filter and tuning circuit block B. LPF
Fig.3 shows the complete block diagram of the filter and the tuning circuit. This filter incorporates the automatic gain-controlled amplifier (AGC) to accomplish the analog frond end in the receiver chain. In order to conform the DMT VDSL system, the filter is configured as a 4-th order Chebyshev low-pass filter with 0.5dB ripple in the passband. The passband corner frequency is programmable to be 1.104x2n MHz, where n is controlled by the Vsel signal. The filter is
followed by an output buffer stage to drive the succeeding circuits in AGC. The switching circuits select the input signal of
the filter from the variable gain amplifier (VGA) in the previous stage and its output signal to ADC for digitization during general operational mode.
Figure 4. 4th order gyrator-c low-pass-filter For high frequency operation and insensibility to process variation, a Gm-C circuit based on LC ladder prototype, as shown in Fig.4, is used to synthesize the filter. Each transconductor in this filter is designed to be programmed by the Vsel signal as
indicated in the figure. The transconductance of Gmi ranges from gmui to 16gmui, where gmui
is the unit transconductance value. Fig.5 shows the transconductor schematic for the Gm-C filter. The input stage contains M1 and
M2 that convert the voltage signal into
current signal. The Vsel signal controls the
transmission gate which turns on/off the bias current provided by Mb1 to Mb8 to select one
of the five Gm values in each transconductor
stage. A dummy input pair by M3 and M4 is
added to compensate the parasitic capacitance at the input. Vctrl is generated
from the tuning circuits and used to fine tune the Gm value through the degeneration transistor Md1 such that the filter bandwidth
can be set to the predefined value. To increase the output impedance without sacrificing power dissipation, the negative resistance load (NRL) by M5-M8 is used.
Figure 5. Gm cell using NRL (Negative Resistance Load)
A complementary common mode feedback (CMFB) is configured for
low-voltage operation. An n-type source-coupled pair (n-SCP) by Mcn1 and
Mcn2 and a p-type SCP (p-SCP) by Mcp1 and
Mcp2 are utilized as the input stage similar to
conventional rail-to-rail amplifiers. The CMFB voltage is extracted by the n-SCP with a common gate amplifier and the p-SCP with a source follower and fed back to the tail currents for the core cell. The two pairs, n-SCP and p-SCP, compensate the nonlinearities of each other and increase the output swing of the Gm cell.
C. Gain/Buffer
The G/B stage is employed to amplify the signal and drive the output pads. Fig.6 depicts the circuit schematic of the G/B. It is composed of three parts, a transconductance stage, a current gain stage and a transimpedance stage. Input stage M1
transforms the input voltage into current. Then, the current gain stages M2-M4 and
M3-M5 utilize current mirror structure twice
to offer current gains. Finally, transistors M7,
M8 and resistor Rf construct a shunt- shunt
feedback transimpedance stage. Essentially there are no high impedance nodes internally.
Figure 6. The wideband gain-and-buffer circuit
D. Digital Feedback Path
Figure 7. The circuit of the digital feedback control path
As shown in Fig.7, the magnitude detector and the bandwidth regulator constitute the digital feedback path. To reduce power consumption, a lower system clock that is generated by dividing the sampling clock of a factor 32. The magnitude
detector is composed of a MUX, a register and an adder. The reference voltage Vref is
firstly loaded into the register in each integrate-and-dump cycle while the 5-bit counter is 0. The stored value is then subtracted from the rectified ADC output and updated by the residual value iteratively until the integrate-and-dump cycle is finished.
In the acquisition process, the output of the bandwidth regulator is the summation of the first loop filter and the second loop filter. Meanwhile, the register keeps updated. When the pre-filter exceeds the threshold voltage, both of the MUXs are switched to the lower signal path by the output of the comparator. The latest value hold in the register is summed with the always-on 1st loop filter output. A steady state control voltage is then sent to VGA. The coefficients of the dividers and multipliers are power of two, i.e. 2n or 1-2-n, which are just modified to perform shift-and- add technique.
Figure 8. Chip Layouts of AGC and Programmable Filter
IV. IMPLEMENTATION AND SIMULATION RESULTS
Table 1. Programmable filter performance summary
The AGC and programmable filter are fabricated with 0.35£g m -well 1P4M CMOS technology. Chip layouts are shown in Fig.8. The programmable filter and AGC performance summaries are shown in Table.1 and Table.2, respectively. Fig.9 shows the
AGC closed-loop simulation result.
Table 2. AGC performance summary
Figure 9. AGC closed-loop simulation V. CONCLUSION
The dual-loop mixed-mode AGC for VDSL up/down stream AFE is presented in this report. With the aid of the digital bandwidth regulator, it provides two distinct loop-bandwidth responses, namely, 12KHz and 5.6KHz, to achieve a fast convergence during acquisition and stable and precise magnitude control at the steady state. The settling time is less than 0.5ms for 26dB dynamic input while the output maintains 1Vpp constant level.
VI. REFERENCES
Hao-Shun Chang, Ching-Chi Chang, Muh-Tain Shiue, Chorng-Kuang Wang. A 2V Dual-Loop Mixed-Mode Automatic Gain Control for VDSL System. IEEJ International Analog VLSI Workshop,
Singapore, Sept., 2002.
Chia-Hua Chou, Chien-Chih Lin, Chorng-Kuang Wang. A Programmable Filter with Self-Tuning for DMT-VDSL Receiver. AP-ASIC 2002, Taiwan, R.O.C., Aug., 2002.
