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A low-power ASIC design for cell search in the W-CDMA system

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power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from

3 4 3 4 mm2 to2 8 2 8 mm2. The design is implemented

and verified in a 3.3-V 0.35- m CMOS technology with clock rate 15.36 MHz.

Index Terms—Cell search, clock error, frequency error,

low-power design, W-CDMA.

I. INTRODUCTION

I

N A CODE-DIVISION multiple-access (CDMA) cellular system, the procedure employed by a mobile station to search for the best cell site and to achieve code, time, and fre-quency synchronization with it is referred to as cell search. Fast cell search is particularly important for the wideband CDMA (W-CDMA) system because of the use of nonsynchronous base stations in the system [1], [2].

A three-stage search procedure has been designed in the W-CDMA specifications in order to facilitate fast cell search, including slot synchronization, joint frame synchronization and code-group identification, and scrambling-code detection [2]. Slot synchronization (stage 1) is achieved by detecting the primary synchronization channel (PSCH). Joint frame synchronization and code-group identification (stage 2) is achieved by detecting the secondary synchronization channel (SSCH). And, after the code group is identified, the scrambling code can be determined easily by using the common pilot channel (CPICH) (stage 3).

A great deal of research has been contributed to the design of the cell search algorithms [1], [3]–[5]. In [1], a pipelined process was proposed to achieve faster cell search than the serial one at the cost of higher complexity. Partial symbol de-spreading with noncoherent combining was proposed in [1], [3] to over-come large frequency error due to the oscillator inaccuracy of

Manuscript received March 6, 2003; revised December 15, 2003. This work was supported by the Chip Implementation Center, National Science Council, under Grant NSC92-2218-E-194-008.

C.-F. Li, Y.-S. Chu, F.-C. Tian, and J.-S. Ho are with the Department of Elec-trical Engineering, National Chung-Cheng University, Chia-Yi 621, Taiwan, R.O.C. (e-mail: richard@vlsi.ee.ccu.edu.tw).

W.-H. Sheen is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: whsheen@cm.nctu.edu.tw).

Digital Object Identifier 10.1109/JSSC.2004.826337

time” candidates was proposed to reduce the search time in the clock-drifting environment.

In this paper, a low-power ASIC is designed for cell search in the W-CDMA system under the effect of large frequency and clock errors. A set of low-power design practices starting from the algorithm to hardware architecture and circuits is per-formed so as to reduce chip’s power consumption. By using the power-efficient algorithm, architecture, and circuit designs, the power consumption of the design is reduced by 51%. The de-sign is implemented and verified in a 3.3-V 0.35- m CMOS technology with clock rate 15.36 MHz.

The rest of this paper is organized as follows. Section II presents a low-complexity cell search algorithm under large frequency and clock errors. Section III describes low-power architecture and circuits, power analysis, and redesign of critical blocks. Section IV summarizes implementation and testing results. Finally, the paper is concluded in Section V.

II. LOW-COMPLEXITYCELLSEARCHALGORITHM

Three stages of cell search can be performed either in the se-rial or pipelined fashion [1]. In the pipelined search, all three stages are performed concurrently and that results in a faster search. In this paper, a low-complexity pipelined search algo-rithm will be adopted for the low-power ASIC design.

Different methods have been proposed to counteract the effects of frequency and clock errors on the cell search perfor-mance. Generally, two methods can be used to mitigate the effect of large frequency error. One is frequency offset compensation (FOC) and the other is partial symbol spreading (PSD). FOC has superior performance but needs multiple stage-1 detectors [1], [4]. To counteract the clock error, the simplest method is the random sampling per frame (RSPF) proposed in [4], which was shown to be able to work satisfactorily under 4 ppm of clock error. For large clock error, the method of multiple timing candidates (MTC) could be employed, but multiple stage-2 and stage-3 detectors are needed [5]. Here, a simple method called sample-point reordering (SPR) is proposed to counteract the clock error for up to 10 ppm. The basic idea is as follows. First, the range of clock error is divided into “bins” with each bin denoting a presumed clock error. Then, within a bin, a controller is used to drop or stuff one sample point from or into incoming sampled sequence whenever the

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 853

Fig. 1. Sample-point reordering.

TABLE I

COMPLEXITY OFDIFFERENTSEARCHINGALGORITHMS INTERMS OFMOPS

clock error is accumulated to one sample interval, as shown in Fig. 1.

Table I compares the complexity of different cell search al-gorithms in terms of million operations per second (MOPS) [6]. Among them, does not need any multi-plier as used in the FOC function and has low complexity under the case of , , , where is the number of stage 1 when using FOC and SPR, and and are the number of candidates associated with MTC for stages 2 and 3, respectively. Fig. 2 shows the search time performance. The algorithm is able to reach 0.9 probability of search success in 600 ms. It is good enough for practical ap-plications and is adopted as the low-complexity algorithm for this low-power ASIC design.

III. LOW-POWERHARDWAREDESIGN

Fig. 3 illustrates the block diagram of cell search ASIC along with internal bitwidths [9]. The ASIC consists of four parts, including preprocessing, stage-1, stage-2, and stage-3 detec-tors. The preprocessing module includes RSPF and SPR. The sample-point reorder consists of a pair of tapped-delay lines along with multiplexers and a reordering controller. The ini-tial selection of multiplexers is at the “0” position. Whenever the reordering controller accumulates sampling error up to one sampling interval, the selection of multiplexers is adjusted to-ward “ ” to drop or stuff one sampling point from or into incoming sampled sequence. Then, the RSPF selects one of the sampling points within one-chip duration as input data to the three stages and changes its selection randomly for every new frame.

Fig. 2. Search performance of different algorithms. (In a frequency nonselective Rayleigh channel with frequency o set = 24 kHz, Doppler frequency = 185:2 Hz, B = 3, L = 10, and L = 10).

In stage 1, the primary synchronization code (PSC) detector is designed as a hybrid de-spreader combining efficient Golay correlator (EGC) and hierarchical matched filter (MF) [7], [8]. As shown in Fig. 4, only 18 additions are needed to match PSC in four segments of 64-chip partial symbols. Similarly, a hy-brid secondary synchronization code (SSC) detector is also de-signed by combining EGC and active correlator in stage 2 [9]. In stage 3, eight complex-valued active de-spreaders are employed to de-spread all scramble codes in the identified group.

After the first-phase design, a complete power analysis is per-formed through its post-layout simulations in a 3.3-V 0.35- m CMOS technology by the EPIC’s Powermill tool. The driving

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Fig. 3. ASIC block diagram.

Fig. 4. Hybrid EGC-HMF detector for PSC. Di: Delay for i clocks. It is implemented by using a shift register with i fields.

vector is generated from the system simulation model in [4] and its length is over 600 ms. Table II tabulates the details of power consumption and layout areas of all blocks.

As shown in the table, de-spreaders and (non)coherent com-biners are the power-critical bocks in cell search processing. In

de-spreaders, many shift registers are used in EGCs and MFs of PSC and SSC detectors. These shift registers are used as delay elements only, but all fields of shift registers change their values per clock cycle. This value (level) changing in CMOS circuits results in unwanted power dissipation. To overcome this

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defi-IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 855

Fig. 5. New approximation of magnitude calculations.

Fig. 6. Simulation results using the new magnitude approximation. (In a frequency nonselective Rayleigh channel withfrequency o set = 0 kHz, Doppler frequency = 200 Hz).

ciency, a pointer-based FIFO buffer is used to replace shift reg-isters [10].

In (non)coherent combiners, main operations are multiplica-tions or squares used to calculate the true magnitude of signals. In cell search, however, magnitude values of signals are just used to compare with each other for finding the largest one. There-fore, a new low-complexity approximation is proposed to reduce the power consumption. That is, is approximated by

(1) where and are of the form and therefore, only shift opera-tions are needed. Fig. 5 shows the curve plane of

TABLE II

POWERCONSUMPTIONS ANDCOREAREAS OFCELLSEARCHCOMPONENTS

which is apparently much closer to that of than other approximations, such as and

. Fig. 6 is the simulation result by using this ap-proximation. It is clear that the approximation induces almost no loss on search performance.

After applying the pointer-based FIFO buffer and the new magnitude calculator into the cell search ASIC, the power re-duction is 51% from the original design of 133.6 mW to 65.49 mW. In addition, the chip area is also reduced 31.9% from

mm to mm . Fig. 7 shows power reduction of re-designed blocks.

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Fig. 7. Power consumption of different blocks.

Fig. 8. Chip photograph.

IV. IMPLEMENTATIONRESULTS

The low-power cell search ASIC is implemented into a real chip through a top-down cell-based ASIC design approach

TABLE III CHIPPROFILE

in a 3.3-V 0.35- m CMOS technology. Fig. 8 is the chip photograph. Three ROMs are used to store the comma-free Reed–Solomon (CFRS) codebook (64 60), 16 SSC outer codes (16 16), and 359 initial phases of scrambling codes (359 18). A 5.12-kB SRAM is used to accumulate correla-tion results of 15 slots for 2,560 slot-boundary hypotheses in stage 1. The chip profile is summarized in Table III. The chip consumes 65.83 mW at 15.36 MHz. It is a little more than the simulation result.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 857

V. CONCLUSION

A low-power cell search ASIC for the W-CDMA system has been designed and implemented. First, a low-complexity search algorithm, which combines sample-point reordering, random sampling per frame, and partial symbol de-spreading is devised to counteract the effects of large frequency and sampling errors. The algorithm is then implemented to its layout with careful consideration for power consumption. Furthermore, the power consumption of whole chip is analyzed, and critical blocks such as those of de-spreading and magnitude calculations are redesigned using pointer-based FIFO buffers and new weighted magnitude calculators. The power and area reductions of the chip are 51% and 31.9%, respectively. The low-power cell search ASIC consumes 65.49 mW at 15.36 MHz.

REFERENCES

[1] Y.-P. E. Wang and T. Ottosson, “Cell search in W-CDMA,” IEEE J. Select. Areas Commun., vol. 18, pp. 1470–1482, Aug. 2002.

[2] “Spreading and Modulation (FDD),” 3rd Generation Partnership Project, 3GPP Tech. Spec. TS 25.213, V3.7.0, Dec. 2001.

[3] K.-M. Lee and J.-Y. Chun, “An initial cell search scheme robust to frequency error in W-CDMA system,” in Proc. IEEE Int. Symp. Personal, Indoor and Mobile Radio Communications, vol. 2, Sept. 2000, pp. 1400–1404.

[4] W.-H. Sheen and J.-S. Ho, “Cell search for 3GPP W-CDMA/FDD with chip clock shift and non-ideal sampling,” in Proc. IEEE Vehicular Tech-nology Conf., vol. 4, Oct. 2001, pp. 2369–2374.

[5] M. Kiessling and S. A. Mujtaba, “Performance enhancements to the UMTS (W-CDMA) initial cell search algorithm,” in Proc. IEEE Int. Conf. Communication, vol. 1, 2002, pp. 590–594.

[6] C.-F. Li, W.-H. Sheen, and Y.-S. Chu, “An integrated multi-scheme cell search platform for W-CDMA applications,” in Proc. IEEE Int. Symp. Personal, Indoor and Mobile Radio Communications, vol. 1, Sept. 2003, pp. 1400–1404.

[7] B. M. Popovic, “Efficient Golay correlator,” IEE Electron. Lett., vol. 33, no. 17, pp. 1427–1428, Aug. 1999.

[8] “A new hierarchical correlation sequence with good properties in pres-ence of a frequency error,” Siemens, 3GPP TSG RAN W1 Tdoc 99/146. [9] C.-F. Li, W.-H. Sheen, and Y.-S. Chu, “ASIC design for cell search in 3GPP W-CDMA/FDD,” in Proc. IEEE Vehicular Technology Conf., vol. 3, Oct. 2001, pp. 1383–1387.

[10] E. K. Tsern and T. H. Meng, “A low power video-rate pyramid VQ de-coder,” IEEE J. Solid-State Circuits, vol. 31, pp. 1789–1794, Nov. 1996.

數據

Fig. 1. Sample-point reordering.
Fig. 4. Hybrid EGC-HMF detector for PSC. D i: Delay for i clocks. It is implemented by using a shift register with i fields.
Fig. 6. Simulation results using the new magnitude approximation. (In a frequency nonselective Rayleigh channel with frequency oset = 0 kHz, Doppler frequency = 200 Hz).
Fig. 7. Power consumption of different blocks.

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