the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In ad-dition, a dynamic push–pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5%, and 70%, respectively, when load current changes between 1 and 100 mA.
Index Terms—Analog ICs, CMOS analog ICs, dc–dc power con-version, MOSFET ICs .
I. INTRODUCTION
L
OW-DROPOUT (LDO) regulators are widely used in portable electronic devices as they occupy only small chip area and can convert battery voltages to low-noise, accurate voltages for noise-sensitive system-on-chip (SoC) applications. However, large parasitic capacitance at the gate of a power transistor degrades the slew rate of an error amplifier in case of load variations. Thus, several techniques are proposed for improving transient response time and transient voltage vari-ations in order to maintain a reliable supply voltage for SoC applications. Especially, in the designs of an RF circuit, a stable and regulated supply voltage is the most important requirement for ensuring optimum performance. As we know, the transient response is limited by the bandwidth of the LDO regulators and the internal slew rate associated with the parasitic capacitance of the power MOSFET. Several fast transient techniques are proposed to extend the bandwidth of the LDO regulators and improve the slew rate at the gate of the power MOSFET [1]–[7].Manuscript received June 19, 2008; revised October 06, 2008. First published January 23, 2009; current version published nulldate. This work was supported by the National Science Council, Taiwan, under Grant NSC 95-2221-E-009-351. Recommended for publication by Associate Editor Y. C. Liang.
C.-H. Lin is with the Department of Electrical and Control Engineering, Na-tional Chiao Tung University, Hsinchu 300, Taiwan.
K.-H. Chen is with the Department of Electrical and Control Engineering, Na-tional Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu. edu.tw).
H.-W. Huang is with RichTek Technology Corporation, Hsinchu 30288, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.2007957
Fig. 1. LDO with ARC technique.
The first fast transient technique named as nonlinear control [1]–[3] speeds up the time of charging/discharging the large par-asitic capacitor ( ) at the gate of a power transistor, as shown in Fig. 1. This technique has the ability to provide large quiescent current for driving a large parasitic capacitor at the output of an error amplifier in case of load variations. However, it may suffer from oscillation problems. Thus, a tradeoff between system sta-bility and speed exists in this fast transient technique. Gener-ally speaking, temperature, process, and voltage variations are needed to be taken into consideration when the LDO regulator uses this fast transient technique.
Prediction control is an important fast transient technique to reduce transient voltage ripple. The most famous prediction technique is the adaptive voltage position (AVP) technique [3], [4], which continuously maintains constant output impedance of the converter. This technique improves dynamic performance like transient response time and transient voltage at the sacrifice of static performance like load regulation. Recently, one pop-ular technique, the end-point prediction (EPP) technique, was proposed to improve the reference tracking speed [6 ]. However, the EPP technique, which is suitable only for reference tracking, still suffers from large overshoot/undershoot output voltage and slow response time in case of large load variations. The EPP technique cannot predict the variation of load current, thereby resulting in slow response.
According to the analysis of literatures, the fast transient technique must contain three important characteristics for pro-viding a reliable supplying voltage. These are system stability at full loads, small overshoot/undershoot output voltage, and good line/load regulation. In order to satisfy the aforementioned
Fig. 2. Concept of ARC. (a) Load current changes from light to heavy. (b) Load current changes from heavy to light.
demands, the adaptive reference control and dynamic push–pull techniques are proposed to provide these three fast-transient characteristics at the same time for getting a regulated power supply.
Section II describes the analysis of the ARC technique for LDO regulators. Section III introduces the architecture of the ARC technique. Experimental results are illustrated in Section IV. Finally, conclusions are presented in Section V.
II. CONCEPT OFARC OPERATION FOR ANLDO REGULATOR
The block diagram of the proposed LDO with ARC technique is shown in Fig. 1 . This LDO is composed of a transconductance amplifier, an ARC circuit, a power transistor, an output capacitor with equivalent series resistance (ESR) , and resistors and .
In this design, ESR frequency compensation is used to intro-duce a pole-zero cancellation to ensure closed-loop stability. It is a simple and popular method to compensate the phase margin of the system. However, ESR degenerates the overshoot/under-shoot voltage and limits the performance of the regulator in case of load variations. In order to overcome this issue, an ARC tech-nique is proposed.
The concept of the proposed ARC technique is shown in Fig. 2(a) and (b). Reference voltage ( ), which is close to voltage , can be adaptively and smoothly adjusted according to the error voltage ( ) between voltage and scaled output voltage . During load transient period, the reference voltage is increased when load current changes from low to high. The quantity of is increased when is smaller than . Therefore, the discharging current of the gate ca-pacitor of the power transistor and the falling rate of the gate voltage are increased to reach the appropriate voltage level. Oppositely, the reference voltage is decreased when load current changes from high to low. The value of and the charging current are also increased so as to fast charge the gate capacitor. Hence, the output voltage during the transient period can rapidly return back to the regulated voltage. It means that this scheme responds to undershoot (or overshoot) of the output
Fig. 3. Schematic of LDO with ARC circuit.
voltage instantly and creates an adaptive adjustment of the ref-erence voltage to achieve fast transient response.
With the ARC technique, waveforms of and are shown in Fig. 2 (a) and (b) when load current changes from light to heavy load, or vice versa. The main concept is that reference voltage changes only during load transient period ( and ). At steady state, is close to and the value of output voltage is not affected. That is the reason why the performance of the ARC technique is better than that of the AVP technique. Besides, load regulation can be enhanced if is directly pro-portional to the load condition [7], i.e., voltage variation can be reduced. Hence, the value of voltage in region is larger than that in region. Similarly, the value of voltage in region is less than that in region when load cur-rent changes from heavy to light. Based on the aforementioned description, the ARC technique can use the error voltage and load condition to control signal for dynamically deter-mining the reference voltage. The implementation of the ARC circuit is described in the following section.
III. DESIGN OF THEPROPOSEDCIRCUITS
The schematic of an LDO with adaptive reference control circuit is shown in Fig. 3 . is the power transistor and is the sensing transistor for sensing load condition, i.e., is a load sensing current. is generated by a reference controller and its value is proportional to the error voltage . In order to achieve the ARC technique, an additional resistor is serial to a fixed voltage . By using two revised currents and to flow through the resistor , the reference voltage can be dynamically adjusted for the LDO regulator according to the output voltage variation and load condition.
A. Transconductance Amplifier
Transconductance amplifier is composed of transistors – and – . Two cascaded flipped voltage fol-lowers (CASFVF) [8]–[10] composed of ( , , and ) and ( , , and ) have small output impedances to improve the linearity of level shifters. Therefore, the voltage difference between and is equal to the voltage dif-ference between nodes and . Using three current mirror
Fig. 4. Schematic of reference controller and dynamic push–pull circuit (M > 1).
pairs, which are ( ), ( ), and ( ), the transconductance can be determined as
(1) where K is the ratio of current mirror. Here, the transconduc-tance amplifier has a broad bandwidth about megahertz, thus contributing to enhance the transient response time. However, the dc gain is slightly lower and not enough to support an excel-lent performance for load regulation. Hence, the load regulation compensator is used to retrieve it.
B. Reference Controller and Dynamic Push–Pull Circuit The reference controller, as shown in Fig. 4, uses the transis-tors and to mirror the small-signal current from and , respectively. Based on current mirror pairs ( ) and ( ), the revised current can be generated and de-rived as
(2)
According to (2), the revised current that is proportional to the output error voltage can be used to adjust the reference voltage in case of large load variations.
The dynamic push–pull circuit is composed of transistors , and – . Based on the appropriate design for the ratio of current mirror (M > 1), voltages of node and are set to “1” and “0” to force transistors and to be turned off at steady state. Assuming that and are the sum of small-signal current of and , respectively, they can be determined as
(3)
immediately owing to the slew rate of the transconductance am-plifier. Hence, the output capacitor supplies the insufficient charge between load current and input supplying source. There is an undershoot voltage at the output node. Thus, the reference controller converts the error voltage to a revised current , and increases the value of reference voltage . Conse-quently, the slew rate of the transconductance amplifier can be enhanced during the transient period. Moreover, the dynamic push–pull circuit pulls up the voltage of node to discharge the node through transistor . The gate–source voltage of power transistor is rapidly increased, and thus, more energy is delivered to the load. When the output voltage is regulated back to its expected voltage, i.e., is small, the revised cur-rent becomes trickle curcur-rent and is not large enough to affect the reference voltage. Besides, the voltage of node is smoothly reset to “0” to turn transistor off. Finally, the voltage becomes constant again at steady state.
C. Load Regulation Compensator
According to [7], the output voltage of LDO regulator can be derived as
where (4) where is the load regulation, is the open-loop gain of the error amplifier,β is the feedback factor, and is the output resistance of the power transistor. In order to reduce the voltage variation due to load variations, the ARC circuit uses a load sensing current to solve this issue, and we can obtain the following condition:
(5) Hence, the sizes of and the value of N are carefully de-signed to get a minimum voltage variation .
Based on the reference controller and load regulation com-pensator, the adaptive reference voltage can be derived as
Fig. 5. Simulation results of loop gain and phase of the proposed LDO regulator. (a) Load current is 1 mA. (b) Load current is 100 mA.
in the following equation to satisfy the demands of different load conditions during transient and steady periods:
(6) Substituting the results of (5) and (6) in (4), the output voltage of LDO regulator is derived as
(7) Referring to (7), the output voltage variation of LDO regu-lator in case of load variation is reduced by minimizing the dif-ference between and . Owing to the varia-tion of temperature and process, there is a little error between the value of and . However, the insertion of still has the ability to improve load regulation com-pared to the original design.
D. Stability Analysis
In order to demonstrate the stability in steady state, the anal-ysis of positive/negative feedback loop should be considered carefully for designing the circuit. The dynamic push–pull cir-cuit will be shut down when the output voltage is close to , i.e., and areOFF; hence, we only need to analyze the ARC technique.
The feedback signal produced by LDO returns to both inputs of the transconductance amplifier. To improve the stability of
TABLE I
PARAMETER ANDCOMPONENTVALUES
the ARC technique, the quantity of both inputs is discussed. At the noninverting input terminal of transconductance amplifier, the negative feedback factor is given by
(8) At the inverting input terminal of transconductance amplifier, the positive feedback factor is given by
(9) Thus, the condition is essential for stability, i.e., the quantity of negative feedback is larger than that of positive feed-back, and it assures that the proposed LDO is operating under stable condition. In our design, the parameters and components are shown in Table I.
Fig. 5 shows the gain and frequency response of the proposed LDO with ARC technique under load currents of 1 and 100 mA. The gain of the LDO regulator is about 60 dB and the phase margin is larger than 60 , i.e., the structure of the ARC does not deteriorate the stability of the original design. The stability of the proposed LDO is guaranteed in our design.
Fig. 6. Chip micrograph.
TABLE II
SUMMARY OF THELDO PERFORMANCE
IV. EXPERIMENTALRESULTS
The proposed LDO regulator with ARC technique was im-plemented in Taiwan Semiconductor Manufacturing Company (TSMC) 0.35- m CMOS technology. The threshold voltages of nMOSFET and pMOSFET are 0.55 and 0.65 V, respectively. The chip micrograph is shown in Fig. 6 and chip area is 400 m 470 m. A summary of the LDO performance is shown in Table II. Fig. 7 shows the experimental setup of the proposed LDO with ARC and dynamic push–pull techniques. Two output filter capacitors 4.7 and 10 F, which have ESRs of 0.3 and 0.5 , respectively, are used to demonstrate the performance of the
Fig. 8. Transient response of an LDO regulator with load current step from 1 to 100 mA, or vice versa. (a) Without ARC technique. (b) With ARC technique (V = 2 V, C = 4.7 F, R = 0.3 ).
LDO regulator with ARC technique. The value of load resistor is used to decide the load current.
The dropout voltage is about 60 mV at = 100 mA. The load current with rising time and falling time of 0.1 s changes from 1 to 100 mA, or vice versa. Fig. 8(a) and (b) shows the waveforms of LDO regulator without and with ARC technique, respectively. Obviously, the undershoot voltage and settling time are improved about 31% and 68.5%, respectively. Load regulation is improved about 70%. The enlarged waveforms
Fig. 9. Enlarged waveforms of an LDO regulator with ARC technique when load current changes from 1 to 100 mA, or vice versa.
shown in Fig. 9 demonstrate that the ARC technique can smoothly adjust reference voltage to stabilize output voltage in case of load variations. As the output capacitor equals 10 F, the measured results are shown in Fig. 10. Certainly, owing to the large output capacitor, the overshoot/undershoot voltage is smaller than that with a small output capacitor. Meanwhile, stability is also guaranteed in the proposed LDO regulator with ARC technique. Besides, Fig. 11 is the statistical representation of measured output voltage with different supply voltages. It is obvious that the LDO regulator with ARC technique has good line regulation. Table III shows the important performance pa-rameters of the proposed circuit compared to previous designs. Referring to Table III, it is clear that the quiescent current of the proposed LDO regulator with ARC technique is much less than those of the previous designs. It causes the recovery time to be a little larger than those of other designs. However, the voltage drop is about 60 mV, which is much better than those of the prior arts. Besides, the performance of load regulation is enhanced by the load regulation compensator. Thus, the load regulation is about 60 V/mA. Compared to other LDO regu-lators, the performance is improved a lot. The figure of merit (FOM) of the proposed LDO regulator with ARC technique is 0.0048 s and close to the values of the previous designs.
V. CONCLUSION
An LDO regulator with ARC technique is presented in this paper. The ARC technique can dynamically and smoothly ad-just the reference voltage, which is proportional to the output error voltage and load condition, to enhance the slew rate of the error amplifier. Not only the undershoot/overshoot voltage can be improved but also the settling time and load regulation can be enhanced significantly.
Fig. 10. Waveforms of an LDO regulator with ARC technique. (a) Load current changes from 1 to 100 mA. (b) Load current changes from 100 to 1 mA (C = 10F, R = 0.5).
Fig. 11. Measured output voltage with different supply voltages.
ACKNOWLEDGMENT
The authors would like to thank RichTek Technology Corpo-ration for its help.
analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 9, pp. 563–567, Sep. 2005.
[2] J. Roh, “High-performance error amplifier for fast transient DC–DC converters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 9, pp. 591–595, Sep. 2005.
[3] K.-H. Chen, H.-W. Huang, and S.-Y. Kuo, “Fast transient DC–DC con-verter with on-chip compensated error amplifier,” IEEE Trans. Circuits
Syst. II, Exp. Briefs , vol. 54, no. 12, pp. 1150–1154, Dec. 2007.
[4] K. Yao, K. Lee, M. Xu, and F. C. Lee, “Optimal design of the active droop control method for the transient response ,” in Proc. Appl. Power
Electron. Conf. Expo., Feb. 2003, vol. 2, pp. 718–723.
[5] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, “Area-efficient linear regulator with ultra-fast load regulation,”
IEEE J. Solid-State Circuits, vol. 40 , no. 4, pp. 933–940, Apr. 2005.
[6] M. Siu, P. K. T. Mok, K. N. Leung, Y.-H. Lam, and W.-H. Ki, “A voltage-mode PWM buck regulator with end-point prediction,” IEEE
Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 4, pp. 294– 298, Apr.
2006.
[7] R. K. Dokania and G. A. Rincon-Mora, “Cancellation of load regula-tion in low drop-out regulators,” Inst. Electr. Eng. Electron. Lett., vol. 38, no. 22, pp. 1300 –1302, Oct. 2002.
[8] J. Ramirez-Angulo , S. G. I. Padilla, R. G. Carvajal, A. Torralba , M. Jimenez, F. Munoz, and A. Lopez-Martin, “Comparison of conven-tional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilities,” in Proc. IEEE
Int. Midwest Symp. Circuits Syst., Aug. 2005, pp. 1151–1154.
[9] R. G. Carvajal , J. Ramirez-Angulo, A. J. Lopez-Martin, A. Torralba , J. A. G. Galan, A. Carlosena, and F. M. Chavero , “The flipped voltage follower: A useful cell for low-voltage low-power circuit design,” IEEE
Trans. Circuits Syst. I, Reg. Papers , vol. 5, no. 7, pp. 1276–1291, Jul.
2005.
[10] I. Padilla, J. Ramirez-Angulo, R. G. Carvajal, and A. Lopez-Martin , “Highly linear VI converter with programmable current mirrors,” in
Proc. IEEE Int. Symp. Circuits Syst., May. 2007, pp. 941–944.
[11] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36–44, Jan. 1998.
[12] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 1041 –1050, Jun. 2004.
[13] W.-J. Hung, S.-H. Lu, and S.-I. Liu, “CMOS low dropout linear reg-ulator with single Miller capacitor,” Inst. Electr. Eng. Electron. Lett., vol. 42 , no. 4, pp. 216–217, Feb. 2006.
of charger and dc–dc converters at the Low Power Mixed Signal Laboratory, National Chiao Tung University, Hsinchu. His current research interests include low-dropout regulator, dc–dc converters, and analog IC design.
Ke-Horng Chen (M’04) received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC De-signer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was engaged in designing power management ICs. He is currently an Associate Professor in the Department of Electrical and Con-trol Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the au-thor or coauau-thor of more than 55 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue (RGB) color sequential backlight designs for optically compensated bend (OCB) panels, and low-voltage circuit designs.
Hong-Wei Huang (S’08) received the B.S. degree
in electronic engineering from Fu Jen Catholic Uni-versity, Hsinchuang, Taiwan, in 2003, and the M.S. degree and the Ph.D. degree in electric engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2005 and 2008, respectively.
He was a member of the Mixed Signal and Power IC Laboratory, Department of Electrical and Con-trol Engineering, National Chiao Tung University, Hsinchu, Taiwan. He is currently with RichTek Technology Corporation, Hsinchu. He is the author or coauthor of more than 15 papers published in journals and conferences, and also holds several patents. His current research interests include power man-agement IC designs and analog ICs of liquid crystal display driver controller.
