快閃記憶體的回顧與展望

(1)

科技技術的演進

科技技術的演進,

,,

,通

通

常都是被市場的需求

所鞭策

(2)

When

Wii / DS

get

hot

(3)

快閃記憶體的回顧與展望

旺宏電子

前瞻技術實驗室

奈米技術研發處

謝光宇處長

2008/06/05

(4)

大綱

1.

1. 1.快閃記憶體簡介

快閃記憶體簡介

2.

2. 2.快閃記憶體記技術的挑戰

快閃記憶體記技術的挑戰

3.SONOS-Type 快閃記憶體

快閃記憶體

4.

4. 4.相變化快閃記憶體

相變化快閃記憶體

5.

5. 5.結論

結論

(5)

半導體記憶體家族

Non-volatile

Volatile

Semiconductor

memory

RAM

DRAM

SRAM

NVM

Incoming

technology

DRAM

SRAM

Floating

Gate

SONOS-Type

(charge trapping

Emerging

ROM &

_Fuse

Phase

Change

FeRAM

MRAM

RRAM

Polymer

Dominate NVM For

the last 25 year

Very potential

emerging NVM

(6)

NAND

NOR

$

(B

il

li

o

n

)

30

40

50 快閃記憶體

快閃記憶體

快閃記憶體 ((NOR, NAND)

NOR, NAND) 產值現況與預估

產值現況與預估

2005

2006

2007

2008

2009

2010

2011

2012

$

(B

il

li

o

n

)

10

20 *

*

NOR Flash growth rate: 2004 2005 2006 2007

NAND Flash growth rate: 2004 2005 2006 2007

-18%

5%

68%

22%

25%

-11%

Web-Feet Research Inc. Mar. 2008

(7)

MOSFET and Flash Memory Cell的差異性

的差異性

V

I

_D

MOS Transistor

Source Gate Drain Oxide ∆ ∆ ∆ ∆Vt Erase State “ 1” Program State “ 0”

∆

∆Vt = -Q / C

FC

V

_G

I

_D

A

B

V

_G

Flash Memory Cell (charge storage type)

A: no charge B: charge stored Source Gate Drain N O O Source Oxide Floating gate Control gate N O O Drain

(8)

Boolean Logic

NOR

NAND

A B C Output A B C Output 1 0 0 0 1 1 0 0 0 1 2 0 0 1 0 2 0 0 1 1 3 0 1 0 0 3 0 1 0 1 4 0 1 1 0 4 0 1 1 1 5 1 0 0 0 5 1 0 0 1 6 1 0 1 0 6 1 0 1 1 7 1 1 0 0 7 1 1 0 1 8 1 1 1 0 8 1 1 1 0 8 1 1 1 0 8 1 1 1 0

A

B

C

Output

VCC

0 0 0 1

A

B

C

Output

VCC

0 0 1 0 0 0 0 1 1 1 1 0

(9)

NOR and NAND 快閃記憶體

快閃記憶體

快閃記憶體矩陣排列結構

快閃記憶體

矩陣排列結構

`` Word line Bit line Unit Cell Contact

Cell

Array

NOR

NAND

Word line Bit line Unit Cell Floating gate Control gate N O O Source line 2F 2F

Layout

Cross

section

10F

2 2

_4F

₂₂ Drain

Single cell structure

Source line 2F 5F Source Oxide gate Drain

(10)

NOR and NAND Flash Memory Array Structure

Cell B

Cell A

Cell C

Cell A

Cell B

Cell C

NOR cell

(11)

快閃記憶體家族及其應用

Flash Memory

NOR

(Code)

NAND

(Data)

高讀取速度

高讀取速度 (High

read current

(>20uA))

高密度

數據寫入速度快

資料抹除速度快

(Code)

(Data)

讀取速度慢

讀取速度慢 (Page reading

is used)

(12)

NOR/NAND - Cell 資料寫入與抹除機制

資料寫入與抹除機制

CHE Program

NOR

NAND

FN Program

Source Gate Drain N O O Source Oxide Floating gate Control gate N O O Drain Source Oxide Floating gate Control gate N O O

Drain DrainSource

Gate Drain N O O

FN Erase

Source Gate Drain N O O Source Drain Source Drain Source Oxide Floating gate Control gate N O O Drain Source Oxide Floating gate Control gate N O O Drain

Source Drain Source Drain

Source Gate Drain N O O

electron

hole

electron

hole

(13)

NOR Flash 微縮趨勢

微縮趨勢

(14)

NAND Flash微縮趨勢

微縮趨勢

(15)

如何增加記憶體之密度

如何增加記憶體之密度?

• Multi-level Cell

(16)

Multi

Multi--Level Cell (MLC) vs. Single

Level Cell (MLC) vs. Single--level Cell (SLC)

level Cell (SLC)

SLC often has better performances (speed, endurance…)

MLC has lower cost (More competitive)

(17)

快閃記憶體技術的挑戰

•記憶晶胞尺寸的微小化

記憶晶胞尺寸的微小化

•穿隧氧化層厚度的極至

穿隧氧化層厚度的極至

•偶合的相互干擾

偶合的相互干擾

•偶合的相互干擾

偶合的相互干擾

•記憶晶胞電性的一致性

記憶晶胞電性的一致性

•記憶晶胞尺寸微小化後之電荷量大

記憶晶胞尺寸微小化後之電荷量大

小之問題

•可靠度

可靠度

(18)

黃光轉印技術

黃光轉印技術 (1)

Year of production

2007

2008

2009

2010

2011

2012

2013

2014

2015

DRAM 1/2 pitch (nm)

65

57

50

45

40

36

32

28

25 NAND Flash will drive the smallest

lithography pitch even 45nm or beyond

ITRS 2007

NAND Flash has become the major technology driving force.

DRAM 1/2 pitch (nm)

65

57

50

45

40

36

32

28

25 Flash 1/2 pitch (nm) (un-contacted poly

54

45

40

36

32

28

25

23

20 MPU/ASIC Metal1 (M1) 1/2 pitch (nm)

68

59

52

45

40

36

32

28

25

(19)

黃光轉印技術

(2)

ITRS 2007

(20)

Tunnel Oxide

Tunnel Oxide 的厚度極限

的厚度極限

Thickness of tunnel oxide

cannot scale below 8 nm

Floating

Gate

Floating

Gate

Source Oxide Floating gate Control gate N O O Drain

Thin oxide:

Frenkel-Poole

tunneling.

Thick oxide:

Beyond

percolation

distance.

Cannot scale

vertically

Cannot scale

laterally

(21)

F. Arai, et. al. 2006 SSDM

Floating Gate

Floating Gate 的偶合作用

的偶合作用

BL direction of FG cell WL direction of FG cell

F. Arai, et. al. 2006 SSDM

V

_th

shift by neighbors

coupling depends on

FG height.

(22)

Impact of FG

Impact of FG--FG Coupling on MLC

FG Coupling on MLC

1.E+03

1.E+04

1.E+05

C

o

u

n

ts

（（（（a

u

））））

WL n Even Write Init

WL n Odd BL After Write

Programmed

After Adj. BL

cell programmed

After Adj. WL

cell programmed

0 1.E+00

1.E+01

1.E+02

1.E+03

0.5

1

1.5

2

2.5

3

3.5

4 Vth(V)

C

o

u

n

ts

_{WL n Odd BL After Write}

WL n+1 Even BL After Write

”

””

”Erase”

“

““

“A””””

“

““

“B””””

“

““

“C””””

Vth

(23)

Floating Gate NAND Scaling Issue - Narrow FG-FG Space

Spacing between two floating gates becomes too

narrow for IPD and control gate poly at < 40nm node.

IPD (Inter Poly Dielectrics)

63nm node NAND array

Control Gate

FG

STI

Si

K. Kim et al., 2006 NVSMW

IPD = 15nm

Minimum

spacing ~

40nm

(24)

Challenge – Cell Uniformity

Flash memory density becomes more than 1Gb (>10

9

9 ₎₎

It is difficult to keep every cells with the same behaviors (from both

process and statistics difficulty)

It requires long program/erase time using algorithms to tighten the

distribution

(25)

Challenge – Reliability

Erratic behavior is

observed after cycling

Need erase algorithms

P. Cappelletti,

et al

., IEDMTech. Dig., p.291, 1994.

Tail bits often happens

during retention

Need error correction

coding (ECC)

(26)

(27)

Gate

O

What is

What is SONOS?

SONOS?

Poly-

S

i

O

xide

N

itride

Source Drain N O

N

itride

O

xide

S

i Substrate

(28)

Advantages of SONOS Device

1. Planar Structure : Much reduced stack height, no gap filling problem

Floating-gate device

Poly gate

ONO

~20 nm

SONOS device

>100 nm

Si

STI

ONO

~20 nm

2. Immune to FG-FG coupling issues

3. Few-Electron Storage Capability

(29)

Problem of SONOS Device

Hole Current Analysis of Various Tunnel Oxide

J

h

(

A

/c

m

2 )

10

-8

10

-7

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

1

15A

20A

25A

By modified FN equations

with hole barrier height =4.5 eV

Required erase current density

R

ea

so

n

a

b

le

e

ra

se

f

ie

ld

Retention loss

Reasonable erase

field <13MV/cm

Reasonable erase

current>10

-4

_A/cm

Good data

Conventional SONOS device cannot find suitable tunnel oxide to

achieve both reasonable erase speed and good data retention.

E

_O1

(MV/cm)

2

4

6

8

10

12

14

16

18 J

h

(

A

/c

m

10

-12

10

-11

10

-10

10

-9

10

-8

30A

35A

40A

_50A

R

ea

so

n

a

b

le

e

ra

se

f

ie

ld

Good data

retention require low

leakage at <3MV/cm

=>

No solution for

any O1 thickness!

(30)

New Innovative Devices

- TANOS & BE-SONOS

New Innovative Devices

- TANOS & BE-SONOS

BE-SONOS

SiO

₂

Gate

Blocking

oxide

TANOS

Al

₂

O

₃

TaN

P+poly

2008 VLSI-TSA Symposium

N+

P-well

SiN

SiO₂ SiN SiO₂

N+

P-well

Trapping

layer

Tunneling

dielectric

SiN

SiO

₂

C.H. Lee et al,

2003 IEDM

Samsung

H.T. Lue et al,

2005 IEDM

Macronix

(31)

TANOS

Metal gate (high work function)

Reduced gate injection

Faster erase speed

Hi-K IPD

Lower EOT

Lower voltage operation

Gate

Blocking

oxide

Trapping

layer

TANOS

Al

₂

O

₃

SiN

TaN

Some uncertainties:

Hi-K IPD

traps charge?

Same issues as SONOS – can we find a “proper” tunnel oxide

thickness to satisfy both

fast erase

and

good retention

?

SiN trapping layer

No gate-gate interference

Effective trapping

“Proper” tunnel oxide thickness

Fast erase

Good retention

N+

P-well

Trapping

layer

Tunneling

dielectric

SiN

SiO

₂

(32)



SiO

₂

_{top dielectric}



 SiN trapping layer

p

+

_{-Poly gate}

_

_n

+

_{-Poly gate}

BE-SONOS

SiO

₂

SiN

SONOS

SiO

₂

SiN

Difference between BE-SONOS and SONOS:

Composite ONO tunneling barrier allows both

fast hole

erasing

and

good data retention

P-poly gate to

reduce gate injection



 SiN trapping layer

Bandgap Engineered

tunnel dielectric

N+

P-well

SiN

SiO₂ SiN SiO₂

_N+

P-well

SiN

SiO₂

(33)

Band Diagram at Retention

B

a

n

d

E

n

e

rg

y

(

e

V

)

-6 -4 -2 0 2 4 6 Si-channel O1 N1 O2 4.5 eV 1.9 eV Conduction Band Valence Band N2

No band offset

Col 3 vs Col 4

Band Diagram at High Electric Field

B

a

n

d

E

n

e

rg

y

(

e

V

)

-4 -2 0 2 4 6 8 10 12 Si-channel O1 N1 O2 Conduction Band Valence Band N2

Band offset

Band-gap Engineering ONO Tunneling Dielectric

During data storage (retention):

Thick tunneling barrier

No direct tunneling leakage

Position (Angstrom)

-20 0 20 40 60 80 -6

No band offset

Position (Angstrom)

-20 0 20 40 60 80 -6 -4

Band offset

At high E-field:

SiN has a small hole barrier

(~2 eV) (SiO

₂

~4.5 eV)

Very easy to offset by E-field

Fast hole tunneling during

erase operation.

(34)

Band-gap Engineered ONO Tunneling Barrier – Hole

Tunneling Current Simulation and Experiment

Efficient hole

tunneling erase

(BE-SONOS)

h

(

A

/c

m

2 )

10

-4

10

-3

10

-2

10

-1

10

0

10

1

Direct Tunneling

O1=1.5 nm

ONO Tunneling

O1/N1/O2

=1.5/2/1.8 nm

Leakage problem

at retention

(SONOS)

ONO tunneling dielectric has a high ON-OFF ratio of hole current.

Suitable hole current of 10

-4

_{to 10}

-3

_A/cm

2 _{during erase @ ~10 MV/cm.}

E

_O1

(MV/cm)

1

2

3

4

5

6

7

8

9 10 11 12 13

J

h

10

-8

10

-7

10

-6

10

-5

FN Tunneling

O1>3 nm

(SONOS)

Suppressed leakage

(BE-SONOS)

No hole FN

tunneling for

thicker oxide

(35)

Comparison of SONOS and BE-SONOS

-1.0 -0.5 0.0 0.5 1.0

V

F B

(

V

)

Erase Speed

150

0 _{C Retention}

Erased from initial

N/O=7/9 nm

150 0C Baking

V

F B

(

V

)

0 1 2 3 4 BE-SONOS SONOS (O1=2 nm) 3300 hours

P

+

_{-poly gate}

BE-SONOS is comparable with

SONOS (O1=2 nm).

The hole tunneling is suppressed for

O1>2.5 nm (SONOS can not use

O1>2.5 nm for the hole tunneling erase)

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 -2.5

-2.0 -1.5

V

Erase Time (sec)

BE-SONOS: -18V

SONOS (O1 = 2 nm): -15V SONOS (O1 = 2.5 nm): -16V

SONOS (O1<=2.5 nm) poor

retention

BE-SONOS sustain very

long-term baking

Baking Time (Hour)

10-4 ₁₀-3 ₁₀-2 ₁₀-1 ₁₀0 ₁₀1 ₁₀2 ₁₀3 ₁₀4

V

-2 -1 0 SONOS (O1=2.5 nm)

P -poly gate

(36)

V

F

B

(

V

)

0

1

2

3

4 V

_G

= - 20V

MANOS

P-sub. O1 SiN Al₂O₃ Gate

V

_G

< 0

e

-e

-P-sub. O1 SiN Al₂O₃ Gate

V

_G

< 0

e -e -e

-Erase Characteristics

Erase Characteristics

of MANOS & BE

of MANOS & BE--SONOS

SONOS

Erase Characteristics

of MANOS & BE

of MANOS & BE--SONOS

SONOS

Erasing time (sec)

10

-6

₁₀

-5

₁₀

-4

₁₀

-3

₁₀

-2

₁₀

-1

₁₀

0

V

F

B

-4

-3

-2

-1

P+ poly gate BE-SONOS

Pt gate MANOS

* S.C. Lai et al, VLSI-TSA, 2007, pp. 14-15.

BE-SONOS

P-sub. O1/N1/O2 N2 SiO2 Gate

V

_G

< 0

h+

e

-P-sub. O1/N1/O2 N2 SiO2 Gate

V

_G

< 0

h+

e

-e

- Erase speed: BE-SONOS > MANOS

(37)

Metal gate/ Al

₂

O

₃

BE

BE--SONOS

SONOS

(BE MANOS)

Metal gate/ Al

₂

O

₃

BE

BE--SONOS

SONOS

(BE MANOS)

BE-SONOS

Gate

SiO

₂

Al

₂

O

₃

BE MAONOS

P-well

N+

P-well

SiN

SiO₂ SiN SiO₂

BE MAONOS

(38)

V

F B

(

V

)

-2 -1 0 1 2 3 4 5 Pt gate MA BE-SONOS Al gate MA BE-SONOS P+ poly-gate BE-SONOS Pt gate MANOS

e

-

V

G

< 0

BE MANOS

High erase speed (Bandgap engineered ONO)

Low erase saturation level (High-k Al

2

O

3

top dielectric)

Large memory window

High work function metal gate is not necessary in BE MANOS.

Time (sec)

10-6 ₁₀-5 ₁₀-4 ₁₀-3 ₁₀-2 ₁₀-1 ₁₀0 -5 -4 -3 -2

V

_G

= -20V

* S.C. Lai et al, NVSMW, 2007, pp. 88-89.

P-sub. O1/N1/O2 N2

h

+

Al

₂

O

₃

Gate

(39)

F

B

(

V

)

0

1

2

3

4

5 Bake@ 85

o

C

0.37/dec. 0.2/dec. 0.12/dec. 0.05/dec. * S.C. Lai et al, NVSMW, 2007, pp. 88-89.

Retention Characteristics of BE MANOS

Baking time (sec)

10

0

₁₀

1

₁₀

2

₁₀

3

₁₀

4

₁₀

5

₁₀

6

₁₀

7

V

F

B

-4

-3

-2

-1

0

0.07/dec. 0.1/dec. 0.19/dec. 0.39/dec.

Data retention of BE MANOS is poor because Al

2

O

3

top dielectric

(40)

BE MANOS

with a SiO

₂

Buffer Layer

BE MANOS

with a SiO

₂

Buffer Layer

BE BE MANOS with

a SiO

₂

buffer layer

BE MANOS

3 2O Al

Φ

Al2O3 Gate e-

Φ

Al₂O₃ Al2O3 O3 Gate e -2008 VLSI-TSA Symposium N2 N2

BE MANOS with a SiO

2

buffer layer is proposed to improve the

reliability of BE MANOS .

The benefits of BE MANOS still can be observed in BE MANOS with a

SiO

₂

buffer layer because the gate injection still can be well

(41)

Read Disturb of BE MANOS

w & w/o a SiO

₂

buffer

Read Disturb of BE MANOS

w & w/o a SiO

₂

buffer

R

e

a

d

N

u

m

b

e

r

106 107 108 109 1010 1011 1012

S4: With SiO₂ buffer

S3: Wihout SiO₂ buffer

1 ms read access time is assumed.

Read failure: Δ

Δ

ΔV

Δ

_FB

= 1V

V

_READ

(V)

4 5 6 7 8 9 10 11

R

e

a

d

N

u

m

b

e

r

102 103 104 105 10

Al gate

Read disturb property is ~ 2 orders of magnitude improved by the

SiO

₂

buffer layer.

Read voltage of BE MANOS with a SiO

2

buffer layer can exceed 7.6

(42)

1

2

3

4 _{S4: BE MANOS with a SiO}

2

buffer

S2: BE-SONOS

S3: BE MANOS

S6: MANOS

BE MANOS

with a SiO

₂

buffer layer

Retention Characteristics

Baking time (sec)

10

0

₁₀

1

₁₀

2

₁₀

3

₁₀

4

₁₀

5

₁₀

6

₁₀

7

V

F

B

(V

)

-3

-2

-1

0

1 @150

o

C

BE MANOS

with a SiO

₂

buffer layer

shows much better data retention.

SiO

₂

buffer layer can block the charge

leakage through Al

₂

O

₃

.

More stable interface between SiO

₂

buffer layer and nitride.

(43)

Cycling Endurance of

BE MANOS with a SiO

₂

buffer

Cycling Endurance of

BE MANOS with a SiO

₂

buffer

F B

(

V

)

0

1

2

3

4

Program: V_G = 19.8 V, 1 ms 2008 VLSI-TSA Symposium

P/E Cycle Number

10

0

₁₀

1

₁₀

2

₁₀

3

₁₀

4

V

F B

-3

-2

-1

0

Program: VG = 19.8 V, 1 ms Erase: V_G = -18V, 10 ms

The memory window is excellently maintained even after 10K

(44)

Bake Retention After P/E Cycling

BE MANOS with a SiO

₂

buffer

Bake Retention After P/E Cycling

BE MANOS with a SiO

₂

buffer

V

F B

(

V

)

2 3 4 Cycle # = 1 Cycle # = 10 @ 150oC 2008 VLSI-TSA Symposium

Baking time (sec)

100 ₁₀1 ₁₀2 ₁₀3 ₁₀4 ₁₀5 0 1 Cycle # = 10 Cycle # = 100 Cycle # = 1k Cycle # = 2k Cycle # = 10k

The initial charge loss becomes larger with the increase of P/E cycles.

Additional shallow traps created during P/E cycling stress.

However, the charge loss during long-term baking is similar.

(45)

(46)

Number of Stored Electrons Decreases Rapidly

Kinam Kim et al., 2005 VLSI

Kinam Kim et al., 2005 VLSI--TSA International Symposium on VLSI Technology P.88TSA International Symposium on VLSI Technology P.88

Memory cell size

40 nm node

No. of Stored electrons

~80 (Vth=4V)

No. of electrons for charge loss tolerance over 10 years (MLC)

5

(47)

Emerging Non

Emerging Non--Volatile Memories

Volatile Memories

FeRAM

MRAM

PCM

W

Chalcogenide Lower electrode Upper electrode

E

PCMO PCMO P+ P+ PtPt P substrate P substrate Bit line 2 Bit line 2 Bit line 1 Bit line 1

Polymer

FE Polymer

RRAM

(48)

Electrical Programming of PCM Cell

W

Top electrode

Bottom electrode

GST

Current

Amorphous

Amorphous, high resistance

Higher current

Shorter pulse

“0”

48 Ta Tx RESETpulse SET t1 t2

Time

Temp.

pulse

Crystalline

Amorphous Tm m.p.

Lower current

Longer pulse

Crystalline，

，

，low resistance

(49)

Comparison Between PCM NOR and NAND

PCM may

substitute NOR

NAND and PCM fit

different markets

PCM

NAND

NOR

5

3

1

4

2 Endurance

XIP

Scalability

different markets

XIP: Execute in Place

Speed: Programming Speed

1 Retention

Speed

Cell Size

(50)

Current Reduction – Sub-litho Contact

Cross-sectional TEM of integrated PCM device RESET current reduced by sub-litho contact