Statistical variability in FinFET devices with intrinsic parameter fluctuations

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Statistical variability in FinFET devices with intrinsic parameter ﬂuctuations

Chih-Hong Hwang

a

, Yiming Li

a,b,*

, Ming-Hung Han

a

Department of Electrical Engineering and Institute of Communications Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan

b

National Nano Device Laboratories, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history:

Received 30 November 2009

Received in revised form 21 January 2010 Available online 25 March 2010

a b s t r a c t

High-j/metal-gate and vertical channel transistors are well-known solutions to continue the device scal-ing. This work extensively estimates the influences of the intrinsic parameter fluctuations on nanoscale fin-type field-effect-transistors and circuits by using an experimentally validated three-dimensional device and coupled device-circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, delay time, and power has been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, can be ignored in AC characteristics due to the screening effect of the inversion layer.

1. Introduction

In nano-device-circuits and systems, the device variability is pronounced and becomes crucial for circuit design[1–9]. The most well-known ﬂuctuation sources on transistors are the random-dopant-ﬂuctuation (RDF) and process-variation-effect (PVE)

[4,6,7]. The RDF comes from the manufacturing process, such as

ion implantation, thermal annealing and so on. Fluctuations of de-vice characteristics including are caused both by a fluctuation in the number of dopants and the particular random distribution of dopants in the channel region[7]. The inevitable variations of pro-cessing conditions, such as the resolution limit of lithography and the grainy nature of photo resist and gate, also impact the device dimensions. The gate length deviation and the line edge roughness are the dominating factors in PVE[4,6,7]. To suppress the impact of these variations, fin-type field-effect-transistors (FinFETs)[10–12]

and high-

j

/metal-gate technology[13] are promising. However, the use of metal as gate material may introduce another source of ﬂuctuation, workfunction ﬂuctuation (WKF). The grain orienta-tion of metal is uncontrollable during growth period[14]; there-fore, the device threshold voltage (Vth) will become a

probabilistic distribution rather than a deterministic value. Ap-proach has been noticed the workfunction ﬂuctuation (WKF); unfortunately, only the device Vthﬂuctuation was concerned and

the scope is limited to the planar transistors[14,15].

In studying the ﬂuctuation of FinFETs, diverse approaches have recently been presented[10–12]; however, the attention is most drawn to the existence of RDF and PVE on transistors. A

compre-hensive understanding of these fluctuations including WKF on Fin-FETs and circuits is lacked. Therefore, this study explores the intrinsic device parameter fluctuations (WKF, PVE, and RDF) on 16-nm-gate silicon-on-insulator (SOI) FinFETs and digital circuits by an experimentally validated three-dimensional coupled de-vice-circuit simulation technique [8,9]. The major variability sources in device’s DC/AC and circuit’s timing/power characteris-tics are explored for the first time. The vast study assesses the fluc-tuation on digital circuit performance and reliability, which can be in turn used to optimize nanoscale devices and circuits.

2. Simulation technique

Fig. 1a illustrates the explored 16-nm-gate SOI FinFETs with

amorphous-based TiN/HfSiON gate stacks with an EOT of 1.2 nm

[14]. The equivalent channel doping concentration is 1.48 1018_cm3_. _{Fig. 1b–d} _{illustrates the RDF-induced}

ﬂuctua-tion, the simulation mainly follows our recent work [7–9]. The PVE-induced ﬂuctuation is examined by Vthroll-off characteristics,

as shown inFig. 1e[7]. The physical models and accuracy of such large-scale simulation approach have been quantitatively cali-brated by experimentally measured results [7,10]. For WKF in

Fig. 1f, a Monte-Carlo approach is proposed for examining such

ef-fect, as shown in Fig. 1g. Based on the average grain size, 4 nm

[14,15], the gate area is ﬁrst partitioned into several parts. Then,

the workfunction of each partitioned area (WKi) is randomized

fol-lowing the properties of metal inFig. 1h[14,15]. The effective de-vice workfunction is then obtained and used for estimation of WKF-induced ﬂuctuations.Fig. 1i is the explored inverter circuit, in which a coupled device-circuit simulation approach[8,9]is em-ployed to ensure the best accuracy. Notably, the device dimension and Vthof both n-type and p-type transistors are the same to

com-pare them on the same basis.

* Corresponding author. Address: Department of Electrical Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan. Tel.: +886 35712121x52974.

E-mail address:[email protected](Y. Li).

Microelectronics Reliability 50 (2010) 635–638

Contents lists available atScienceDirect

Microelectronics Reliability

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3. Results and discussion

Fig. 2a and b displays the components of

r

Vthfor n-type and

p-type planar MOSFETs and FinFETs, respectively. The total

r

Vth,

r

Vth,total, are obtained from the statistical addition as shown in

below:

ð

r

Vth;totalÞ2 ð

r

Vth;PVEÞ2þ ð

r

Vth;WKFÞ2þ ð

r

Vth;RDFÞ2 ð1Þ

The

r

Vth,PVE,

r

Vth,WKF, and

r

Vth,RDF are the PVE-, WKF-, and RDF-induced

r

Vth, respectively. The FinFET shows a signiﬁ-cantly smaller

r

Vth than the planar MOSFET due to its better channel controllability[10]. The RDF and WKF dominate the

r

Vth in both n-type and p-type transistors. The

r

Vth,WKF in p-type Fin-FETs becomes comparable to

r

Vth,RDF due to the large deviation of workfunction. InFig. 1h, the probability for the used material TiN (for NMOS) and MoN (for PMOS) are the same; however, the differences of workfunction in different grain orientation are quite different. The large deviation of workfunction in MoN enlarges the

r

Vth,WKF of p-type FinFETs and makes the

r

Vth,total of p-type FinFETs larger than the n-type FinFETs. Notably, the simulation re-sult is still valid for doped transistors, in which the lightly-doped channel is employed for the suppression of RDF. With sim-ilar simulation methodology, the WKF possesses over 95% Vth ﬂuc-tuation of

r

Vth,total, which shows the signiﬁcance of controlling

WKF.Fig. 3 summarizes the gate capacitance ﬂuctuations (

r

Cg)

with 0 V, 0.5 V and 1.0 V gate bias. Different to the results of Vth ﬂuctuation, the WKF brought less impact on gate capacitance

ﬂuc-tuation. At low gate bias or negative gate bias, the accumulation layer screens the impact of WKF. Additionally, at low gate bias, the total capacitance decreases because of an increased depletion

Fig. 1. (a) The explore SOI FinFET with RDF effect. The number of channel dopants in device may vary from 2 to 22, and the average number is 13(b–d). (e) The Vthroll-off

characteristics for estimating PVE. (f) Metal-gate surface morphology. (g) In estimation of WKF, the gate area is partitioned into several pieces according to the average grain size. The workfunction of each partitioned area (WKi) is a random value, whose probability follows (h). (i) The tested inverter circuit.

0 20 40 60 80 Planar MOSFET FinFET 18.1 8.3 24.3 17.4 61 42.2 Total

σ

V

th

(mV)

69 47.5 NMOS Planar MOSFET FinFET 18.1 8.3 24.3 17.4 61 42.2 69 47.5 Planar MOSFET FinFET 18.1 8.3 24.3 17.4 61 42.2 69 47.5 NMOS

(a)

0 20 40 60 80 100 PVE WKF RDF PVE WKF RDF 16.7 7.5 72.8 33.4 58.8 41.5 Total 95.1 53.8 PMOS 16.7 7.5 72.8 33.4 58.8 41.5 95.1 53.8 16.7 7.5 72.8 33.4 58.8 41.5

σ

V

th

(mV)

σσ

95.1 53.8 PMOS

(b)

Fig. 2. The components ofrVthfor (a) n-type and (b) p-type planar MSOFETs and

SOI FinFETs.

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region. The associated Cg ﬂuctuation is small. As the VG increases, the inversion layer formed and the Cg is now given by the change of inversion charge with respect to surface potential. Therefore, the

r

Cg becomes significant due to the intrinsic-parameter-fluctuated electrostatic potentials. If the high VG is achieved, the inversion layer is formed below the surface of the gate oxide and the total gate capacitance is mostly contributed by the gate oxide capaci-tance (Cox). Therefore, the variation of capacicapaci-tance now again be-comes the variation of capacitance of gate oxide (Cox). Under strong inversion, the gate capacitance is dominated by the inver-sion layer and a small change resulting from the WKF in the volt-age across the MOS structure will induce a differential change in the inversion layer charge density. The WKF is therefore bringing less impact on the gate capacitance fluctuation because the inver-sion charge responds to the change in capacitor voltage (i.e., the WKF is now screened by the inversion layer). Similarly, in RDF, the impact of the individual dopants induced electrostatic poten-tial variation is screened by the inversion layer itself. However, the screening effect of inversion layer is weakened by discrete do-pants positioned near the channel surface. Therefore, the gate capacitance fluctuation is still obviously fluctuated at high gate bias. The results of this study show that the RDF and PVE dominate the gate capacitance fluctuations at all gate bias conditions, respec-tively. The impact of the WKF on Cg is reduced significantly at low and high gate voltage (VG) due to the screening effect. Notably, the

PVE brings direct impact on gate length and therefore inﬂuences the gate capacitance. The PVE-induced gate capacitance ﬂuctuation is independent of screening effect and should be noticed when the transistor operated in high gate bias.

Fig. 4a–cdescribes PVE-, WKF-, and RDF-induced the cuts-off

frequency (FT = vsat/2

p

Lg = gm/2

p

Cg) characteristic ﬂuctuation for the n-type transistors. gm, Cg and vsat are the transconduc-tance, gate capacitransconduc-tance, and the saturation velocity, respectively. The solid lines are the nominal case; the dashed lines are the cases with intrinsic parameter ﬂuctuation; the symbol lines are the aver-aged result. InFig. 4b, the WKF-induced

r

FT diminished as the sat-uration of the carrier velocity occurs due to the screening effect of inversion layer of device, which screens the variation of surface electrostatic potential. The

r

FT then becomes signiﬁcant at high-ﬁeld because of the carrier scattering. The PVE-induced

r

FT, as plotted inFig. 4a, is signiﬁcant at high-ﬁeld owing to the change of gate length. As for the RDF-induced

r

FT inFig. 4c, the

r

FT does not diminish when the saturation of the carrier velocity occurs due to the randomness of carrier-impurity scattering events and carrier velocity variations. Similar to WKF, the screening effect also de-creases the RDF-induced fluctuation; however, the screening effect may be broken by discrete dopant positioned near the channel sur-face. Notably, the nominal and the averaged values of FT are similar for the results of PVE and WKF. However, in RDF, the difference of the nominal and the averaged FT becomes significant as VG in-creases. The inset plots ofFig. 4c are the distribution of electron velocity for the nominal and the RDF-fluctuated cases. The discrete channel dopants induced a relatively negative potential in channel and then twisted the electric field nearby. The distribution of elec-tron velocity is thus altered; therefore increases the vsat and aver-aged FT. The

r

FT is summarized inFig. 4d, in which the RDF and PVE dominate the

r

FT. Different to the results of

r

Vth, the WKF brought less impact on the AC characteristics.

Fig. 5a shows the normalized high-to-low delay time (tHL) and

low-to-high delay time (tLH) ﬂuctuations. The nominal values of

delay time are shown in insets. The normalized ﬂuctuation is the ratio of the standard deviation to the nominal value. The tHLand

tLHdependent on the Vthfor n-type and p-type transistors,

respec-tively; therefore, the trend of

r

tHLand

r

tLHfollow the trend of

r

Vth

σ

C

g

(x10

-3

fF)

0.0 0.5 1.0 1.5 2.0 VG = 0.0 V VG = 0.5 V VG = 1.0 V PVE WKF RDF 0.03 0.07 0.12 1.1 0.42 1.12 1.3 0.04 0.28

Fig. 3. The Cg ﬂuctuation at VG= 0, 0.5, and 1 V for 16-nm-gate FinFETs with

intrinsic parameter ﬂuctuations, WKF, PVE, and RDF.

V_G (V) FT Fluctuation (GHz) 10 20 30 40 50 WKF PVE RDF

V

_G

(V)

F

T

(GHz)

0 50 100 150 200 250 Fluctuated case Nominal case Averaged

(a)

(b)

(c)

V

_G

(V)

F

T

(GHz)

0 50 100 150 200 250

V

_G

(V)

0.0 0.5 1.0

F

T

(GHz)

0 50 100 150 200 250

RDF

WKF

PVE

(d)

S DS D 1.1 1.4 Electron Velocity (x107_cm/s) Nominal RDF 0.0 0.5 1.0 0.0 0.5 1.0 0.0 0.5 1.0 0

Fig. 4. TherFTinduced by (a) PVE, (b) WKF, and (c) RDF. (d) The summarizedrFTfor the studied SOI FinFETs. The inset plots are nominal and RDF-ﬂuctuated electron velocity.

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for n-type and p-type transistors[9]. The major ﬂuctuation source for timing characteristics are RDF and WKF. The overall normalized

r

tHLand

r

tLHof SOI FinFETs inverter are 12.3% and 10.1%,

respec-tively, which are signiﬁcant smaller than that of planar MOSFETs in our previous work (

r

tHL:21.0% and

r

tLH:20.5%)[9].Fig. 5b

esti-mates the power ﬂuctuations for the studied FinFET inverters and the inset shows the nominal value of power. The total power (Ptotal) is consisting of the dynamic power (Pdyn¼ CloadV2DDf0>1),

the short-circuit power (Psc= f0>1VDD

R

Isc(

s

)d

s

), the static power

(Pstat= VDD Ileakage). The f0>1is the clock rate. Iscis the

short-cir-cuit current. T is the switching period. Ileakageis the leakage current.

The Pdynand Pscare the two signiﬁcant factors in total power

con-sumption. In ﬂuctuations of dynamic power (

r

Pdyn), the RDF and

PVE dominate the dynamic power fluctuation. The WKF shows less impact due to the smaller AC fluctuation. Since the short-circuit power is defined by the time of existence of DC path between the power rails and the short-circuit current, the

r

Pscdepends on

the

r

Vthof n-type and p-type FinFETs. The RDF and WKF thus

dom-inate the

r

Psc. The WKF plays a more important role than PVE in

r

Pscbecause of the larger

r

Vthinduced by workfunction difference.

The static power ﬂuctuation (

r

Pstat) is the most signiﬁcant

ﬂuctu-ation source in power. The leakage current is an exponential func-tion of Vth(Ileakage exp(qVth/nkT)); therefore, the

r

Pstatbecomes

signiﬁcant even though the static power is not an important part in total power dissipation. The dominating ﬂuctuation source in

r

Vth

also implies the dominant sources of ﬂuctuation, RDF and WKF. The total power ﬂuctuation (

r

Ptotal) is obtained from

[(

r

PPVE)2+ (

r

PWKF)2+ (

r

PRDF)2]0.5. The statistic addition of

individ-ual fluctuation sources simplifies the variability analysis of nano-devices and circuits, significantly [6]. The

r

Ptotal is 0.042

l

W,

which is 5.2% (

r

Ptotal/Ptotal= 0.042/0.8) of the total power. The

power ﬂuctuation may bring impacts on the reliability of circuits,

such as temperature and in turn degrades the performance of de-vices and circuits.

4. Conclusions

This study explores the metal-gate device DC/AC variability and correspondent circuit’s delay and power ﬂuctuations. The domi-nant variability source in circuits has been studied. The RDF and WKF dominate

r

Vthfor n-type and p-type FinFETs and therefore

rule the

r

tHLand

r

tLHof the explored digital circuits. The overall

normalized

r

tHL,

r

tLH and

r

Ptotal of SOI FinFETs inverter are

12.3%, 10.1%, and 5.2%, respectively. As for the device AC character-istics, the PVE and RDF are the major sources of fluctuation. The influence of the emerging fluctuation source, WKF, is negligible due to the screening effect of inversion layer. We are currently studying the fluctuations of lightly-doped FinFETs and the effects of fin aspect ratio and associated round-top fin structure on Fin-FETs and circuits.

Acknowledgments

This work was supported in part by National Science Council (NSC), Taiwan under Contract NSC-97-2221-E-009-154-MY2 and by the TSMC, Hsinchu, Taiwan under a 2008–2010 Grant.

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Normalized Delay

Time Fluctuaiton (%)

₀ 2 4 6 8 10 12 14 t_HL t_LH 1.5% 5.7% 10.7% 1.4% 4.5% 8.9% (Nominal = 1.01 ps) (Nominal = 2.03 ps)

(a)

PVE WKF RDF PVE WKF RDF

Power Fluctuation (

μ

W)

0.00 0.02 0.04 0.06 P P P P P P P P (unit: μW) 0.80 0.01 0.35 0.44 Nominal P P P P (unit: μW) 0.80 0.01 0.35 0.44 Nominal

(b)

Fig. 5. (a) The normalized high-to-low and low-to-high delay time ﬂuctuations for the explored circuits with WKF, PVE, and RDF. (b) The ﬂuctuations of dynamic power, short-circuit power, static power, and total power, where the inset shows the nominal power.