Memory properties of metal/ferroelectric/semiconductor and metal/ferroelectric/insulator/semiconductor structures using rf sputtered ferroelectric Sr0.8Bi2.5Ta1.2Nb0.8O9 thin films

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Memory properties of metal/ferroelectric/semiconductor and

metal/ferroelectric/insulator/semiconductor structures using rf

sputtered ferroelectric Sr

_0.8

Bi

_2.5

Ta

_1.2

Nb

_0.8

O

₉

thin ﬁlms

Chia-Hsing Huang, Yi-Kai Wang, Hang-Ting Lue, Jun-Yao Huang, Ming-Zi Lee,

Tseung-Yuen Tseng

*

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30050, Taiwan, ROC Received 15 January 2003; received in revised form 29May 2003; accepted 8 June 2003

Abstract

Oﬀ-axis rf magnetron sputtering has been employed to grow Sr0.8Bi2.5Ta1.2Nb0.8O9(SBTN) ferroelectric thin ﬁlms with (115)

preferred orientation on SiO2/Si and Si substrates. The lower temperature and the higher oxygen mixing ratios [OMR, O2/

(Ar+O2)] used in ﬁlm processing lead to reduction in the leakage current densities and widening the memory window of the

resultant metal–ferroelectric–insulator–semiconductor (MFIS) structures. The maximum memory windows of the MFIS structures based on 40% OMR SBTN ﬁlms deposited at 500_{C on SiO}

2/Si substrate are 2.87 and 2.27 V at the bias amplitudes of 10 and 8 V,

respectively. With increasing applied voltage, the memory window also increases. The memory window decreases from 2.27 to 1.59 V after the 1011_{switching cycles at a bias amplitude of 8 V. The capacitance diﬀerence, C, between the two states decreases by}

Keywords:Fatigue; Ferroelectric properties; Films; Lifetime; SBTN; Sputtering; (Sr,Bi)(Ta,Nb)O3

1. Introduction

Ferroelectric thin films are promising for nonvolatile memory applications. At present, the capacitor-type ferroelectric random access memory (FRAM) is used in a destructive readout1,2 _{operation. In principle, it is} much more desirable to develop nonvolatile memory device based on the metal–ferroelectric–semiconductor field–effect transistor (MFSFET) to serve both as the storage element and the sensing device with a non-destructive readout operation.3,4_{However, it is extremely} difficult to prepare the ferroelectric/Si structure with good interface because of the chemical reaction and the interdiffusion of Si and ferroelectric materials. Therefore, an insulating buffer layer is usually inserted between the ferroelectric material and Si, resulting in a metal–ferro-electric–insulator–semiconductor (MFIS) structure.5 9

The Sr0.8Bi2.5Ta1.2Nb0.8O9 film is used as ferroelectric film because the film exhibited no fatigue up to 1010 cycles, and had excellent retention characteristics and a low leakage current in comparison with other related

compounds.10,11 _{The material SiO}

2 is selected as an insulator in MFIS structures because the combination of SiO2–Si is believed to be the most stable and pro-mising structure to control the gate potential precisely through FET channel due to its excellent interface characteristics and also to achieve reliability with regard to fatigue or retention characteristics in the operation of MFISFET.5,8,9 _{Nevertheless, SiO}

2 has a rather small

dielectric constant that reduces the electric field and the polarization in SBT. Therefore, an effective way to increase the electric field in SBT is to decrease the SiO2 film thickness. However, as the thickness of the SiO2 layer is reduced, preventing a mutual diffusion between SBT and Si substrate and hence the degradation of the SiO2–Si interfaces is a challenging task. Therefore, the thickness of this buffer layer must be chosen properly. In this paper, the 27 nm thick SiO2film is employed for maintaining excellent MFIS characteristics.

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* Corresponding author. Tel.: 5731879; fax: +886-3-5724361.

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SBTN thin ﬁlms were determined using ellipsometry and scanning electron microscopy (SEM). The surface roughness and morphology of the SBTN thin ﬁlm deposited at 500_{C in various OMR were observed with}

atomic force microscopy (AFM). The Pt top electrodes with diameters of 150, 250 and 350 mm were deposited by rf magnetron sputtering using a shadow mask

fol-lowed by annealing at 400 _{C. The MFIS and MFS}

structures with the SBTN crystallized ﬁlms sputtered on the SiO2/n-Si and bare n-Si substrates at 500in various OMR were characterized by a Rigaku X-ray dif-fractometer to detect crystalline structure and preferred orientation of SBTN ﬁlms. For the electrical measure-ments, back electrode Al was vacuum evaporated to

form Pt/SBTN/SiO2/n-Si/Al(MFISM) and Pt/SBTN/

n-Si/Al(MFSM) structures. The leakage current density was performed using HP 4156B semiconductor para-meter analyzer with 1 s delay time. The capacitance– voltage (C–V) characteristics were measured using HP4284 LCR meter. To measure the C–V character-istics, the voltage was applied from the accumulation to the inversion with a sweep rate of 0.1 V/s at 100 kHz.

3. Results and discussion

Fig. 1shows X-ray diﬀraction (XRD) patterns of Pt/ SBTN/Si and Pt/SBTN/SiO2/Si deposited at 500C in various OMR and all SBTN ﬁlms are polycrystalline structure. The preferred (115) peak intensity increases

with decreasing OMR for SBTN ﬁlms on SiO2/Si. The

grain size can be calculated from the Scherrer’s formula which is inversely proportional to full width half-max-imum (FWHM) of XRD peak. The average grain size

values for SBTN ﬁlms deposited at 500 _{C for MFS}

structure in 40% OMR and deposited at 500 _{C for}

MFIS structure in 10, 25, and 40% OMR are 12.8, 24.1, 22.8, and 21.6 nm, respectively. Fig. 2(a), (b) and (c)

show the AFM surface images of various OMR SBTN ﬁlms deposited at 500 _{C. The root-mean-square (rms)}

surface roughnesses of SBTN ﬁlms are decreased with increasing OMR during sputtering, which are 52, 46, and 43 nm for 10, 25, and 40% OMR SBTN ﬁlms. The

higher OMR in the sputtering gas decreases the deposi-tion rate of the film. Smaller grain size and a lower film deposition rate at higher OMR may result in a smoother surface. Fig. 3indicates the normalized C–V curves for Pt/SBTN/Si and Pt/SBTN/SiO2/Si structures based SBTN films deposited at 500, 525, and 550_{C in}

40% OMR. The sweeping voltage is changed in either

direction from 10 to +10 V, and the frequency of the

measuring signal is 1 MHz. The memory windows are about 2.87, 2.4, and 0.6 V in MFIS structures with SBTN ﬁlms deposited at 500, 525, and 550 _C,

respec-tively and that is 0.9V in MFS structure.Fig. 4 shows the comparison of the leakage current density vs electric field for the MFS and MFIS structures with SBTN films deposited at various temperatures in 40% OMR. It indicates that leakage current density of the MFS structure is about 110 5_A/cm2_{at 200 kV/cm while the} MFIS structures with 500, 525, and 550_{C SBTN films}

have lower leakage current densities of about 110 9_, 310 9_{, and 110} 8_A/cm2_{at 200 kV/cm, respectively.} The inset in Fig. 4 depicts that the leakage current increases and memory window decreases with increasing substrate temperature. The correlation of the leakage current with memory window implies that higher leak-age current seriously deteriorates the width of memory windows. On the basis of the comparison of the C–V and J–E curves, it is indicated that the interdiffusion at the interface of SBTN/Si is worse than that of SBTN/ SiO2and the higher deposition temperature favors the interfacial diffusion occurred. The interdiffusion occurs at the interface of SBTN/Si during fabrication, leading to increase interface trap density, which also implies a change in Si surface conductivity. This could be detri-mental to the ferroelectric switching property. The fail-ure of controlling the surface conductivity is supposed to be caused by the ferroelectric border traps,12,13_which are the near-interface oxide traps in ferroelectric films

Fig. 1. XRD patterns of the Pt/SBTN/Si and Pt/SBTN/SiO2/Si

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communicating with the underlying Si. Therefore, the buffer layer is necessary for obtaining a better interface. The native oxide might be formed during film deposi-tion process. The charge injecdeposi-tion from the semi-conductor to the film possibly dominates across the native oxide when high concentration traps exist in the native oxide. The memory windows also narrow down as the charge injection and leakage current increase. Hence, the silicon dioxide is very important as a barrier layer in order to lower the leakage current of the device. The OMR used in the sputtering process is an impor-tant factor that affects the crystallinity of SBTN films

deposited at 500_{C, which was conﬁrmed in}_{Fig. 1}_{. The}

(115) peak intensity shown in Fig. 1 decreases with

increasing OMR. The 10% OMR SBTN ﬁlm exhibits the strongest (115) peak intensity, indicating that this ﬁlm has better crystallinity.Fig. 5depicts the curves of

normalized C–V of the Pt/SBTN/SiO2/n-Si(100) MFIS

structure using 500 _{C, various OMR deposited}

SBTN ﬁlms. According to previous investigations,14 16 the ferroelectric property of SBTN can cause the

Fig. 4. Plots of leakage current density vs electric ﬁeld of the MFIS structures with SBTN ﬁlms deposited at various substrate tempera-tures indicated and that of the MFS structure at 500_{C. The inset}

shows relations between the leakage current density at 200 kV/cm and the memory window at various deposition temperatures of SBTN ﬁlms on SiO2/Si substrates.

Fig. 3. The normalized C–V of Pt/SBTN/Si and Pt/SBTN/SiO2/Si

diodes based on the 40% OMR SBTN ﬁlms deposited at 500, 525, and 550_C.

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the high resistively SiO2insulator (band gap, 9eV) layer blocks current ﬂow eﬃciently. The higher OMR in MFIS structure has lower leakage current density because oxygen vacancies diminish with higher OMR leading to the decrease in the electron concentration.

the Pt/SBTN/SiO2/Si structure incorporating SBTN

ﬁlm processed at 500_{C and 40% OMR. The memory}

window increases from 1.06 to 3.34 V when the applied voltage is changed from 4 to 12 V, and the widths of the memory windows are almost in proportion to the applied voltage, as shown in the inset of Fig. 7. This phenomenon is attributed to the non-saturation polar-ization of the SBTN thin ﬁlms. Since the dielectric

con-stant of SiO2 is much lower than that of SBTN, the

voltage drop in the SBTN is much lower than that in the oxide buffer layer. This insufficient electric field can not drive the SBTN thin film into a state of saturated polarization and therefore all the memory windows are operated in non-saturated sub-hysteresis loops. There-fore, increasing the applied voltage would promote the formation of more saturated hysteresis loop and wider memory window. The capacitance matching of the fer-roelectric and insulator layers is important to increase the voltage drop in the ferroelectric layer, which can drive the ferroelectric into larger minor loop.18

Fig. 8 shows the curves of the C–V of the MFIS structure with the SBTN ﬁlms deposited at 500_{C and}

40% OMR ﬁlms for various switching cycles as indi-cated in this plot. The fatigue test was performed using

Fig. 5. The normalized C–V of the MFIS structure based on SBTN ﬁlms deposited at 500_{C for various OMR.}

Fig. 6. Plots of leakage current density vs. electric field of the MFS and MFIS structures with SBTN films deposited in various OMR. The inset shows the performance of the memory window for the structures with various OMR SBTN films.

Fig. 7. The normalized C–V characteristics of the MFIS structure based on 500_{C, 40% OMR SBTN ﬁlm. The inset shows the plot of}

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a bipolar triangle wave of 8 V at 10 kHz below 106

cycles and 1 MHz over 106 _{cycles and the sweeping}

voltage change in either switching from +8 to 8 V.

We survey the fatigue property using two different fre-quencies, 10 kHz and 1 MHz. It would have longer time to reverse the polarization of ferroelectric films at 10 kHz than at 1 MHz. Nevertheless, it could still have enough time to invert the polarization of ferroelectric films in accordance with former study.10 _{It is shown in}

Fig. 8 that the accumulation capacitance reduced from its initial value after several cycles of switching dura-tion. The reduced accumulation capacitance may be attributed to the decreased polarization of the SBTN ﬁlm due to fatigue. Besides, the memory window decreases with increasing switching cycles. We ﬁnd that the memory window degrades over 106_{switching cycles} due to fatigue. The memory window narrows from 2.27 to 1.59V after 1011_{switching cycles.}

Memory retention time was measured for the Pt/

SBTN/SiO2/Si/Al capacitor with the SBTN ﬁlms

deposited at 500_{C and 40% OMR, where ‘on’ and ‘oﬀ’}

writing pulse voltages are +10 and 10 V. The

measurement voltage was kept at 0 V.Fig. 9shows the change in capacitance with time. The data storage and measurement are executed at room temperature. The memory capacitance decreases linearly as a function of the logarithm of the retention time. The capacitance diﬀerence, C, between the two states decreased by 48% after retention time of 7000 s. Such poor retention may be attributed to small remanent polarization to saturation polarization ratio ferroelectric ﬁlm, relatively high leakage current density of the MFIS structure and low dielectric constant of SiO2 insulator layer.14,18 As shown in Fig. 9, the writing at 10 V has a stronger degradation than the writing at +10 V. Such asym-metry is attributed to that the C–V curves (Fig. 3) shift left along voltage axis and do not show symmetrical

with respect to zero voltage. This imprinted behavior may be resulted from some ﬁxed charge in the insulating layer.

4. Conclusions

We have investigated the effects of substrate tem-perature and O2/Ar ratio during rf magnetron sputtered SBTN films on the properties of MFS and MFIS struc-tures based on SBTN films. Increasing the OMR increases the memory window and reduces the leakage

current density. The SBTN ﬁlms deposited at 500 _C

and 40% OMR on SiO2/Si substrate, which formed

MFIS structures, have larger maximum memory

win-dow of 2.87 V at a sweeping voltage from +10 to 10

V. The buffer layer SiO2 is necessary for avoiding the possible interdiffusion between SBTN and Si interface. The reliability of SBTN film has been examined through the fatigue and retention time tests. The width of

mem-ory window decreases from 2.27 to 1.59V after 1011

switching cycles. The capacitance diﬀerence, C, between the two states decreased by 48% after the retention time of 7000 s.

Acknowledgements

The authors acknowledge the ﬁnancial support from the National Science Council of R.O.C. under contract No. NSC 90-2215-E009-100.

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