負回授多級放大電路之設計與實作

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國立交通大學

機械工程學系

碩士論文

負回授多級放大電路之設計與實作

A Feedback Structure for Muti-Cell Linear Power Amplifier

Circuit

研究生：丁之浩

指導教授：成維華教授

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負回授多級放大電路之設計與實作

A Feedback Structure for Muti-Cell Linear Power Amplifier Circuit

研究生：丁之浩 Student：Chih-Hao Ting 指導教授：成維華博士 Advisor：Dr.Wei-Hua Chieng 國立交通大學機械工程學系碩士論文 A thesis

Submitted to Department of Mechanical Engineering College of Engineering

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

In

Mechanical Engineering

August 2009

Hsinchu, Taiwan, Republic of China

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負回授多級放大電路之設計與實作

研究生:丁之浩指導教授:成維華教授國立交通大學機械工程學系

摘要

本文內容提出一負回授多級放大電路的架構，此電路架構延續著多級放大電路可平均將高總功率消耗分散至各級的特點，並加以改良為一負回授架構，以提高其抗雜訊能力。且針對此架構所需的交換式供電系統作研究及實作。文中首先回顧開迴路多級放大電路的分析及數學模型。隨後接續著提出一負回授的多級放大電路架構，對此電路架構提出了數學模型分析及模擬，並對此架構作六級架構的設計與模擬。之後介紹交換式電源供應器的理論、返馳式電源供應器控制電路的分析。最後實際製作一100W 的返馳式電源供應器，並量測其參數。

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A Feedback Structure for Multi-Cell Linear Power Amplifier

Circuit

Student: Chih-Hao Ting Advisor: Dr. Wei-Hua Chieng

Department of Mechanical Engineering National Chiao Tung University

Abstract

This article proposes a feedback structure for the multi-cell linear power amplifier circuit, which maintains the merit to divide total power dissipation to the each module. And the feedback structure can promote the ability to resist noise. The switching power supply needed by the circuit is also discussed in this article. In the beginning, we reviewed the multi-cell linear power amplifier circuit then propose a feedback structure of this circuit. The mathematical model is later build up and a six cells design of this structure is then made and analyzed. The theory of switch mode power converters is introduced. The control circuit of flyback converter is later illustrated. A 100W flyback converter is made and measured to compare with simulations.

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誌

謝

首先真誠的感謝成維華教授和鄭時龍博士，感謝兩位老師在學生兩年的碩士生涯中的指導，不論在求學問的態度與做人處事的道理，讓學生在這兩年收穫良多。感謝實驗室向斌學長、葛雷學長和黑人學長，給予的指導及照顧，學磊、星雲、富源、強哥、文彬、洋豪和小賴學長在經驗上的傳承。感謝同屆身高一般但籃球身手不凡的文祥(小妞猪)、身高差不多但手比我長 10 公分的冠今(砍怕啦)、熱愛宅物的宅宅安鎮(槍鎮)和愛看書的志隆，還有一票熱愛電力電子的學弟們。系足的同胞們在我研究所兩年共同奮戰，拿到了大機盃冠軍、系際盃冠軍、交大足球聯賽冠軍等等，還把我踢的世界波拍成影片，實在是揪甘心。最後也是最重要的是要感謝我的父母及家人，做為我強力的後盾讓我能無後顧之憂全力衝刺學業，三不五時還帶一些好料的來讓我有一兩餐能不用吃交大的…….。丁之浩謹於 2009.08

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List of Tables

Table2.1 The amplifiers’ specifications………... 53

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List of Figures

FIGURE1.1 DIFFERENCE AMPLIFIER ... 28

FIGURE1.2 OUTPUT SIGNALS FROM DIFFERENCE AMPLIFIER ... 28

FIGURE1.3 ISOLATED FLOATING DIFFERENCE AMPLIFIER ... 29

FIGURE1.4 A FLOATING SIGNAL MODULE ... 29

FIGURE1.5 THE CASCADED MULTI-CELL AMPLIFIER ... 30

FIGURE2.1 THE TOPOLOGY OF THE FEEDBACK STRUCTURE ... 31

FIGURE2.2 THE SYSTEM BLOCK DIAGRAM OF THE FEEDBACK STRUCTURE ... 32

FIGURE2.3 THE BODE PLOT OF THE UNCOMPENSATED SYSTEM... 32

FIGURE2.4 THE CIRCUIT OF THE PASSIVE FILTER ... 33

FIGURE2.5 THE BODE PLOT OF THE COMPENSATED SYSTEM ... 33

FIGURE2.6 THE GAIN MARGIN OF THE ISSPICE SIMULATION ... 34

FIGURE2.7 THE PHASE MARGIN OF THE ISSPICE SIMULATION ... 34

FIGURE3.1 THE BASIC TOPOLOGY OF THE FLYBACK CONVERTER ... 35

FIGURE3.2 PRIMARY WINDING CURRENT AND VOLTAGE AT CCM. ... 35

FIGURE3.3 THE EQUIVALENT CIRCUIT OF THE CONVERTER AT 0~DTS ... 36

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FIGURE3.5 PRIMARY WINDING CURRENT AND INPUT CURRENT AT DCM. ... 37

FIGURE3.6 RCD TURN-OFF SNUBBER ... 37

FIGURE3.7 RCD TURN-OFF SNUBBER STATE 1 ... 38

FIGURE3.8 RCD TURN-OFF SNUBBER STATE 2 ... 38

FIGURE3.9 CURRENT-MODE CONTROL SCHEME ... 39

FIGURE3.10 SIMPLIFIED CURRENT CONTROL CIRCUIT ... 39

FIGURE3.11 DETERMINATION OF THE PEAK CURRENT-MODE DUTY CYCLE ... 40

FIGURE3.12 SIMPLIFY BLOCK DIAGRAM OF UC3844 ... 40

FIGURE3.13 MAGNETIC ISOLATED FEEDBACK CIRCUIT ... 41

FIGURE3.14 OPTICAL ISOLATED FEEDBACK CIRCUIT ... 41

FIGURE4.1 EXPERIMENTAL SETUP ... 42

FIGURE4.2 THE FLYBACK CONVERTER ... 42

FIGURE4.3 CEMENT RESISTOR LOADS ... 43

FIGURE4.4 OUTPUT RIPPLE 0.08V AT NO LOADING SITUATION ... 43

FIGURE4.5 OUTPUT RIPPLE 0.12V AT 32W LOADING SITUATION ... 44

FIGURE4.6 OUTPUT RIPPLE 0.12V AT 100W SITUATION ... 44

FIGURE4.7 THE V_GS AND V_S SIGNAL AT NO LOADING SITUATION ... 45

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FIGURE4.9 THE VGS AND VS SIGNAL AT 100W LOADING SITUATION ... 46

FIGURE4.10 THE VGS AND VDS SIGNAL AT NO LOADING SITUATION ... 46

FIGURE4.11 THE V_GS AND V_DS SIGNAL AT 32W LOADING SITUATION ... 47

FIGURE4.12 THE V_GS AND V_DS SIGNAL AT 100W LOADING SITUATION ... 47

FIGURE4.13 V_GS AND SENSING CURRENT AT NO LOAD ... 48

FIGURE4.14 V_GS AND SENSING CURRENT AT 32W LOAD ... 48

FIGURE4.15 VGS AND SENSING CURRENT AT 100W LOAD ... 49

FIGURE4.16 VGS AND VDS AT NO LOAD ... 49

FIGURE4.17 V_GS AND V_DS AT 32W LOAD ... 50

FIGURE4.18 V_GS AND V_DS AT 100W LOAD ... 50

FIGURE4.19 SPICE SIMULATION MODEL OF THE FLYBACK CONVERTER... 51

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Chapter 1 Introduction

1.1. General Introduction

The Multi-Cell Linear Power Amplifier is proposed for applications involving high capacitive load and large voltage output swing, such as piezoelectric (PZT) actuator drivers. Voltage amplifiers are often used to drive piezoelectric actuators because they can precisely generate any waveform. The Multi-Cell Linear Power Amplifier is one of the topology of voltage amplifiers. It has the advantages including approximately constant corner frequency and high common mode rejection ratio (CMRR), which offer the accuracy and linearity for piezoelectric applications. Strong electrical isolation keeps high voltages away from equipment and reduces the risk if electrical shock. The drawback of the multi-cell circuit topology is that many isolated switching power supply units are required to feed the individual cell of power.[1][2]

1.2. Literature Review

An innovative amplifier called Multi-Cell Linear Power Amplifier is proposed for application involving high capacitive load and large voltage output swing. It’s bandwidth can up to 100kHz with ±200V output swing.[1][2]

Nomenclature

α

,

α

N ,

α

P : Resistance ratio of closed-loop amplifier

D

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amplifier

C

A

_{: Closed loop dc gain of operational amplifier}

I

A

_,

A

_I_{: Differential gain and frequency response of isolation amplifier}

i

V

_{+ , i}

V

− : Input signal of difference amplifier

b

V

: Bias voltage of the power supply

bs

V

: Bias voltage of isolation amplifier

in

V

: Input voltage of isolation amplifier

o

V

: Output voltage of difference amplifier

o

V

_{+ , o}

V

− : Output voltage of floating signal module

out

V

: Differential output voltage of floating signal module

ps

V

_{: Power supplies of operational amplifier}

G

V

: Ground potential

ω

: Frequency operator

c

ω

: Cutoff frequency of operational amplifier

,

ci cs

ω ω

: Bandwidth of isolation and difference amplifier

1.2.1. Differential Amplifier

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(

)

1

D c

A

j

ω

_ω

ω

=

+

D

A

_(1.1)

Where ωc denotes the 3dB cut off frequency. Providing a bias voltage on

the power supply Vb, the output voltage of the difference amplifier, as

illustrated in Fig 2.1, is expressed as

(

1 )

(

1 )

N o P i N i b P N

V

α

V

α

V

α

+ −

α

⎛

⎞

=

_⎜

−

_⎟

+

⎝

⎠

D D

A

(1.2)

The bandwidth of the difference amplifier ωcs is derived from (1.2) for AD

>>αN

1

D D c cs c N N

A

ω

α

⎛

⎞

=

_⎜

+

_⎜

_⎟

≈

⎝

⎠

⎝

⎠

(1.3)

If Vb = 0, then the output voltage swing is bounded by the power supply, i.e.,

±Vps. As illustrated in Figure 1.2(a), the dotted line indicating the output signal is

bounded by solid lines indicating power supply voltages. Conversely, the supply voltages may be varied, i.e., Vb = Vb(t), to yield different output signals as

indicated in Figure 1.2(b). Such a power supply providing output voltage Vps +

Vb(t) is called the floating power supply. An op-amp feedback application

should always be restricted by a constant-gain-bandwidth product [3]. According to (1.3), the difference amplifier has a large close-loop bandwidth (ωcs) corresponding to a small close-loop voltage gain (αn).

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A difference amplifier using floating power supplies can generate sufficiently large output signal with respect to the ground as shown in Figure 1.2(b). Such an amplifier structure may comprise an isolation amplifier, and a difference amplifier with floating power supplies called the isolated floating difference amplifier, as illustrated in Figure 1.3. Providing the differential gain of the isolation amplifier AI and the bias voltage of the isolation amplifier Vbs, the

differential outputs of the isolation amplifier may be obtained where

2

i in b b s

V

+

= −

A

I

V

+

V

+

V

_(1.4a)

2

i in b b s

V

−

=

A

I

V

+

V

+

V

_(1.4b)

The isolation amplifier imposes a bias voltage Vb on the input signal of

difference amplifier. The biased input signal is then fed into the difference amplifier to modify the common-mode voltage. For simplicity, αP-1 =αN-1 = α

may be selected, where AD >>α>>1. By substituting (1.4a) and (1.4b) into (1.2),

the output of an isolated floating difference amplifier is obtained as

in o b N

V

α

V

α

= −

+

D I D

A A

A

(1.5)

1.2.3. Multi-Cell Amplifier

A. Floating Signal Module

Figure 1.4 illustrates a floating signal module based on the isolated floating difference amplifier. Each floating signal module comprises one non-inverting

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amplifier and one inverting amplifier. The output swing is therefore double the swing that would be produced by a single difference amplifier. The output voltage of the non-inverting amplifier is

in o G N

V

α

V

α

+

=

+

D I D

A A

A

(1.6)

The output voltage of the inverting amplifier is

in o G N

V

α

V

α

−

= −

+

D I D

A A

A

(1.7)

The overall output of the floating signal module is

2

o u t o o _in N

V

α

V

α

+ −

=

−

=

+

D I D

A A

A

(1.8)

The output signal is independent on the ground pin, which is the key to the flexibility of the floating signal module.

B. Cascaded Multi-Cell Amplifier

The cascaded multi-cell amplifier shown in Figure 1.5 consists of familiar floating signal modules in cascaded connection. Each floating signal module is made from low voltage devices and provides both positive and negative analogous voltage levels. In the following, the superscript i refers to the ith cell of floating signal module. The isolated bipolar power sources are required to

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provide sufficient power to the floating signal module and to deliver a specified power to a load. Previous results indicate that each floating signal module yields two output voltages VO+(i) and VO-(i), which are equal in magnitude but anti-phase.

The non-inverting output terminal of the (i-1)th cell of the floating signal module is directly connected to the inverting output terminal of the ith cell of the floating signal module

(i 1) ( )i o o

V

₊−

=

V

₋ (1.9) Substituting (2.6), (2.7) into (2.9) and rearrange the terms yields

( )i (i 1)

2

G G in N

V

α

V

α

−

=

+

D I D

A A

A

(1.10)

The maximum output voltage between the non-inverting output terminal of the

ith cell of the floating signal module and the inverting output terminal of the first cell of the floating signal module is

( )i (1) ( )i (1) O O in G in G N N

V

α

V

α

V

α

+

−

=

D

₊

I

+

D

₊

I

−

D D

A A

A

(1.11)

Solving the ground potential among each cell circuit by recursively commutating from (1.10) enables (1.11) to be rewritten as

( )i (1)

2

O O in N

V

i

α

V

α

+

−

=

D

₊

I D

A A

A

(1.12)

The synthesized voltage waveform may be specified as a sum of output voltages of floating signal module cells. Any number of floating signal modules may

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have in general any number of cells.

1.3. Thesis Structure

In the next chapter we will propose a feedback structure for the Multi-Cell Linear Power Amplifier which we suggest to have better performance than the open-loop structure. And we will introduce the flyback converter which is one topology of the isolated switching power supply. The converter is for the purpose to feed the Multi-Cell Linear Power Amplifier circuit.

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Chapter 2 Feedback Structure for Multi-Cell Linear

Power Amplifier

2.1. Topology of the Feedback Structure

A feedback structure is proposed here to improve the multi-cell circuit. The advantage of the closed-loop system is that the use of feedback make the system response relatively insensitive to external disturbances and internal variations in system parameters and still keeps the advantages of the multi-cell amplifier. The topology of a feedback structure is shown in Figure 2.1.In this topology we use several resistors to take out a part of output voltage for feedback use. The feedback circuit is consisted of two op-amps and one isolation amplifier. The first op-amp is use to adjust the take out voltage to meet the input limitation of the isolation amplifier. The second op-amp is use to adjust the feedback parameter to meet our design. The isolation amplifier is used for the purpose of electrical isolation between the input device and the output load.

2.2. Mathematical Modeling of the Feedback Structure

To analyze the characteristic of the closed loop circuit, we develop a mathematical model. First we introduce the electronic components we selected for this circuit. For the isolation amplifiers we choose HCPL 7820, for the difference amplifiers we choose LM3875 and for the op-amps we choose LM6361. The abbreviated specifications of these electronic components are shown in Table 2.1. By the discussion we made in chapter 1 we can write the

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mathematical model of isolation amplifier as

(

)

1

I ci

A

j

ω

_ω

ω

=

+

I

A

_(2.1)

And repeat (1.1) we write the mathematical model of the difference amplifier as

(

)

1

D cs

A

j

ω

_ω

ω

=

+

D

A

_(2.2)

The other op-amps we used in the circuit we can write their models separately as 1 1

(

)

1

o p co p

A

j

ω

_ω

ω

=

+

o p 1

A

(2.3) 2 2

(

)

1

o p co p

A

j

ω

_ω

ω

=

+

o p 2

A

_(2.4)

Therefore we can draw our system block diagram as in Fig 2.2 according to the topology and the models we made. Where Aop1(jω), and AI(jω) has

already shown in (2.1) and (2.3). Forward transfer function G(jω) and feedback transfer function H(jω) can be express as (2.5) and (2.6).

(

j

ω

)

=

2 i

o p 1

(

j

ω

)

I

(

j

ω

)

D

(

j

ω

)

G

A

(2.5)

(

j

ω

)

=

(

j

ω

)

I

(

j

ω

)

o p 2

(

j

ω

)

H

K

A

(2.6)

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output voltage sampling circuit which we will discuss in the next section. The closed-loop system transfer function T(jω) becomes

2 (

)

(

)

1 2

(

) (

)

2 (

)

(

)

(

)

1 2

(

)

(

)

(

)

(

)

(

)

(

)

i

j

i

j

i

j

i

j

ω

=

+

=

+

op1 I D I op2 op1 I D

G

T

G

H

A

K

A

(2.7)

2.3. System Compensation

First, we give the values of the parameters of the model refer to the specifications [9][10][11] of the components we choose and the DC gain of

T(jω) to be 40. The values of the parameters are shown in table2.2. Initially, we

let K(0) to be a constant, which implement to the circuit is a voltage divider using the resistors. The Bode plot of the mathematical model is shown in Figure2.3. We can see from the simulation result that the system phase margin and the system gain margin are both negative, so the system is unstable and need to be compensated.

We set our target to compensate the phase margin to have at least 30 degrees. The phase lead-lag compensator is the method we utilize. Considering the gain cross frequency at wg and the slope is -60db/Decade, we plan to use three

passive filters to compensate. The circuit of the passive filter is shown in Figure2.4. We can write the transfer function of the passive filter as

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, 2 1 1 2 , 1 2 1 1 1 2

1

2 ₁

2

p out p in

V

R

R C s

R

V

R

_{R C s}

R

+

=

+

₊

+

(2.8)

Where Vp,in is the input voltage of the passive filter and Vp,out is the output

voltage of the passive filter. Then we can write the pole introduce by the passive filter as (2.9). 1 2 2 1 1

2R

R

π

R C

+

1

2

(2.9)

And the zero introduce by the passive filter as (2.10).

1 1

R C

π

1

2

(2.10)

We set the zeros of the three passive filters around wg and the poles according

to the following equation

If we use three identical passive filters, the value of the resistors can be decided by (2.11) and the poles should be (2.12)

3 2 1 2

(0)

2 R

R

⎛

⎞

= ⎜

₊

⎟

⎝

⎠

K

_(2.11) 3 1 1

(0)

R C

π

K

1

2

(2.12)

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3 1 2 2 1 1

2 (

j

)

R

R C

ω

π

+

⎛

⎞

= ⎜

⎟

⎝

⎠

K

1

2

(2.13)

2.4. Simulation Result

In this section, we will simulate both mathematical model and the circuit by software. In Figure2.5 we show the compensated system Bode plot, which we set the zeros at 1.7MHz and poles at 20.6MHz. We can see from Figure2.5 that the compensated system has a gain margin 11.1dB and a phase margin 44.4degrees. Figure2.6 and Figure2.7 show the IsSpice simulation Bode plot of the circuit implementation of the system. We can see from Figure2.6 and Figure2.7 that the compensated system has a gain margin 4.7dB and a phase margin 33degrees. The difference between the two simulations occurs at frequency over 1MHz, which we believe is cause by the high frequency poles that we didn’t consider in the mathematical models.

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Chapter 3 Switch-Mode Power Converter

3.1 . Introduction of Switch-Mode Power Converter

Switch-mode power converter is one of the circuit structures of DC to DC converter. Switch-mode power converter has three basic topologies: step-down, step-up, step-down/up. Those three are the fundamental and non-isolated ones, each of the three can correspond to their isolated topologies which are: buck, forward (step-down), boost (step-up), flyback (step-down/up). Depending on their operating conditions, switch-mode power converters may operate either in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). Under transient conditions, the operation of power converters may slide in and out both modes. For closed-loop control of converters, two fundamental mechanisms, voltage-mode control or current-mode control, are generally employed. Current-mode control has been often used for its superior performance. Current-mode control can further subdivided into average-current control and peak-current control. The switch-mode power converter we tend to design and use is the flyback converter. The chip IC we used, UC3844, is a fixed frequency current-mode control IC.

3.2 The Flyback Converter

In this section we will introduce the basic theory of the flyback converter. First, as shown in Figure3.1 we can see the basic topology of the flyback converter. When we turn on the switch, the primary winding will store energy from the primary current. In the same time, the second winding has been cut off

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because the diode is reversed biased. Therefore, there is no energy transformed from primary side to the second side at this period. As we turn off the switch, the primary current comes to zero, and the transformer polarity reversed. The energy we stored in the first period then transformed to the second side. Repeating this mechanism by controlling the voltage across the gate and source of the MOSFET, we can get a continuous power output.

According to three different operating mode: continuous conduction mode (CCM), discontinuous conduction mode (DCM) and boundary conduction mode (BCM), we will have three discussions respectively.

Several assumptions we have to make before the discussions:

1. Assuming the output capacitor is ultra large and let the output voltage to be constant.

2. The circuit is operating under steady-state. 3. The switch and the diode are ideal.

4. The duty ratio is D, which means the switch turned on DTs and turned off

(1-D)Ts, where Ts is the period of one switching cycle.

A.. Continuous conduction mode (CCM)

Figure3.2 show the current and voltage when the converter is operating under continuous conduction mode. Figure3.3 and Figure3.4 show the equivalent circuit of the converter at 0~ DTs and DTs ~ Ts .

When the switch is on the equivalent circuit as shown in Figure3.3 we can write the primary voltage as

= =

, 0

≤ ≤

L i n p p s

d i

v

L

t

D T

d t

(3.1)

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Where VL is the voltage across the primary side of the transformer, Vin is the

input voltage and L is the primary inductance of the transformer. We can write the change of primary winding current ∆ip as

in s p p

V DT

i

L

Δ =

_(3.2)

The secondary winding current due to the reverse bias of the diode is zero

0

s

i

=

(3.3) Thus, we can see from (3.3) that primary winding current gains linearly and no current flow through secondary winding when the switch is on.

As we turn off the switch at the time DTs ~ Ts, the primary winding voltage is

shown as follow 1 2

p p out

N

p

di

s s

V

L

DT

t T

N

dt

= −

=

≤ ≤

_(3.4)

Where Vout is the output voltage, N1 is the turns of primary winding and N2 is

the turns of secondary winding. From (3.4) we can get the change of primary winding current 1 2

(1

)

out s p p

V

D T N

i

L

N

−

Δ =

_(3.5)

While we assume operating under steady-state, the change of the winding during a cycle should be zero. By this relation and using (3.4) (3.5) we can acquire the relation between output voltage and input voltage as

1 2

1

out in

D N

V

D N

=

−

(3.6)

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B. Boundary conduction mode (BCM)

When the flyback converter is working at boundary conduction mode, is the situation that the primary winding current decreases to zero at DTs.

C. Discontinuous conduction mode (DCM)

The discontinuous conduction mode during the time 0~DTs, the switch is on

and just like operating under CCM, the primary winding current gains linearly and no current flow through secondary winding. But the difference with CCM is that the primary winding current of DCM will decrease to zero before the next cycle starts. Thus, each cycle the primary winding current will start from zero, we can calculate the peak current of the primary winding from (3.2)

0

in s pp p p

V DT

i

L

= + Δ =

_(3.7)

Assuming no energy loss during energy transfer, we can derive the relation between the output voltage and the input voltage by the following equations.

The average of input current Iin which we can calculate from the area under

Figure3.5 (b) divided by a cycle time

2

in s in p

V D T

I

L

=

_(3.8)

The input power is equal to the output power

2 2 2

2

in s o p

V D T

V

L

=

R

(3.9) From (3.9) we can get the relation between the output voltage and the input voltage

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2

s out in p

T R

V

V D

L

=

(3.10)

We can see as the comparison of CCM and DCM that the relation between the output voltage and the input voltage only depends on the turn ratio and duty ratio at CCM but depends on switching frequency, output load, primary inductance and duty ratio.

3.3 The Switching Component

In this section we will introduce the switching component used for dc to dc converters. In the early 1970s, switch-mode power converters employed bipolar junction transistors as the main power switch exclusively, since MOSFET were not yet mature for power application. Bipolar transistor switches at that time, in general, also operated at switching frequencies of lower tens of kilohertz. The latter is attributed to the slower response time as a result of distributed junction capacitances in the bipolar transistor’s junctions. More important, the bipolar transistors are current-controlled devices. Effective control of the transistor requires timely injection, or removal, of charge carriers into, or out of, the base terminal.

In contrast to the bipolar transistors, the MOSFETs are voltage-controlled transistors, which is easier to drive than the bipolar transistors. In normal situation, no gate current is required. The region between the gate and the channel of the MOSFET form a parallel-plate capacitor. Only when MOSFETs are switched on/off will required current to build up the conducting channel.

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To understand the switching behavior of MOSFETs, we have to consider the parasitic capacitances that exist between pairs of terminals: CGS, CGD, and CDS.

As a consequence of these capacitances, the transistor experiences a turn-on delay td(on) corresponding to the time required to charge the equivalent input

capacitance to the threshold voltage VT. As shown in Figure3. , the rise time tr is

defined as the time it takes to charge the gate from the threshold voltage to the gate voltage required to have the MOSFET in the triode region VGSP. The turnoff

delay time td(off) is the time required for the input capacitance to discharge, so

that the gate voltage can drop and vDS can begin to rise. As vGS continues to

decrease, we define the fall time tf as the time required for vGS to drop below the

threshold voltage and turn the transistor off. Typical switching time is about 30ns to 50ns and is faster than the bipolar transistor.

3.4 Resistor-Capacitor-Diode(RCD) Snubber

In general, the load lines encountered in a switch-mode power converter are inductive. On the i-v coordinate plane, the power switch current and voltage traverse a nonlinear trajectory. This load behavior exerts significant stress on the switch in the form of local power dissipation that elevates the devices operating temperature and reduces reliability. The switching losses are associated with the transitory nature of rising and falling of switch voltage and current at the very moment of on/off state changes. The voltage rising due to an inductive di/dt kickback is more pronounced when the switch turns off. We, therefore, focus on the turnoff snubbers, which are intended to manage the rate of falling current.

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a preferred, guided way, diodes are also used. Figure3.6 gives a turn-off RCD snubber.

The operating sequence of the circuit can be briefly described as follows. When the power switch terminates conduction, the inductive load voltage flips polarity (Figure3.7). The clamping diode conducts and keeps the magnetizing current flowing without interruption; though at a decreasing rate. The action moves the energy previously stored in the magnetic core to the capacitor. When the next on-cycle commences, the clamping diode disengages the RC network and the capacitor discharges its contents (Figure3.8).

3.5 Current Mode Control

By nature, signals in current forms have advantages over those in voltage form, since voltage is an accumulation of electron flux and, therefore, slow in time as far as control mechanism is concerned. In the early 1980s, this understanding spawned a new tide in switch-mode power supply design, namely, the current-mode control. In this control mode, the averaged or peak current of magnetic origin is employed in the feedback loop of switch-mode power converters. Figure3.9 demonstrates the general feature of a current-mode control scheme. We can see from the current-mode control scheme that two loops are involved. The external loop includes the output voltage feedback sensing error amplifier. The internal loop is the current sensing circuit.

Here, we will give an example to illustrate how peak-current current-mode control is working. In Figure 3.10 shows that the instantaneous switch current is sensed by a current sensing resistor Rsen that provides isolation and current

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scaling. The switch is turned on at a clock edge. It is turned off when the sensed current in voltage form intercepts the error voltage, Ve (Figure3.11).

The current-mode control has some benefit compared with voltage-mode control [16]:

1. The peak current flow through the power MOSFET can be limited. Because of the peak current of the inductance is measured directly, we can limit the peak current by adjusting the current sensing resistor.

2. Can overcome the saturation of the transformer. If the transformer is saturate, extreme large current will shut down power MOSFET by the peak-current sensing mechanism.

3. Has better response time than the voltage-mode control process. 4. Has better performance to loading current modulation.

3.6 Current Mode Control Circuit

The PWM controller we used in our circuit is the UC3844, which is a peak-current current control mode IC. The UC3844 is a high performance fixed frequency current mode controllers. It is specifically designed for Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each

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with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single pulse metering. The simplified block diagram is shown in Figure3.12.

3.7 Isolated Feedback

Both voltage and current feedbacks are used effectively in modern power converters. Early on, voltage feedback had the upper hand, since it was easy to implement. Non-isolated voltage feedback is even easier. It takes just a node voltage and two resistors as a voltage divider. Of course, its simplicity hides its shortcoming—no isolation. To implement isolated voltage feedback, either magnetic or optical means must be employed. The magnetic approach requires that the voltage being fed back must first be converted into AC form. The optical approach requires that the feedback voltage be in current form to drie an optical element. Therefore, the requirement of isolation wipes out the advantage voltage feedback has over current feedback. The latter stands out as a better choice for that reason and others. In addition to the ability of offering isolation, current feedback is also less prone to noise. A voltage node with certain impedance can be easily influence by radiated emissions with no direct connection. In contrast, it is not so easy to inject unwanted current into a current-sensing branch without direct physical contact.

In Figure3.13 is a magnetic isolated feedback circuit and Figure3.14 is an optical isolated feedback circuit. The optical isolated feedback circuit involved an opto-coupler, a precision shunt regulator and several resistors. As shown in Figure3.14, the output to be regulated feeds a voltage divider that samples the

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output. The sampled output is compared with a reference voltage, Vref=2.5V,

residing in TL431, a precision shunt regulator. The error voltage is converted into drive current for the opto-coupler, an LED and phototransistor combination. The current transfer ratio of the opto-coupler transfers the drive current. The opto-coupler output current is converted into a feedback voltage via a resistor.

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Chapter 4 Experimental Results

4.1 Experimental Setup

Figure4.1 displays the photograph of the experimental setup of the flyback converter. The flyback converter is designed to supply 100W power and multiple output voltages: +40V, +15V, 0, +5V, -15V and -40V. It’s maximum output voltage is 80V and output current is 1.2A.. Input voltage we give 110VAC. The load we use for testing is shown in Figure 4.3. The flyback implementation circuit schematic is in Figure 4.20.

4.2 Results of the Experiment

We measured the gate to source voltage, drain to source voltage, source voltage and 80V output of flyback converter with different loadings: no loading, 32W and 100W. The actual value due to different scale we take is not correctly shown in the oscilloscope capture picture, so we annotate the actual value below the photograph except for the source voltage, we exchange its actual voltage value to the current flow through by dividing sensing resistor Rs. Figure4.4,

Figure4.5 and Figure4.6 show the output voltage and ripple for different loads. Figure4.7, Figure4.8 and Figure4.9 show the gate to source voltage which is the switching signal for the MOSFET and the source voltage which is the peak-current sensing signal. Figure4.10, Figure4.11 and Figure4.12 show the gate to source voltage and the drain to source voltage which is the voltage stress that the MOSFET has to bear.

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In Figure4.13, Figure4.14 and Figure4.15 we show the simulation result of gate to source voltage and the current on the peak-current sensing resistor. Figure4.16, Figure4.17 and Figure4.18 we show the simulation result of gate to source voltage and the drain to source voltage. The simulation spice model demonstrated in Figure 4.19.

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Chapter 5 Conclusions

The feedback structure of multi-cell linear power amplifier offers a way to drive high output power loads while the total power dissipation divided into each of the modules. The switch mode flyback converter provides a way to feed the individual cell of power. Integration of the two can be a more compact and flexible solution for high power output usage.

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Reference

[1] Yung-Cheng Tung , Shyr-Long Jeng and Wei-Hua Chieng, “Multi-Level Balanced Isolated Floating Difference Amplifier,” IEEE Transactions on Circuits and Systems I, vol.55, no.10, pp.3016-3022, November 2008. [2] Shyr-Long Jeng and Yung-Cheng Tung, “A Multi-Cell Linear Power

Amplifier for Driving Piezoelectric Loads,” IEEE Transactions Industrial Electronics, vol. 55, no.10, pp.3644-3652, October 2008.

[3] Keng wu, “Switch-Mode Power Converters Design and Analysis,” Elsevier Inc., 2006

[4] 張碩編著，“自動控制系統＂，台北，全華，1998.

[5] Giorgio Rizzoni, “Electrical Engineering,” Revised 4 ed., Thomas, 1997. [6] Adel S. Sedra, Kenneth C. Smith, “Microelectronic Circuits,”5th ed., New

York: Oxford, 2004

[7] 鄭培璿編著，“IsSpice 在電力電子與電源轉換器上的應用＂，台北，全華，1999.

[8] 岡村迪夫，楊武智編譯，“運算放大電路設計＂，台北，全華，1998. [9] HCPL 7820 (High CMR Analog Isolation Amplifier) Datasheet, Agilent

Technologies, INC.

[10] LM3875 (Audio Power Amplifier) Datasheet, National Semiconductor Corp., August 2000.

[11] LM6361 (High Speed Operational Amplifier) Datasheet, National Semiconductor Corp., May 1999.

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[13] LM431 (Adjustable Precision Zener Shunt Regultor) Datasheet, National Semiconductor Corp., March 2002.

[14] UC3844 (Current mode PWM Controller) Datasheet, Texas Instrument, June 2007

[15] IRF 840 (N-Channel Power MOSFET) Datasheet, Fairchild Semiconductor, 2002. [16] 江炫璋譯，“電力電子學＂，台北，全華，2001 [17] 胡江毅，李偉，“單端反激式變換器在兩種工作模式下特性的比較＂，華東地區第二屆電源技術研討會論文，2002 [18] 長谷川彰譯，“轉換式電源供給器＂，台北，全華，1992 [19] 謝沐田著，“高低頻變壓器設計＂，台北，全華，2008 [20] 梁適安編著，“交換式電源供給器之理論與實務設計＂，台北，全華， 2008 [21] EPARC 著，“電力電子學綜論＂，台北，全華，2008 [22] 內山, 明治著，“圖解簡明運算放大器電路＂，台北，新興， 2006 [23] 長橋, 芳行著，“OP 放大器之寬頻帶電路設計＂，台北，全華，1987

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Figures

Figure1.1 Difference amplifier

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Figure1.3 Isolated floating difference amplifier

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Figure2.2 The system block diagram of the feedback structure

Figure2.3 The Bode plot of the uncompensated system

-200 -150 -100 -50 0 50 Mag ni tud e ( dB ) 104 105 106 107 108 -450 -405 -360 -315 -270 -225 -180 -135 -90 -45 0 P has e ( deg ) Bode Diagram

Gm = -24.3 dB (at 4.62e+005 Hz) , Pm = -69.9 deg (at 1.38e+006 Hz)

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Figure2.4 The circuit of the passive filter -200 -150 -100 -50 0 50 M agni tude ( dB ) 104 105 106 107 108 109 -450 -360 -270 -180 -90 0 P has e ( deg) Bode Diagram

Gm = 11.1 dB (at 8.06e+006 Hz) , Pm = 44.4 deg (at 2.4e+006 Hz)

Frequency (Hz)

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Figure2.6 The gain margin of the IsSpice simulation

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Figure3.1 The basic topology of the flyback converter

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Figure3.3 The equivalent circuit of the converter at 0~ DTs

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Figure3.5 Primary winding current and input current at DCM.

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Figure3.7 RCD turn-off snubber state 1

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Figure3.9 Current-mode control scheme

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Figure3.11 Determination of the peak current-mode duty cycle

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Figure3.13 Magnetic isolated feedback circuit

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Figure4.1 Experimental setup

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Figure4.3 Cement resistor loads

VGS: signal1 Voutput: signal2 Vavg=81.52V, Vpp=0.08V

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Figure4.5 Output ripple 0.12V at 32W loading situation

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VGS: signal1 VS: signal2 Isen,min=0A, Isen,max=0.864A

Figure4.7 The VGS and VS signal at no loading situation

VGS: signal1 VS: signal2 Isen,min=0A, Isen,max=1.44A

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VGS: signal1 VS: signal2 Isen,min=1.44A, Isen,max=3.552A

Figure4.9 The VGS and VS signal at 100W loading situation

VGS: signal1 VDS: signal2 VDS,min=4V, VDS,max=184V

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Figure4.11 The VGS and VDS signal at 32W loading situation

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Figure4.13 VGS and sensing current at no load

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Figure4.15 VGS and sensing current at 100W load

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Figure4.17 VGS and VDS at 32W load

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Tables

Isolation Amplifier (IC:HCPL7820)

Input voltage Swing ±200mV Gain 8

Bandwidth 200kHz

Difference Amplifier (IC:LM3875)

Maximum Supply Voltage ±84V Output Dissipation 50W Maximum Output Current 6A Gain-Bandwidth Product 8MHz Open-Loop Gain 120dB Slew rate 11V/μs

Op-Amp (IC:LM6361)

Maximum Supply Voltage ±15V Gain-Bandwidth Product 40MHz

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Description of parameter Parameter Value of parameter DC gain of OpAmp1 1 op

A

4 Cut-off frequency of OpAmp1

ω

cop1 20000000π DC gain of OpAmp2 2 op

A

5.5 Cut-off frequency of OpAmp2

ω

cop2 14540000π DC gain of difference amplifier

A

D 15 Cut-off frequency of difference amplifier

ω

cs 1066000π DC gain of isolation amplifier

A

I 8 Cut-off frequency of isolation amplifier

ω

ci 400000π

Output voltage sampling resistor ratio

K(0) 0.000595

負回授多級放大電路之設計與實作

國 立 交 通 大 學

機械工程學系

碩 士 論 文

負回授多級放大電路之設計與實作

A Feedback Structure for Muti-Cell Linear Power Amplifier

Circuit

研 究 生：丁之浩

指導教授：成維華 教授

負回授多級放大電路之設計與實作

負回授多級放大電路之設計與實作

摘要

A Feedback Structure for Multi-Cell Linear Power Amplifier

Circuit

Abstract

誌

謝

Contents

List of Tables

List of Figures

Chapter 1 Introduction

1.1.

General Introduction

1.2. Literature Review

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國立交通大學

碩士論文

研究生：丁之浩

指導教授：成維華教授

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