Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

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Impact of SOI thickness on device performance and gate oxide reliability of Ni

fully silicide metal-gate strained SOI MOSFET

Cheng-Li Lin

a,⇑

_{, Wen-Kuan Yeh}

b a

Department of Electronic Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 407, Taiwan b

Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung 811, Taiwan

a r t i c l e

i n f o

Article history: Received 8 August 2010

Received in revised form 17 October 2010 Accepted 24 October 2010

Available online 3 November 2010 Keywords:

SOI Strained SOI Strain silicon

Contact etch stop layer (CESL) Gate oxide reliability TDDB

Low frequency noise (LFN)

a b s t r a c t

This study investigates the effects of oxide traps induced by SOI of various thicknesses (TSOI= 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner TSOIdevices have a smaller net remaining stress in gate oxide film than thicker TSOIdevices, and thus possess a smaller bulk oxide trap (NBOT) and reveal a superior gate oxide reliability. On the other hand, the thicker TSOIdevices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker TSOIdevice has a higher bulk oxide trap (NBOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker TSOIdevices in this CESL strain technology. In addi-tion, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.

1. Introduction

In past few years, the evolution of CMOS technology is contin-uing to scale down the gate length to gain high performance and to achieve the ULSI product application. But with aggressive scal-ing the device gate length, some impacts of scalscal-ing will degrade the device performance, such as carrier mobility and off-state drain leakage current[1,2]. In order to improve these issues, some tech-niques such as strain engineering and silicon-on-insulator (SOI) technology have been proposed [3–7]. Recently, SOI combined strain engineering has been considered to be one of the most promising technology to realize high performance ULSI with low power consumption and high carrier mobility [8–11]. Below 65 nm technology node and beyond, SOI MOSFET was fabricated toward thin silicon thickness (so-called the fully depleted SOI, FDSOI) to suppress the short channel effects (SCEs) and decrease the parasitic bipolar transistor effects [12–14]. Some strain technologies were implemented to improve the device mobility, e.g. global approach which results in the biaxial stress in the carrier

transport plane by growing a thin epitaxial Si or Ge layer on a Si1 xGexrelaxed buffer layer deposited on silicon substrate capped

buried oxide (BOX) insulator[5]. A tensile strained-Si (x < 0.5) and a compressive strained-Ge layers (x > 0.5) were fabricated for n-and pMOSFET, respectively. Local stressors are the other ap-proaches; in one of the local stressors, the uniaxial stress is gener-ated in the channel using a recessed SiC or SiGe source/drain region to produce the tensile (for nMOSFET) or compressive (for pMOS-FET) strain[5]. Another local stressor method uses the SiN-based contact etch stop layers (CESL) to create uni- or biaxial strain in the channel. The tensile CESL or compressive CESL can be obtained depending on the deposition recipe (via different hydrogen con-tent) of the CESL for n- and pMOSFET devices[5,15]. Since the CESL is process-compatible, this is a simple method to produce strain (tensile or compressive) in the channel as well as large gains to im-prove the device performance and demonstrate excellent device reliability[16–18]. Moreover, fully silicide (FUSI) gate, such as NiSi, has some advantages over the metal gate, including tunable work function and compatible CMOS process[19,20]. It is believed that SOI technology with fully depleted SOI (FDSOI) and CESL strain engineering as well as FUSI gate is one of the most promising candidates for future technology node application. While some

doi:10.1016/j.mee.2010.10.030

⇑Corresponding author. Tel.: +886 4 24517250x4969; fax: +886 4 24510405. E-mail address:[email protected](C.-L. Lin).

Contents lists available atScienceDirect

Microelectronic Engineering

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literatures have reported the effects of CESL and SOI thicknesses on the device performance[8–11,17,18], very few studies focus on the reliability and oxide trap distribution proﬁle in the gate oxide with CESL strain and various SOI silicon thicknesses, and they are still not clearly understood. In this paper, we investigate the impact of SOI thickness on strained SOI MOSFETs, including the device performance, gate leakage current, gate oxide reliability of time dependent dielectric breakdown (TDDB) and oxide trap distribu-tion identiﬁed using low frequency noise measurement (LFN)

[21,22]. Moreover, we found that the gate oxide quality is corre-lated to the SOI thickness.

2. Experimental

SOI CMOSFETs were fabricated on smart-cut SOI substrate with (100)-channel orientation. A 90-nm fully Ni-silicide (FUSI) gate MOSFET with 1.5-nm-thick nitride gate oxide, was formed on SOI substrate with 400-nm-thick buried oxide (BOX) at three silicon thicknesses (TSOIs) of 50, 70 and 90 nm, separately. The nitride gate

oxide was grown using rapid thermal oxidation in NO ambient. Then, composite oxide/SiN spacers were formed using low temper-ature processing, and source/drain junctions for n- and pMOSFET were formed using arsenic and boron ion implantations, respec-tively. After poly Si gate deposition and patterning, a spike anneal-ing process was used for source/drain activation. Then, Ni was deposited and formed to fully Ni silicide using two step rapid ther-mal processes (RTP1 340 °C/RTP2 520 °C) by conventional

self-aligned silicidation (salicide) process [10]. Then, SiN ﬁlms with three different strain processes were deposited. They are low ten-sile stress 38-nm-thick CESL, high tenten-sile stress 70-nm-thick CESL, and high compressive stress 70-nm-thick CESL. The low tensile CESL is a standard recipe for 90 nm CMOSFET process and was used as a reference of comparison with the two higher stress CESLs in this paper.Fig. 1shows the schematic view of CESL capped Ni-FUSI gate strained SOI MOSFET devices with various SOI thicknesses. Drain current and subthreshold swing of DC characteristics were measured by the Agilent 4156C. The conventional carrier separa-tion method was used to measure the gate leakage current; in this method, voltage source was applied to the gate terminal while the source/drain and bulk terminals were ground [23]. Gate oxide TDDB reliability was measured at inversion operation mode under constant voltage stress (CVS). The time to breakdown (TBD) of gate

oxide was determined by the onset of the ﬁrst breakdown in the gate current versus time plot[24]. In addition, a BTA9812 noise analyzer was used for the noise measurement at various gate biases and frequencies to study the amount of oxide trap charge and to identify the location of oxide trap charge for gate oxide quality analysis[21,22].

3. Results and discussion

Figs. 2 and 3show the temperature dependence of drain cur-rents for the FUSI gate SOI n- and pMOSFETs, respectively, of vari-ous TSOIs with low and high tensile (or compressive) stresses.

Carrier mobility of both n- and pMOSFETs can be enhanced, respec-tively, by tensile and compressive stress. It can be seen fromFigs. 2 and 3that the drain current (or mobility) is improved by increasing TSOI, especially for the high tensile and high compressive stresses,

respectively. To investigate the interface state at the SiO2/Si

inter-faces of MOSFETs with various SOI thicknesses and with different stress CESLs, the subthreshold swing (SS) is a useful index to verify the variation of the interface state.Fig. 4shows the subthreshold swing behavior of nMOSFETs with different stress CESLs and TSOIs.

For low tensile CESL devices, the SS was improved by decreasing TSOI, suggesting that less interface states were formed with a

thin-ner TSOI. On the other hand, for devices with high tensile CESL, we

found that the SS was degraded by CESL, especially with a thinner TSOI, suggesting that more interface states were formed by high

tensile stress with a thinner TSOI. Similar tendency was observed

in pMOSFETs (not shown). Thus, more interface trap charges (Nit)

Fig. 1. Schematic view of CESL capped Ni-FUSI gate strained SOI MOSFET with various TSOIs (50, 70 and 90 nm).

Low Stain CESL

NMOSFET

High Tenslie CESL

I

D

(

A/

m)

Temperature ( C)

nMOS

L= 90 nm

90nm

70nm

50nm

T

SOI

Low Tensile CESL High Tensile CESL

Fig. 2. Temperature dependence of drain currents for FUSI gate SOI nMOSFETs with low and high tensile CESLs. The drain current (or mobility) of nMOSFET can be enhanced by high tensile CESL.

High Compressive CESL

Low strain CESL

PMOSFET

pMOS

L= 90 nm

90nm

70nm

50nm

T

SOI

Low Tensile CESL

Temperature ( C)

I

D

(

A/

m)

Fig. 3. Temperature dependence of drain currents for FUSI gate SOI pMOSFETs with low tensile and high compressive CESLs. The drain current (or mobility) of pMOSFET can be enhanced by high compressive CESL.

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were possibly induced by high stress CESL, especially for the MOS-FETs with a thinner TSOI.

Device driving capability is related to the channel carrier mobil-ity, which is composed of three components of phonon scattering (

l

ph), surface roughness scattering (

l

sr) and Coulomb scattering

(

l

coul) [25]. For the nMOSFETs with low tensile CESL capped

(Fig. 2), thinner TSOIdevices have lower drain currents, and the

low mobility is limited by phonon scattering [26]. In addition, the parasitic series resistance is another possible factor to slightly limit the drain current. With high tensile stress CESL capped, the mobility enhancement is associated with the suppression of intervalley phonon scattering, and the mobility is limited by the intravalley phonon scattering[27]. Thus, electron mobility for the nMOSFETs is enhanced by tensile CESL [9], while the extent of mobility degradation is larger for the devices with thinner TSOI

for high tensile CESL, which is associated with phonon scattering limited mobility [26]. Additionally, surface roughness scattering for thinner TSOIdevices with high tensile CESL is also another

pos-sible factor to decrease the carrier mobility due to higher interface state in the thinner TSOI devices (Fig. 4) [25,28]. Similar results

were observed for the pMOSFET SOI devices as shown inFig. 3. Compared to nMOSFET (Fig. 2), the extent of drain current (mobil-ity) degradation is larger for pMOSFET with thinner TSOIfor both

low tensile and high compressive CESLs. This indicates more pho-non scattering and/or surface roughness scattering limited carrier mobility for pMOSFET with thinner TSOIs, especially for the case

of high compressive CESL.

Larger CESL stress can also induce larger oxide trap charges, resulting in threshold voltage shift, gate leakage current variation and reliability degradation. The gate leakage currents of n- and pMOSFET are also correlated with strain stress[5,29–31]. Fig. 5

shows the gate leakage currents of n- and pMOSFETs with 50 or 90 nm SOI thickness and various stress CESLs. For nMOSFETs with 50 nm SOI thickness capped with tensile stress CESLs (Fig. 5a), the high tensile CESL capped devices show lower leakage current irre-spective of operation mode (accumulation or inversion). It was also reported in literature that higher tensile stress applied on devices (tensile stress in channel direction) show lower leakage current in inversion mode operation (positive gate voltage)[32]. For the gate leakage current in inversion mode, it is dominated by the elec-tron tunneling from the p-type SOI[23]. The lower leakage current of nMOSFET with high tensile stress CESL is attributed to the band gap narrowing of SOI substrate due to the strain leading to the low-er ground enlow-ergy level in the invlow-ersion laylow-er of channel[29,33]. As a result, the effective barrier height (/eff) for the emission of

elec-tron from the p-type SOI substrate across the oxide/Si interface is increased. In addition, the transverse effective mass (m

eff) of

elec-tron is also increased. These two factors decrease the probability of electron tunneling across oxide and lead to the decrease of gate leakage current. As for the gate leakage current at the accumula-tion mode operaaccumula-tion (negative gate voltage), the leakage current is dominated by the electron tunneling from the FUSI gate. Pre-sumably the work function of the FUSI gate and the effective mass of electron are changed by the high tensile CESL stress, resulting in the lower gate leakage current[34]. For pMOSFETs with 50 nm SOI thickness, high compressive CESL devices also show lower leakage current than the low tensile CESL devices, as shown inFig. 5b. In

80

90

100

110

120 T

SOI

improve S.S.

NMOS

W/L=10um/90nm

CESL

induced S.S.

Degradation

90

70

Subt hr eshol d Sw ing (m V/ decade)

SOI Thickness nm

Low Stress

High Tensile

50 nMOS

W/L=10 m/90 nm

High Tensile

Low Tensile

Fig. 4. Subthreshold swing (SS) versus SOI thickness with low and high tensile CESLs for nMOSFETs. Subthreshold swing can be improved using thinner TSOIand low tensile CESL, but degraded by high tensile CESL.

Gate Voltage (V)

ak

age Cu

rr

ent (A)

nMOS

Gate Le

ak

age Cu

rr

ent (A)

Compressive

(b)

2 1 0 1 2

pMOS

Compressive

(d)

2 1 0 1 2

Gate Voltage (V)

pMOS

T

SOI

= 90nm

W/L 3.6/10 m

Fig. 5. Gate leakage currents of FUSI gate SOI (a) n- and (b) pMOSFETs with 50 nm SOI thickness, and (c) n- and (d) pMOSFETs with 90 nm SOI thickness, for various stress CESLs.

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inversion mode operation (negative gate voltage), the leakage cur-rent is dominated by the hole tunneling curcur-rent from the n-type SOI[23]. The lower leakage current of pMOSFET with high com-pressive stress CESL is attributed to the band gap narrowing of the SOI substrate, leading to the increase of effective barrier height of hole tunneling across oxide from the n-type SOI[31]. In addition, the strain-induced band warping creates a larger out-of-plane mass[31]. These two factors reduce the probability of hole tunnel-ing from the n-type SOI, resulttunnel-ing in the lower gate leakage cur-rent. As for the accumulation mode operation (positive gate voltage), it is believed that the gate leakage current is dominated by the electron tunneling from the n-type SOI, and presumably the effective barrier height and/or effective mass of electron are changed by the high compressive CESL stress, resulting in the low-er gate leakage current [34]. For the 90-nm-thick-SOI n- and pMOSFETs, the opposite tendency of leakage current behavior (as compared to the 50-nm-thick SOI devices) was observed as shown inFig. 5c and d, respectively, for various stress CESLs. This suggests that the thicker SOI (TSOI= 90 nm) induced another factor to

in-crease the gate leakage currents of n- and pMOSFETs capped with high tensile and high compressive CESLs, respectively, irrespective of operation mode (inversion or accumulation). It is believed that the SOI thickness will impact the gate leakage current of SOI MOS-FETs capped with various stress CESLs. We rearrange the data in

Fig. 5to appear as those shown inFig. 6, in which we can clearly see the gate leakage currents variation between the low and high stress CESL devices (Fig. 6a and b versusFig. 6c and d). Apparently, the leakage current behavior is affected by the devices SOI thick-ness and CESL stress. Furthermore, it can be seen from Fig. 6c and d that the extent of gate leakage current change is larger for n-type devices with increasing TSOI thickness. Increasing TSOI is

beneﬁcial to improve carrier mobility, but it will also increase gate leakage current as well as power consumption. The gate oxide quality is another factor to affect the gate leakage current[35]. We presume that a large amount of oxide traps is the possible rea-son to lead to the increase of leakage current for n- and pMOSFETs with thicker SOI thickness (TSOI= 90 nm) capped high tensile and

high compressive CESLs, respectively.

To look into the quality of gate oxide, we employed the TDDB measurement.Fig. 7shows the gate leakage current versus time

plots under TDDB CVS testing for n- and pMOSFETs capped with high tensile and high compressive CESLs, respectively. It can be seen that the thinner SOI devices (TSOI= 50 nm) reveal longer time

to breakdown (TBD) and more clear oxide hard breakdown behavior

(Fig. 7a and b). For thicker SOI devices (TSOI= 90 nm), however,

shorter TBDand more soft breakdown and/or progressive

break-down behavior were observed (Fig. 7c and d). The soft breakdown and progressive breakdown are correlated with the trap charges in oxide ﬁlm[36]. This indicates more oxide traps in oxide ﬁlm for the thicker SOI n- and pMOSFETs capped with high tensile and high compressive CESLs, respectively.Fig. 8shows the TBDWeibull

dis-tributions for n- and pMOSFETs capped with high tensile and high compressive stresses, respectively, for various SOI thicknesses. Lar-ger TBD was found for the devices with thinner SOI thickness

regardless of n- or pMOSFETs. This indicates that the gate oxide quality is degraded with increasing TSOIthickness for the devices

capped with high stress CESLs. Furthermore, it can be seen from

Fig. 8that the extent of gate oxide quality degradation is larger for n-type devices with increasing TSOIthickness. Increasing TSOI

is beneﬁcial to improve carrier mobility, but it will also degrade the gate oxide TDDB reliability. This is consistent with the larger gate leakage current behavior for the devices with thicker SOI thickness (Fig. 6c and d).

A low frequency noise spectrum analysis was employed to eval-uate the distribution of oxide traps in the gate oxide for the devices with various TSOIs capped with high stress CESLs. The oxide traps

(NT) contain two components of interfere trap (Nit) and bulk oxide

trap (NBOT).Fig. 9shows the input-referred voltage noises versus

gate overdrive voltage of noise measurement at a low frequency of 20 Hz for the n- and pMOSFETs of various SOI thicknesses capped with different stress CESLs. By comparing the noise data of low tensile and high tensile (or high compressive) stresses, we found that the noises of both n- and pMOSFETs with high tensile stress and high compressive stress, respectively, are all larger than those with low tensile stress at all gate voltages, especially for the thicker SOI devices (TSOI= 90 nm). This indicates that higher tensile

(or compressive) stress CESL will induce more oxide traps (NT). To

investigate the location (proﬁle) of oxide traps in the oxide ﬁlm, the input-referred voltage noise variation at various operation fre-quencies were observed.Fig. 10shows the input-referred voltage

Gate Voltage (V)

= 50nm

T

SOI

= 90nm

(a)

nMOS

Low Tensile

2 1 0 1 2

Gate Voltage (V)

Gate Le

ak

age Cu

rr

ent (A)

W/L 3.6/10 m

(c)

2 1 0 1 2

Gate Voltage (V)

nMOS

High Tensile

T

SOI

= 50nm

age Cu

rr

ent (A)

= 50nm

Gate Voltage (V)

pMOS

High Compressive

T

SOI

= 50nm

T

SOI

= 90nm

W/L 3.6/10 m

Fig. 6. Gate leakage currents of FUSI gate SOI (a) n- and (b) pMOSFETs with low tensile stress CESLs, and (c) n- and (d) pMOSFETs with high tensile and high compressive CESLs, respectively, with various SOI thicknesses.

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noises of low frequency noise measurement for the n- and pMOS-FETs with high tensile and high compressive stress, respectively. For the nMOSFETs with high tensile stress, it was found that thick-er TSOIdevices revealed larger noise signal than the thinner TSOI

de-vices (Fig. 10a); this is attributed to higher NTin the thicker TSOI

devices. The slope of noise spectrum is correlated with the density distribution of Nitand NBOT, and it follows the form of 1/fa[5,22,37],

where the exponent

a

can be calculated by neglecting the genera-tion–recombination noise (GR noise). If the NBOTdensities in gate

SOI

90nm

pMOS

10

7

(a)

(b)

(c)

(d)

Vg = 3V

Time (sec)

Lea

k

age

Curr

en

t

(A)

Fig. 7. Gate leakage currents of time dependent dielectric breakdown (TDDB) testing for (a) n- and (b) pMOSFET with 50 nm SOI thickness, and (c) n- and (d) pMOSFET with 90 nm SOI thickness capped with different stress CESLs (high tensile and high compressive CESLs for n- and pMOSFETs, respectively) under constant voltage stresses of Vg= 3 V and Vg= 3 V for n- and pMOSFETs, respectively.

-4 -3 -2 -1 0 1 2 1 10 100 1000 10000 ln (-l n(1 -F)) -4 -3 -2 -1 0 1 2 1 10 100 1000 10000 ln (-ln (1 -F) )

(b)

pMOS

V

G

= 3V

(a)

nMOS

V

G

=3V

T

SOI

T

SOI

Ln(-Ln(1-F))

Time to breakdown T

BD

(sec)

Fig. 8. TBDWeibull distributions of (a) nMOSFET with high tensile stress and (b) pMOSFET with high compressive stress under constant voltage stresses of Vg= 3 V and Vg= 3 V, respectively, for various SOI thicknesses.

90 nm (HC)

50 nm (HC)

90 nm (LT)

50 nm (LT)

90 nm (HT)

50 nm (HT)

90 nm (LT)

50 nm (LT)

N

T

(+)

N

T

(+)

(a) nMOS

W/L=10 m/90nm

V

DS

=0.05V

Freq= 20Hz

(b) pMOS

W/L=10 m/90nm

V

DS

= 0.05V

Freq= 20Hz

|V

GS

-V

th

| (V)

0.1

1

0.1

1 S

VG

(V

2

/Hz)

S

VG

(V

2

/Hz)

T

SOI

T

SOI

Fig. 9. Input-referred voltage noises versus gate overdrive voltage (Vgs–Vth) of noise measurement at a low frequency of 20 Hz for (a) nMOSFETs with low and high tensile stresses, and (b) pMOSFETs with low tensile and high compressive stresses, for various SOI thicknesses.

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ﬂicker noise is mainly resulting from Nit. For the n- and pMOSFETs

capped with high stress CESLs studied in this work, the exponent values (

a

) are all larger than 1 with large gate overdrive voltage. Moreover, the

a

values of thicker TSOI(90 nm) devices are larger

than those of thinner TSOI(50 nm) devices for both n- and

pMOS-FETs (1.43 versus 1.16 and 1.14 versus 1.08, respectively). This im-plies that the density of NBOTlocated near the FUSI/oxide region is

larger than that of Nitlocated at the oxide/Si-substrate interface for

the thicker TSOIdevices. From the results of the subthreshold swing

(SS) (Fig. 4), the input-referred voltage noise analysis (Fig. 9) and the low frequency noise spectrum (Fig. 10), the number and distri-bution of oxide trap (NT) composed of interface trap (Nit) and bulk

oxide trap (NBOT) in gate oxides of various TSOIs devices with high

and low stress CESLs can be depicted. For devices with high stress CESLs, thinner TSOIdevices have a larger Nitand a smaller NBOT, and

the total oxide trap (NT= Nit+ NBOT) is relatively smaller than that

the thicker TSOIdevices. On the other hand, the thicker TSOIdevices

have a smaller Nitand larger NBOT, and the total oxide trap (NT) is

relatively larger than that of the thinner TSOIdevices. Therefore,

the number of NTinduced by the high stress CESL is mainly

con-tributed by the NBOT. This is consistent with the behavior of gate

leakage currents of n- and pMOSFETs with thicker TSOI(90 nm)

capped with high stress CESLs that revealed larger leakage current, as shown inFig. 6c and d, respectively. Additionally,Fig. 10a and b also clearly indicates that thicker SOI (TSOI= 90 nm) induced higher

density of NBOTin the nMOSFETs than the pMOSFETs. This result is

also consistent with the gate leakage current behavior (Fig. 6c and d) and the TDDB behavior (Fig. 8).

The origin of oxide trap is considered to be due to the stress in gate oxide ﬁlm[5]. In addition, due to the fact that the thermal

expansion coefﬁcient of Si (

a

Si) is larger than that of oxide (

a

ox)

[38], strain will be induced in top layer of SOI after gate oxide growth and CESL capping, as shown inFig. 11. For low tensile (or no stress) CESL capped MOSFETs with different SOI thickness, as shown inFig. 11a, slight tensile stress (

r

T) and thus slight strain

in SOI ﬁlm was induced mainly by the gate oxide ﬁlm and low ten-sile (or no stress) CESL capping, compensating the slight compres-sive stress (

r

C) in gate oxide, thus leading to slightly alleviate down

T) in gate oxide, thus leading

to alleviate up bending of the gate oxide ﬁlm. With a thicker TSOI

(90 nm), less compressive stress (

r

C) and thus less strain was

in-duced in SOI, resulting in larger tensile stress (

r

T) remaining in

gate oxide, thus leading to larger up bending of the gate oxide ﬁlm. Thus, for thicker TSOIpMOSFETs, there is a larger net tensile stress

induced in the bulk region of gate oxide near the FUSI gate, which tends to induce more bulk oxide traps (NBOT). Furthermore, there is

another compressive stress to press SOI film resulting from the sur-rounding oxide of shallow trench isolation (STI) for n- and pMOS-FETs[8]. This outer compressive stress on SOI surrounding will lead to the extent of down bending of gate oxide film for nMOSFETs larger than that of up bending of gate oxide film for pMOSFETs. Thus, the extent of NBOTgeneration with increasing TSOIof

pMOS-FETs is smaller than that of nMOSpMOS-FETs. We believe that the oxide traps (NBOTand/or Nit) are generated by high stress CESL, especially

for the thicker SOI devices, and that is the main reason to degrade device reliability. The optimal device performance and reliability can be achieved by appropriate design of CESL and SOI ﬁlm. 4. Conclusion

In this work, the Ni-FUSI gate strained SOI CMOSFETs with var-ious SOI thicknesses (50, 70 and 90 nm) and capped with different stress CESLs were investigated with respect to device performance (carrier mobility and subthreshold swing), gate leakage current and gate oxide TDDB reliability. The device performance and gate oxide reliability are affected by interface trap (Nit) and bulk oxide

trap (NBOT) in the gate oxide induced by the CESL and the Si layer

of SOI. For devices with high stress CESL, thinner TSOI(thickness

of SOI) devices have a smaller net remaining stress in gate oxide ﬁlm than the thicker TSOIdevices, and thus possess a larger Nit

and a smaller NBOT, leading to the total oxide trap (NT= Nit+ NBOT)

is relatively smaller than that of the thicker TSOIdevices, and thus

reveal a superior gate oxide reliability. On the other hand, the thicker TSOIdevices show a superior driving capability, but it

re-veals an inferior gate oxide reliability and a larger gate leakage cur-rent. Therefore, the NBOTinduced by the net stress is responsible for

the gate oxide reliability. Presumably, the gate oxide ﬁlm is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker TSOIdevices in this strain technology, and we

be-lieve this is the main reason for the devices reliability degradation, in particular the nMOSFETs. Therefore, an appropriate SOI thick-ness design is the key factor to achieve superior device perfor-mance and reliability.

Acknowledgments

This work was supported by the National Science Council (NSC) under contract NSC 97-2221-E035-090, and partially supported by NSC under contract NSC 99-2221-E035-099. The authors would like to thank Dr. Chien-Ting Lin and UMC staffs for their helpful process supporting, and the assistances of Mr. Kai-Sheng Wang and Mr. Yu-Ting Chen for the TDDB reliability and the low fre-quency noise measurement, respectively.

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