A Three-Stage One-Sided Rearrangeable Polygonal Switching Network

A Three-Stage One-Sided Rearrangeable

Polygonal Switching Network

Mao-Hsu Yen,

Sao-Jie Chen, Member, IEEE, and

Sanko H. Lan

AbstractÐThis paper proposes a three-stage rearrangeable polygonal switching network (PSN) for interconnecting one-sided input-output terminals. In comparing our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches, we prove that rearrangeability of a PSN is better than that of a Clos switching network. Also, the switches efficiency of PSN is explored.

Index TermsÐRearrangeable, switching network, polygonal switching network.

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INcommunication and computer networks, two-sided switching networks consisting of switching elements, such as crosspoints and interconnecting links, have been used to interconnect input and output terminals (ports) located on opposite sides. To interconnect input-output terminals located on the same side, another kind of switching network, called the one-sided switching network, is used instead. For example, Fig. 1 shows a three-stage one-sided Clos network [1], [2] C…n; m; s†, which consists of s CB…n; m† crossbars (at the first and third stages) interconnected by m triangular arrays (at the second stage). As we know, this C…n; m; s† Clos network with m  2n ÿ 1 is a nonblocking network. Through the arrangement of switches (or interconnects) in various combinations, different input-output terminals of a one-sided switching network can be connected to each other. Assuming that all connections are point-to-point, the enumeration of all pairs of input-output terminals to be connected is called an assignment, where an input (or output) terminal can appear in at most one pair of connections. An assignment is realizable if there exist in the network disjoint paths connecting all pairs of input-output terminals given in the assignment. A switching network is rearrangeable [2], [3], [4], [5], [6], [7] if any given assignment is realizable.

Studies on multistage switching networks are fruitful. Yen and Feng [4] proposed a class of 2 log2N-stage two-sided networks,

which are equivalent to Benes networks. All networks in this class are nonblocking and rearrangeable. The one-stage one-sided rearrangeable switching networks have been discussed by Mitchell and Wild [5]; then, the reduction of crosspoints in the one-stage one-sided crosspoint switching network has been investigated by Varma and Chalasani [6]. Gordon and Srikanthan [7] studied another multistage one-sided switching network with many 2  2 switch elements. Chang et al. [8], [9], [10] proposed universal switch blocks to improve the routability in a Field Programmable Gate Array (FPGA) routing network. However, most of these studies are concerned with either the two-sided rearrangeable switching networks or the one-stage one-sided rearrangeable

switching networks. In this paper, we propose a new three-stage one-sided rearrangeable network, called the Polygonal Switching Network (PSN) [11], [12] for the bidirectional communication system. We investigate how to use this PSN to construct a rearrangeable switching network and how to minimize the number of switches in PSN. We also compare our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches. We show that a C…n; m; s† Clos switching network with m  n is not rearrangeable.

The next section gives a description of the proposed PSN and some notation and definitions. Furthermore, we prove that the Clos switching network is not rearrangeable. Section 3 proves the rearrangeability of a PSN and Section 4 shows how to minimize the number of switches in a rearrangeable PSN. Conclusions are reported in Section 5.

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A three-stage one-sided polygonal switching network (PSN) consists of s crossbars (CBs) interconnected by an s-sided polygonal switch block (PSB) with s  3. Fig. 2 shows an example of PSN with n ˆ 2, m ˆ 2, and s ˆ 4, where the first and third stages are composed of four CBs and the second (internal) stage is a 4-sided PSB.

Each crossbar in a PSN, denoted as CBi…n; m† for i ˆ 1; 2; . . . ; s,

is an n  m block architecture having n external terminals Piˆ

fpi;1; pi;2; . . . ; pi;ng connected to the input-output ports and m

internal terminals Tiˆ fti;1; ti;2; . . . ; ti;mg connected to one side of

PSB. Since we have two sets of terminals P ˆ P1[ P2[


[ Psand

T ˆ T1[ T2[


[ Ts, a polygonal switching network can then

provide N ˆ s  n external terminals for interconnection. Through these n  m programmable and electrically noninteracting switches in a crossbar CBi…n; m†, any external terminal in Pi can

be connected to a free internal terminal in Tiwithout any blocking.

For example, if switch SW…pi;j; ti;h† is programmed to be ªON,º

then connection …pi;j; ti;h† between an external terminal pi;jand an

internal terminal ti;his established.

The polygonal switch block in a PSN, denoted as PSB…m; s†, is an s-sided switch block with m (internal) terminals on each side of the block, as shown in Fig. 3a and

IEEE TRANSACTIONS ON COMPUTERS, VOL. 50, NO. 11, NOVEMBER 2001 1291

. M.-H. Yen is with the China Institute of Technology, Taipei, Taiwan, ROC. E-mail: [email protected].

. S.-J. Chen is with National Taiwan University, Taipei, Taiwan, ROC. E-mail: [email protected].

. S.H. Lan is with National Taiwan University of Science and Technology, Taipei, Taiwan, ROC. E-mail: [email protected].

Manuscript received 4 May 2000; revised 19 Apr. 2001; accepted 22 May 2001.

For information on obtaining reprints of this article, please send e-mail to: [email protected], and reference IEEECS Log Number 112051.

Fig. 1. A three-stage one-sided Clos switching network C…n; m; s† with n ˆ 2, m ˆ 2, and s ˆ 4.

0018-9340/01/$10.00 ß 2001 IEEE

Fig. 3d. Label the terminals on the ith side of a PSB…m; s† as Tiˆ fti;1; ti;2; . . . ; ti;mg for 1  i  s. Since a terminal in one

side of the PSB should be connected to a terminal in any of the other …s ÿ 1† sides through switches, a PSB…m; s† needs ms…s ÿ 1†=2 switches. If a switch SW…ti;j; tk;l†; i 6ˆ k is

pro-grammed to be ªON,º then a connection between terminals ti;jand

tk;lis established, as shown in Fig. 3a and Fig. 3d. To form a PSN,

we need s CB…n; m† crossbars connected to a PSB…m; s†. Thus, a PSN…n; m; s† can be completely characterized by three parameters: n, m, and s.

In the following, we study two types of PSB, as shown in Fig. 3a and Fig. 3d. The PSB in Fig. 3a is equivalent to the two isolated triangular arrays in Fig. 3b, which is exactly the second stage of a

Clos switching network in Fig. 1. And, this PSBC…m; s† is

composed of m isolated PSBC…1; s†, as shown in Fig. 3c. Fig. 4a

shows a polygonal switching network PSNC…n; m; s† constructed

with a PSBC…m; s†, which can be used to implement a Clos

switching network C…n; m; s†. Fig. 3d shows a universal polygonal

switch block PSBU…m; s† proposed by Chang et al. [8], [9], [10]. A

PSNU…n; m; s†, consisting of s CB…n; m† crossbars connected to a

PSBU…m; s†, is shown in Fig. 4b. Note both PSNU…n; m; s† and

PSNC…n; m; s† have the same size and the same number of

switches.

In a PSN…n; m; s†, any connection pair …pi;j; pk;l† is a

point-to-point connection, where pi;j; pk;l2 P. An assignment AS ˆ

f…pi;j; pk;l†g represents a set of connection pairs to be connected,

where a terminal can appear in at most one pair. A PSN…n; m; s† is rearrangeable if any assignment AS is realizable (routable). To examine whether a connection pair …pi;j; pk;l† 2 AS can be

con-nected through PSB…m; s†, let us classify AS into two disjoint sets, AS ˆ ASD[ ASS, such that

ASDˆ f…pi;j; pk;l† : …pi;j; pk;l† 2 AS and i 6ˆ kg

and

ASSˆ f…pi;j; pk;l† : …pi;j; pk;l† 2 AS and i ˆ kg;

where pi;j; pk;l2 P, 1  i; k  s, and 1  j; l  m.

Note that a connection pair …pi;j; pk;l† belonging to ASDis to be

connected by passing through blocks CBiÿ PSB ÿ CBk, while the

1292 IEEE TRANSACTIONS ON COMPUTERS, VOL. 50, NO. 11, NOVEMBER 2001

Fig. 2. A polygonal switching network PSN…n; m; s† with n ˆ 2, m ˆ 2, and s ˆ 4.

Fig. 3. Two types of polygonal switch blocks PSB…m; s† with m ˆ 2 and s ˆ 4. (a) A PSBC…m; s† and (b) its corresponding triangular arrays. (c) A PSBC…m; s† is

equivalent to the m isolated PSBC…1; s†. (d) A PSBU…m; s†.

Fig. 4. Two types of polygonal switching networks PSN…n; m; s† with n ˆ 2, m ˆ 2, and s ˆ 4. (a) A PSNC…n; m; s† implementation of the Clos switching network

C…n; m; s† in Fig. 1. (b) A PSNU…n; m; s†.

pair belonging to ASS has to be connected through a CB only. In

ASD, each connection is accomplished using two sides of a

PSB…m; s†; we can thus classify those connections passing through a PSB…m; s† into s…s ÿ 1†=2 types of connections. Fig. 5 shows the six possible types of connections in a four-sided switch block. A routing requirement vector …RRV † ~r[8], [9], [10] for a PSB…m; s† is an s…s ÿ 1†=2-tuple (r1;2; r1;3; . . . ; r1;s; r2;3; . . . ; r2;s; . . . ; rsÿ1;s), where ri;k

represents the number of the connection pairs …pi;j; pk;l† required to

be connected through PSB…m; s† and 0  ri;k m for

1  i < k  s. An RRV ~r is said to be realizable (routable) on a PSB…m; s† if there exist disjoint paths for ~r on a PSB…m; s†. For example, Fig. 6a shows a routing instance with three nets corresponding to the RRV ~rˆ …1; 0; 1; 0; 1; 0† and we try to route this RRV using two different polygonal switch blocks PSBU…2; 4†

and PSBC…2; 4†. Instances of an RRV (1, 0, 1, 0, 1, 0) routable on a

PSBU…2; 4† are shown in Fig. 6b and Fig. 6c, where the routing

solutions are illustrated by thick lines. As shown in Fig. 6d and Fig. 6e, however, there is always one net that cannot be routed on a PSBC…2; 4†. Thus, this RRV (1, 0, 1, 0, 1, 0) is not routable on a

PSBC…2; 4†.

Now, let AS ˆ f…p1;1; p4;1†; …p1;2; p2;1†; …p2;2; p4;2†; …p3;1; p3;2†g be

routed on a PSNC…2; 2; 4† and a PSNU…2; 2; 4†, as, respectively,

shown in Fig. 4a and Fig. 4b. Decomposing AS ˆ ASD[ ASS, we

have

ASDˆ f…p1;1; p4;1†; …p1;2; p2;1†; …p2;2; p4;2†g

and

ASSˆ f…p3;1; p3;2†g:

The RRV for routing ASDon a PSB…2; 4† is ~rˆ …1; 0; 1; 0; 1; 0†. We

show, in Fig. 4b, a possible routing solution for the given AS on a PSNU…2; 2; 4† switching network. For instance, Fig. 4a shows that

the same AS is not routable on a PSNC…2; 2; 4† switching network

because RRV ~rˆ …1; 0; 1; 0; 1; 0† contains at least one connection that cannot be routed on a PSBC…2; 4†, as already shown in Fig. 6d

and Fig. 6e. In the following, we prove that a PSNC…n; m; s† with

m  n is not rearrangeable.

Theorem 1. A PSNC…n; m; s† polygonal switching network is not

rearrangeable for m  n and s  3.

Proof. Observably, if a PSNC…n; m; s† with m ˆ n is not

rearrange-able, then a PSNC…n; m; s† with m < n is not rearrangeable.

Thus, we need to prove that a PSNC…n; n; s† is not rearrangeable.

Arbitrarily select three sides i, k, and u of a PSNC…n; n; s†,

1  i < k < u  s, we form an assignment

AS ˆ ASD

ˆ f…pi;1; pu;1†; …pi;2; pu;2†; . . . ; …pi;nÿ1; pu;nÿ1†; …pi;n; pk;n†; …pk;1; pu;n†g

to be connected between the Pi, Pk, and Puon a PSNC…n; n; s†.

The RRV for routing ASDon a PSBC…n; s† is ~rˆ …0; . . . ; 0; ri;kˆ

1; 0; . . . ; 0; ri;uˆ n ÿ 1; 0; . . . ; 0; rk;uˆ 1; 0; . . . ; 0† as shown in

Fig. 7a. Since a PSBC…n; s† is equivalent to n isolated

PSBC…1; s†s, the first ri;uˆ …n ÿ 1† can be realizable on …n ÿ 1†

isolated PSBC…1; s†s, as shown in Fig. 7b. But, we cannot find

enough disjoint paths to simultaneously realize an ri;kˆ 1 and

an rk;uˆ 1 on the last PSBC…1; s†, as shown in Fig. 7c. Thus, this

AS cannot be realizable on a PSNC…n; n; s† because this RRV ~r

contains at least one connection that cannot be routed on a PSBC…n; s†. Therefore, the PSNC…n; n; s† is not rearrangeable.tu

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PSN

A polygonal switch block PSB…m; s† is said to be universal [8], [9], [10] if any RRV ~rˆ …r1;2; r1;3; . . . ; rsÿ1;s† satisfying the dimensional

constraint is realizable on this PSB…m; s†. The dimensional constraint for a PSB…m; s† is that the number of connections interconnecting through each side of PSB…m; s† cannot exceed m

IEEE TRANSACTIONS ON COMPUTERS, VOL. 50, NO. 11, NOVEMBER 2001 1293

Fig. 5. Six possible types of connections in a four-sided switch block.

Fig. 6. Examples of routing on two four-sided switch blocks, each of the same size. (a) An RRV instance (1, 0, 1, 0, 1, 0). (b) and (c) This RRV is routable on a PSBU…2; 4†. (d) and (e) This RRV is not routable on a PSBC…2; 4†.

Fig. 7. An instance of RRV not routable on a PSBC…n; s†. (a) An RRV instance

~rˆ …0; . . . ; 0; ri;kˆ 1; 0; . . . ; 0; ri;uˆ n ÿ 1; 0; . . . ; 0; rk;uˆ 1; 0; . . . ; 0†. (b) This ri;uˆ

n ÿ 1 is routable on …n ÿ 1† isolated PSBC…1; s†. (c) This ri;kˆ 1 and rk;uˆ 1 are

not simultaneously routable on a PSBC…1; s†.

[8], [9], [10]. A generic universal switch block has been proposed by Shyu et al. [10]. Furthermore, they presented an algorithm to construct an s-sided universal switch block with m terminals on each side. We use this algorithm to construct a universal PSBU…m; s† for our PSNU…n; m; s†. Based on the universality of

PSBU…m; s† and the properties of a crossbar CB…n; m†, we proceed

to prove the rearrangeability of a PSNU…n; m; s†.

Theorem 2. A PSNU…n; m; s† polygonal switching network is

rearrangeable if and only if m  n.

Proof. Observably, if a PSNU…n; m; s† with m ˆ n is rearrangeable,

then a PSNU…n; m; s† with m  n is rearrangeable. Thus, we

need to prove that a PSNU…n; n; s† is rearrangeable.

(If) A PSNU…n; n; s† is rearrangeable if any assignment AS ˆ

ASD[ ASS is realizable. First, we prove that ASD is realizable

on a PSNU…n; n; s†. Since each connection pair …pi;j; pk;l† 2 ASD,

i 6ˆ k, i s c o n n e c t e d b y p a s s i n g t h r o u g h b l o c k s CBiÿ PSB ÿ CBk. Furthermore, we observe that the RRV ~r

for ASDsatisfying the dimension constraint is also realizable on

a universal PSBU…n; s† since the number of connection pairs

interconnecting through each side of PSBU…n; s† does not

exceed n. Therefore, for each …pi;j; pk;l† 2 ASD, we can find a

connection path …ti;q; tk;nÿq‡1† in a PSBU…n; s† because its RRV ~r

is realizable on a PSBU…n; s†, where 1  q  n. The last thing to

do is to program the two switches SW…pi;j; ti;q† and

SW…pk;l; tk;nÿq‡1† in the CBi…n; n† and CBk…n; n†, respectively.

Then, we have all the connection pairs …pi;j; pk;l† 2 ASD

connected by PSNU…n; n; s†. That is, ASD is realizable on a

PSNU…n; n; s†.

Next, we consider the ASS connections on a PSNU…n; n; s†

after the ASD ones have been realized on a PSNU…n; n; s†. For

each connection pair …pi;j; pi;l† 2 ASS, we can find a terminal

ti;h2 Ti(truly, at least two terminals) in the CBi…n; n† which is

not in use by ASD. And, this connection pair …pi;j; pi;l† can be

connected by programming two switches SW…pi;j; ti;h† and

SW…pi;l; ti;h† in the CBi…n; n†. Therefore, ASS is realizable

through s CB…n; n†s of a PSNU…n; n; s†.

Hence, any assignment AS ˆ ASD[ ASS is realizable on a

PSNU…n; n; s†. That is, a PSNU…n; m; s† polygonal switching

networks with m  n is rearrangeable.

(Only If) If, in a PSNU…n; m; s† with m < n, we have an

assignment AS ˆ ASDˆ f…pi;1; pk;1†; …pi;2; pk;2†; . . . ; …pi;n; pk;n†g to

be connected between the Piand Pkon a PSNU…n; m; s†, i 6ˆ k.

Since each connection pair …pi;j; pk;l† 2 AS is connected by

passing through blocks CBiÿ PSB ÿ CBk. In each CBi…n; m†,

we cannot find enough disjoint paths to connect all the n external terminals in Pi to all the m internal terminals in Ti,

which in turn are connected to the ith side of a PSBU…m; s† due

to m < n. Thus, this AS is not realizable on a PSNU…n; m; s†

with m < n. tu

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We have shown the rearrangeability of our PSNU…n; n; s† in

Section 3. Now, we start to explore the effect of the parameters s and n in a PSNU…n; n; s† on the switch-efficiency and we try to find

proper s and n values to minimize the number of switches needed in a rearrangeable PSNU…n; n; s† to interconnect N ˆ s  n

input-output terminals.

Since the number of switches in s CB…n; n† crossbars is equal to

s  n2_{, the number of switches in a PSB}

U…n; s† is equal to

ns…s ÿ 1†=2. Denote the number of switches in a PSNU…n; n; s† as

SW…n; n; s†. By summing the number of switches in all the above blocks, we have:

SW…n; n; s† ˆ sn2_‡ns…s ÿ 1†

2 : …1†

Substituting n ˆ N=s into (1) results in

SW…n; n; s† ˆN_s2‡Ns₂ ÿN₂: …2†

This indicates that the function SW…n; n; s† has minimum value at s ˆp2N,

SW…n; n;p2N† ˆp2N3=2_ÿN

2: …3†

From (3), we have that a PSNU…n; n; s† with s ˆp2Ncontains

the number of switches to a minimum. Furthermore, the SW…n; n; s† is proportional to N3=2_.

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This paper proposed a three-stage one-sided rearrangeable polygonal switching network PSNU…n; m; s†, which consists of

s CB…n; m† crossbars interconnected by a universal polygonal switch block PSBU…m; s† with s sides. We not only provide the

designers with a rearrangeable PSNU…n; m; s†, where m  n for

interconnecting N ˆ s  n input-output ports, but also show what value of s can be used to minimize the number of switches needed in a network. Besides, this polygonal switching network has been successfully applied to the design of a Field Programmable Interconnection Chip (FPIC) for interconnecting FPGAs in a symmetric multi-FPGA system [11], [12], [13].

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The authors are grateful to Dr. Y.-W. Chang, G.-M. Wu, and other members of the NCTU VLSI Systems Labs for their invaluable suggestions.

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[3] P.K. Chan and M. Schlag, ªArchitecture Tradeoffs in Field Programmable Device-Based Computing Systems,º Proc. IEEE Workshop FPGAs for Custom Computing Machines, pp. 152-161, 1993.

[4] Y.M. Yen and T.Y. Feng, ªOn a Class of Rearrangeable Networks,º IEEE Trans. Computers, vol. 41, no. 11, pp. 1361-1379, Nov. 1992.

[5] C. Mitchell and P. Wild, ªOne-Stage One-Sided Rearrangeable Switching Networks,º IEEE Trans. Comm., vol. 37, no. 1, pp. 52-56, Jan. 1989. [6] A. Varma and S. Chalasani, ªReduction of Crosspoints in One-Sided

Crosspoint Switching Networks,º Proc. Eighth Ann. Joint Conf. IEEE Computer and Comm. Soc. Technology: Emerging or Converging (INFOCOM '89), vol. 3, pp. 943-952, 1989.

[7] J. Gordon and S. Srikanthan, ªSingle Sided Switching Network,º Electronics Letters, vol. 26, no. 4, pp. 248-250, Feb. 1990.

[8] Y.W. Chang, D.F. Wong, and C.K. Wong, ªUniversal Switch Modules for FPGA Design,º ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 1, pp. 80-101, Jan. 1996.

[9] G.M. Wu, M. Shyu, and Y.W. Chang, ªUniversal Switch Blocks for Three-Dimensional FPGA Design,º Proc. 1999 ACM Int'l Symp. Field Programmable Gate Arrays (FPGA-99), Feb. 1999.

[10] M. Shyu, Y.D. Chang, G.M. Wu, and Y.W. Chang, ªGeneric Universal Switch Blocks,º IEEE Trans. Computers, vol. 49, no. 4, pp. 348-359, Apr. 2000. [11] M.H. Yen, M.C. Shie, and S.H. Lan, ªPolygonal Routing Network for FPGA/FPIC,º Proc. 1999 Int'l Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 104-107, 1999.

[12] M.H. Yen, S.J. Chen, and S.H. Lan, ªSymmetric and Programmable Multi-Chip Module for Rapid Prototyping System,º Proc. 1999 IEEE Workshop Signal Processing Systems (SiPS 99) Design and Implementation, pp. 301-310, 1999.

[13] M.H. Yen, S.J. Chen, and S.H. Lan, ªSymmetric and Programmable Multi-Chip Module for Low-Power Prototyping System,º VLSI Design, An Int'l J. Custom-Chip Design, Simulation, and Testing, (to appear).

1294 IEEE TRANSACTIONS ON COMPUTERS, VOL. 50, NO. 11, NOVEMBER 2001