Design, Fabrication, and Reliability of Low-Cost
Flip-Chip-On-Board Package for Commercial
Applications up to 50 GHz
Li-Han Hsu, Chee-Way Oh, Wei-Cheng Wu, Edward Yi Chang, Senior Member, IEEE,
Herbert Zirath, Senior Member, IEEE, Chin-Te Wang, Szu-Ping Tsai, Wee-Chin Lim, and Yueh-Chin Lin
Abstract— This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technol-ogy skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (εr = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss S11greater than 18 dB and insertion loss S21less than 0.5 dB. Meanwhile, the flip-chip bond-ing of the in-house-fabricated In0.52Al0.48As/In0.6Ga0.4As meta-morphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implement-ing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors’ knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.
Index Terms— Coplanar waveguide, fabrication, flip-chip-on-board, interconnect, metamorphic high-electron-mobility transis-tor device, microwave, packaging, reliability, RO3210 laminate, underfill.
I. INTRODUCTION
A
S CONSUMER products and portable devices move tohigher frequencies of operation, low-cost, light-weight, Manuscript received July 1, 2010; revised August 15, 2011; accepted September 15, 2011. Date of publication January 31, 2012; date of current version February 28, 2012. Recommended for publication by Associate Editor M. Cases upon evaluation of reviewers’comments.
L.-H. Hsu, C.-W. Oh, W.-C. Wu, E. Y. Chang, C.-T. Wang, S.-P. Tsai, W.-C. Lim, and Y.-C. Lin are with the Department of Material Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jones2.mse94g@nctu.edu.tw; ohcheeway@yahoo.com; williamwu. mse90g@nctu.edu.tw; edc@mail.nctu.edu.tw; rinexoper.mse95g@nctu. edu.tw; mai.mse96g@nctu.edu.tw; nmlwchin@yahoo.com; nctulin@yahoo. com.tw).
H. Zirath is with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg 41296, Sweden (e-mail: her-bert.zirath@chalmers.se).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2011.2171485
and compact packages with good performance are required. Generally, conventional microwave packaging involves three levels of packages: chip to module, module to printed cir-cuit board (PCB), and PCB to motherboard. The transitions between these packaging levels result in significant reflec-tion losses and pull down the radio frequency (RF) perfor-mance of the packaged devices. When the operating frequency moves higher, the situation becomes even worse. Besides, conventional bond wire has a significant parasitic inductance and thus induces some unwanted effects at microwave fre-quencies, which could compromise the device performance after assembly [1]. Hence, low-cost packaging solutions with excellent RF performance are highly sought. In this respect, flip-chip interconnect has gained much attention as a chip-level interconnect because of several advantages, such as shorter interconnect length, higher throughput, and smaller package size [2]–[6]. The integration of chip-on-board (COB) [7] with flip-chip technology by directly mounting chips onto the PCB and bypassing one level of ceramic package can not only save the manufacturing cost but also enhance the packaging performance. This is the so-called flip-COB (FCOB) packaging, which is a technique derived from low-frequency applications [8]. Fig. 1(a) shows the illustration of the conventional microwave package structure and Fig. 1(b) the schematic diagrams of the conventional RF package (two levels) and the proposed FCOB package (one level). As can be seen, the module-level (ceramic) package is eliminated by using the proposed FCOB structure, which can reduce the package cost and enhance the package performance.
In the literature, some investigations on flip-chip aseembly on PCB at the gigahertz frequency range have been reported [9]–[11]. The performance of the flip-chip assembly using coplanar strip transmission line on an RT/Duroid 6010 sub-strate has been reported, demonstrating a high return loss of up to 50 GHz [9]. Case reported a hybrid microwave integrated circuit amplifier with the flip-chip-attached discrete SiGe heterojuction bipolar transistor microstrip transmission lines and other distributed elements integrated on a Duroid circuit board [10]. The amplifier was designed to operate at the Ku band (12–18 GHz), and the gain (S21) was around 7 dB. Xiao et al. reported a flip-chip-assembled 2.4-GHz Si CMOS voltage-controlled oscillator (VCO) with integrated Cu inductors on organic substrates. The flip-chip-assembled VCO showed a phase noise of 108 dBc at 600 kHz offset for a 2156–3950/$31.00 © 2012 IEEE
Chip
Wafer bond wire
Module Al2O3, AlN, LTCC ……. BGA GaAs, Si ….. Chip to Module Module to PCB Underfill PCB Conventional RF Package Motherboard
Printed Circuit Board
GaAs, Si….. bump Chip to
PCB Underfill
Proposed FCOB PackageFCOB
(b) (a)
Printed Circuit Board
Fig. 1. (a) Illustration of conventional microwave package structure. (b) Schematic diagrams of the conventional RF package (2-levels) and proposed FCOB package (1-level).
80 90 100 W = 50 μm W = 100 μm 50 60 70 W = 150 μm Substrate W G G 20 30 40 0 2 4 6 8 10 12 14 10 20 C PW Gap, G (in μ m)
Substrate Dielectric Constant
W = 70 μm (Used in this paper)
Fig. 2. Signal-to-ground gap (G) of 50 CPW lines with different signal widths (W) versus substrate dielectric constant at 50 GHz.
2.4-GHz carrier [11]. These papers mainly focused on the performance demonstration of the flip-chip die attachments on PCBs. Investigations on the design, fabrication, and reliability remain insufficient.
This paper is organized as follows. In Section II, the design and fabrication concern of a CPW transmission line on PCB is discussed. In Section III, the in-house process flow of the flip-chip assembly on an RO3210 is presented. Sections IV and V present the measurement results of the flip-chip-bonded passive structure and active metamorphic high-electron-mobility transistor (mHEMT) device, respectively. The reliability test result of the FCOB structure with underfill is presented and discussed in Section VI. Finally, this paper concludes in Section VII.
II. CPW TRANSMISSIONLINE ONPCB
On a packaging carrier, using CPW transmission line is considered to be more compatible with flip-chip technology [2]–[4]. Since the ground is at the same level as the signal line, the via hole to the backside is not necessary and thus the inductance associated with accessing ground is signifi-cantly reduced [12]. The absence of the via hole makes the CPW perform well at high frequencies at low manufacturing cost. However, for microwave/millimeter wave applications,
TABLE I
COMPARISON OF THEPROPERTIES ANDPRICE OFRO3210 VERSUSSOME
OTHERCOMMONLY-USEDMICROWAVESUBSTRATES. (THECOSTWAS
OBTAINED FROM THELOCALSUBSTRATESUPPLIERS)
Substrate X-Y CTE(ppm/K) Dielectricconstant factorLoss Cost in USD(2× 2)
GaAs 5.7 12.9 0.0020 88.9
Al2O3 6.3 9.8 0.0002 23
AlN 5.27 6.3 0.0120 42
FR-4 15 4.2–4.3 0.0015 2.02
RO3210 13 10.2 0.0027 2.56
the characteristic impedance-related physical parameters of a CPW line, i.e., signal conductor width (W) and signal-to-ground gap (G), are typically less than 100 μm, which cannot be applied in the conventional PCB process. In the conventional PCB process, the copper cladding on the surface (usually 17 or 35 μm) is wet-etched back for patterning transmission lines and passive components on the board. The wet-etching process produces an undesirable undercut profile and the structure dimensions are difficult to control [13]. Therefore, in this paper, photolithography and electroplating with low-cost film masks are proposed in order to give more precise line resolution on the PCBs.
Fig. 2 shows the G value of 50- CPW lines with different signal widths (W) versus the substrate dielectric constant at 50 GHz. The substrate thickness is 650μm. In the design rule of CPW transmission line, a low substrate dielectric constant reduces the dimension, which is difficult to fabricate. For
example, for a CPW line with W = 70 μm on a Rogers
RO4003 substrate (εr = 3.38), G is only 8 μm. However, the
substrate dielectric constant of the PCBs can be tailored using polymer/ceramic composites [14]. The substrate used in this paper is a Rogers series polytetrafluoroethene based RO3210 ceramic-filled laminate reinforced with woven fiberglass and designed for high-frequency applications. Table I shows the comparison of RO3210 versus some other commonly used microwave substrates. As can be seen, RO3210 has a high dielectric constant (εr) of 10.2 and a low loss tangent (tan δ)
of 0.0027. The high dielectric constant enlarges the dimensions of the CPW line and thus facilitates the fabrication.
III. PACKAGEFABRICATION
Fig. 3 shows the process flow of the RO3210 board for the flip-chip assemblies. The RO3210 laminate board has an electrodeposited copper cladding on both sides of the sheet. The sheet thickness is about 650 μm and the copper cladding thickness is about 17 μm on each side. In this paper, the photolithography and electroplating processes were implemented in order to give good line resolution on the RO3210 laminate. The commercially available low-cost film mask with patterned silver bromide (AgBr) on plastic film was employed in the photolithography process. The resolution limit of the film mask is around 25 μm. First, a solution of water, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2) was used to etch away the copper cladding. Then, titanium (Ti) and gold (Au) metal were deposited in situ using an
(i) (ii) (iii) (vii) (v) (vi) Seed layer Thin PR Gold CPW Thick PR Copper cladding (iv) (viii) Al2O3 carrier CPW width: 570 μm Gold bump (BH: 50 μm)
Fig. 3. Process flow of the RO3210 board for flip-chip assembly.
E-gun evaporator onto the RO3210 board with the thickness of 1000 and 2000 Å to form a continuous seed layer for the following Au electroplating. Ti was used as an adhesion layer. A thin photoresist (PR) layer was then patterned on the board for electroplating the CPW circuits. After the electroplating of the Au circuits, the thin PR film was removed. The board was then covered by a thick PR layer patterned to define the positions of the Au bumps, which were formed by electroplating. By controlling the electroplating current density and time, the required bump height was achieved. The Au bump height and diameter in this paper were both around
50 μm. The seed layers were then removed with a KI/I2
solution for the removal of Au metal, and a dilute hydrogen fluoride solution for the removal of Ti metal. Fig. 4 shows the scanning electron microscopy (SEM) image of the fabricated CPW line with Au bumps on the RO3210 board.
Finally, the Au-to-Au thermocompression bonding was car-ried out to flip-chip-bond the passive CPW transmission line and active mHEMT device onto the RO3210 board using a precision flip-chip die bonder. After the optimization of the bonding parameters, the temperature of this paper holder was set to 250 °C and the bonding force was adjusted to 20 grams per bump which was maintained for a bonding time of 3 min. Fig. 5 shows the SEM image of the fabricated flip-chip interconnect structure on an RO3210 board. By using the FCOB packaging process, since the chip is directly flip-chip-mounted onto PCB, the ceramic package can be skipped, which results in lower cost and better RF performance.
(a)
CSD Lab 25.0 kV 350 × 100 μm
CSD Lab 25.0 kV 800 × 50 μm
50 μm
(b)
Fig. 4. SEM images of the fabricated Au bumps on RO3210 laminate. (a) Au bumps and CPW circuits on RO3210 board. (b) Zoom-in view of an Au bump.
On comparing with the conventional flip-chip carrier on a ceramic-based substrate, the bumping process on RO3210 is almost the same except that the copper cladding needs to be removed in the beginning. Moreover, regarding the flip-chip assembly, the bonding temperature for RO3210 is lower than that of ceramic substrate since the glass transition temperature
(Tg) of the organic laminate is around 300 °C. These issues
should be carefully considered during carrier fabrication and the assembly process.
IV. PASSIVESTRUCTURES
The scattering parameters (S parameters) of the fabricated interconnect structures were characterized to 50 GHz using an on-wafer probing measurement system with a vector network analyzer. The design and optimization of the interconnect structures were carried out by using the simulation tool high-frequency simulation software (HFSS) for the 3-D electromag-netic field analysis. In order to investigate the RF performance on the RO3210 board, a CPW thru line with characteristic
impedance of Z0 = 50 was fabricated on the RO3210
board. At the same time, an Al2O3 substrate was used for comparison with the same CPW thru-line design (Z0= 50 ). The CPW length for both cases was 3000μm. Finite-ground coplanar waveguide (FGCPW) was employed on the substrates
RO3210 GaAs Chip CSDLAB 25.0 kV 40 x 100 × 200 μm 1 mm GaAs Chip RO3210 (a) (b)
Fig. 5. SEM images of the GaAs chip with flip-chip interconnect structure on RO3210TM board. (a) Top-view. (b) Side-view.
to suppress the parallel-plate and higher-order modes [15]. Fig. 6 shows the measured and simulated results. As can be seen, a return loss of greater than 20 dB was achieved for both substrates because of the good matching of the 50- impedance. On the other hand, the insertion losses on both substrates suffered the same degree of degradation, i.e., less than 0.4 dB from dc to 40 GHz. After 40 GHz, RO3210 showed poorer performance than Al2O3 with an additional loss of 0.3 dB at 50 GHz. The poorer performance of the former can be explained by its material properties: higher loss tangent (0.0027) compared to Al2O3(0.0002). In addition, the surface roughness of RO3210 is greater than that of Al2O3(see Fig. 7), which results in a greater insertion loss, especially at higher frequencies. Fig. 7 shows the comparison of the surface roughness of the CPW transmission lines on the Al2O3 substrate and the RO3210 laminate.
The GaAs chip patterned with 50- CPW transmission lines was flip-chip-bonded onto the RO3210 board. The total length of the back-to-back interconnect structure was 3000 μm, including 1000 μm on the chip and 2000 μm on the board.
Alumina RO3210 0 0.0 Alumina (Simulation) RO3210 (Simulation) CPWon Sub −20 −10 −1.0 −0.5 −30 S11 (dB) S21 (dB) −1.5 0 10 20 30 40 50 −40 −2.0 Frequency (GHz)
Fig. 6. Measured and simulated S-parameters of the CPW thru line on RO3210 and Al2O3.
Fig. 8 shows both the measured and simulated S-parameters results. As can be seen, the measured return loss was greater than 15 dB from dc to 50 GHz, and the measured insertion loss was about 1.2 dB at 50 GHz. The poor performance is caused by the bump transitions at the flip-chip structures. For a flip-chip interconnect with typical dimensions, the equivalent circuit model shows an overall capacitive property [16], which could degenerate the transition performance. It is suggested that the bump pad be kept as small as possible to reduce the capacitance at the transitions [2], [3], however, it increases the difficulty in the fabrication. The most effective way to improve the interconnect performance is by adopting a high-impedance compensation line in front of the vertical bump transition. The high-impedance line provides an inductive counterpart to compensate for the excessive capacitance at the transition [3], [4]. In this paper, the dimensions of the high-impedance line were 100μm in length and 30 μm in width (see Fig. 8). As can be seen, the return loss significantly improved after the compensation. From dc to 20 GHz, S11 is better than 18 dB, from 20 to 50 GHz, S11 is better than 20 dB. The insertion loss is within 0.5 dB from dc to 50 GHz, showing excellent broadband performance for commercial RF applications.
V. ACTIVEDISCRETE MHEMT DEVICE
The in-house-fabricated In0.52Al0.48As/In0.6Ga0.4As mHEMTs were flip-chip-assembled onto a RO3210 laminate with the same compensation design adopted in Section IV. Fig. 9 shows the device structure and the photographs of the mHEMT chip before and after the flip-chip assembly. The gate length of the device was 0.15μm and the total gate width was 4×40 μm. Fig. 10 shows the measured transconductance
(Gm) of the mHEMT device. The transconductance of the
mHEMT after flip-chip bonding remained at the same level and shifted to more positive gate bias compared to the bare die. After the flip-chip bonding process, a compressive stress in the assembly was induced due to the coefficient of thermal
Al2O3 RO3210 (a) (b) CSD Lab 25.0 kV 350 × 100 μm CSD Lab 25.0 kV 300 × 100 μm
Fig. 7. SEM images of the surface morphologies of the CPW transmission lines on (a) Al2O3and (b) RO3210 laminate.
expansion (CTE) mismatch between GaAs (5.7 ppm/°C) and RO3210 (13 ppm/°C). This excessive compressive stress could lead to performance deviation [17], which should be carefully avoided during the assembly.
Figs. 11 and 12 show the measured S-parameters results of the flipped mHEMT on Al2O3and RO3210, respectively. The
S parameters were measured under the same bias condition of
gate voltage VG = −0.15 V and drain voltage VD = 0.6 V.
As can be seen, the extra loss in gain is smaller on Al2O3
(< 1.5 dB at 40 GHz) compared to RO3210 (< 2.0 dB
at 40 GHz). The losses were due not only to the flip-chip transitions, but also to the long CPW transmission line on the substrates (Al2O3 and RO3210). (The total length of the transmission line on the substrate was 2000 μm.) Since RO3210 has higher loss tangent (0.0027) than Al2O3(0.0002), the gain degradation of RO3210 is slightly higher.
VI. UNDERFILLINJECTION ANDRELIABILITYTEST
Reliability investigation is always essential for commer-cial applications. For the FCOB structure, there is a large CTE mismatch between GaAs (5.7 ppm/°C) and RO3210
0 10 20 30 40 50 Frequency (GHz) 100 μm Chip Hi-Compensation Without compensation With compensation 30 μm Bump Substrate Without compensation (Simulation) With compensation (Simulation) 0 −20 −10 −30 S11 (dB) −40 0 −2 −1 −3 S21 (dB) −4
Fig. 8. Measured and simulated S-parameters of the flip-chip interconnect structure on RO3210 board with and without compensation.
Au/Ge/Ni/Au Au/Ge/Ni/Au Ti/Pt/Au n-In0.52Ga0.48As i-In0.3Al0.7As 15 nm S S Gate RO3210 i-InAlAs Siσ-doping i-In0.52Al0.48As i-In0.6Ga0.4As i-In0.52Al0.48As 16 nm 3 nm 3 nm G D (c) Chip CPW SI GaAs InAlAs buffer (a) (b)
Fig. 9. (a) mHEMT device epitaxial layer structure (cross-sectional view). (b) Photograph of the chip before flip-chip assembly (top-view). (c) Photo-graph of the chip after flip-chip assembly (top-view).
600
Bare die
Flip chip on RO3210
600 400 500 400 500 100 200 300 100 200 300 Gm (mS/mm) −2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 0 Drain C u rrent, ID (mA/mm) Gate Voltage, VG (V) 0
Fig. 10. Measured transconductance (Gm) of the bare and flip-chip packaged mHEMT on RO3210 laminate VD = 0.6 V).
(13 ppm/°C), which is detrimental to the package reliability. The interconnects could fail because of the thermal stress induced during temperature cycling. Besides, the adhesion of
Bare die
Flip chip on Al2O3
15 5 10 S21 −5 0 S -P rameters in a dB 0 10 20 30 40 Frequency in GHz S11
Fig. 11. Measured S-parameter results of the bare and flip-chip packaged mHEMT on Al2O3substrate (VG= −0.15 V, VD = 0.6 V).
Bare die
Flip chip on RO3210 Flip chip on RO3210 with UF
10 15 S21 5 0 S11 0 10 20 30 40 Frequency in GHz S -P rameters in a dB
Fig. 12. Measured S-parameter results of the bare, flip-chip packaged mHEMT, and flip-chip packaged mHEMT with underfill on RO3210 laminate (VG = −0.15 V, VD = 0.6 V).
the flip-chip is weak since it relies only on several bump connections, which is sensitive and fragile to mechanical vibrations. Thus, to enhance the mechanical reliability, using an underfill in the flip-chip interconnect is necessary [18]. In this paper, an epoxy-based underfill with dielectric constant εr = 3.5 and loss tangent tan δ = 0.02 at 10 MHz was
injected into the flip-chip assemblies by the capillary underfill process and then cured at 150 °C for 2 h. The reliability of the flip-chip assemblies on RO3210 board with and without underfill was tested using the thermal cycling test. Fig. 13 shows the temperature profile of the thermal cycling test used
15 mins 125 −55 Temperat u re (°C) 15 mins Time (minutes) 5 mins 5 mins
Fig. 13. Temperature profile of the thermal cycling test (Specification of JEDEC standard).
TABLE II
THERMALCYCLINGTESTRESULTS
FCOB without underfill
0 cycle 200 cycles 400 cycles 600 cycles Resistance () 2.07 2.77 1.88
-Failure 0/3 0/3 2/3 3/3
FCOB with underfill
0 cycle 200 cycles 400 cycles 600 cycles Resistance () 1.97 2.44 1.99 2.55
Failure 0/3 0/3 0/3 0/3
in this paper (per JEDEC standard). The temperature range of the test was −55 to 125 °C with a 15-min dwell time. Table II shows the test results. Three samples with underfill and three samples without underfill were tested. For the flip-chip assemblies without underfill, two samples failed as the temperature cycling reached 400 cycles. All three samples without underfill failed after 600 cycles. The GaAs chips peeled off from the substrate bonding. The attachment of the chip to the substrate became weak as fatigue failure occurred at the bump–transition interface. For the flip-chip assemblies with underfill, as temperature cycling reached 600 cycles, no failure was observed. This is because the underfill redistributed the excessive stress and provided mechanical stability to the flip-chip structures.
However, the injection of the underfill could compromise the performance of the packaged devices [18]. As the epoxy-based underfill is filled in the flip-chip assemblies, an addi-tional loss arises because of the higher loss tangent of the epoxy (tan δ = 0.007 ∼ 0.02) compared to its value in air
(tan δ ∼ 0). As can be seen in Fig. 12, from dc to 40 GHz,
an average additional loss of 1 dB was induced as a result of the introduction of the underfill.
VII. CONCLUSION
The design, fabrication, and reliability of an FCOB package on a Rogers RO3210 laminate were studied up to 50 GHz. The Au CPW transmission line (W = 70 μm and G = 40 μm) and pillar bump (diameter= 50 μm) were successfully fabricated
on a high-k RO3210 laminate with photolithography and electroplating processes. The Au-to-Au thermal compression method was performed to flip-chip-bond the passive CPW transmission line and active discrete mHEMTs onto the RO3210 board. The passive flip-chip on RO3210 showed excellent performance up to 50 GHz, with a return loss S11 larger than 18 dB and insertion loss S21 within 0.5 dB. The electrical performance of the flip-chip-assembled in-house-fabricated mHEMT on RO3210 exhibited only a small gain degradation (less than 1.0 dB) from dc to 40 GHz, showing the potential of implementing MICs on the RO3210 board. Moreover, an underfill was applied to enhance the mechanical reliability of the packaged device on RO3210, resulting in an additional loss of 1 dB from dc to 40 GHz. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples with underfill passed the thermal cycling test up to 600 cycles. These results demon-strate the feasibility of using FCOB packaging technology on RO3210 laminates for commercial applications up to 50 GHz. To the best of our knowledge, this is the first study that evaluated the use of RO3210 laminate for microwave flip-chip in the open literature.
ACKNOWLEDGMENT
The authors would like to thank Y. M. Teng and G. W. Huang at the High Frequency Technology Center, National Nano Device Laboratories, Hsinchu, Taiwan, for help with the radio frequency measurements.
REFERENCES
[1] G. Baumann, H. Richter, A. Baumgärtner, D. Ferling, and R. Heilig, “51 GHz frontend with flip chip and wire bond interconnections from GaAs MMICs to a planar patch antenna,” in Proc. IEEE MTT-S Int.
Microw. Symp. Dig., vol. 3. Orlando, FL, May 1995, pp. 1639–1642.
[2] D. Staiculescu, J. Laskar, and E. M. Tentzeris, “Design rule development for microwave flip-chip applications,” IEEE Trans. Microw. Theory
Tech., vol. 48, no. 9, pp. 1476–1481, Sep. 2000.
[3] A. Jentzsch and W. Heinrich, “Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microw.
Theory Tech., vol. 49, no. 5, pp. 871–878, May 2001.
[4] C. L. Wang and R. B. Wu, “Modeling and design for electrical performance of wideband flip-chip transition,” IEEE Trans. Adv. Packag., vol. 26, no. 4, pp. 385–391, Nov. 2003.
[5] K. Maruhashi, M. Ito, H. Kusamitsu, Y. Morishita, and K. Ohata, “RF performance of a 77 GHz monolithic CPW amplifier with flip-chip interconnections,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., vol. 2. Baltimore, MD, Jun. 1998, pp. 1095–1098.
[6] H. Kusamitsu, Y. Morishita, K. Maruhasi, M. Ito, and K. Ohata, “The flip-chip bump interconnection for millimeter-wave GaAs MMIC,” IEEE
Trans. Electron. Packag. Manuf., vol. 22, no. 1, pp. 23–28, Jan. 1999.
[7] P. Monfraix, J. Monsarrat, J. L. Muraro, C. Drevon, S. Dareys, M. Billot, and J. L. Cazaux, “Is hermitic encapsulation of GaAs MMIC still required for space applications?” in Proc. IEEE MTT-S Int. Microw.
Symp. Dig., Long Beach, CA, Jun. 2005, pp. 1–4.
[8] D. Gamota and C. Melton, “Materials to integrate the solder reflow and underfill encapsulation processes for flip chip on board assembly,”
IEEE Trans. Comp., Packag., Manuf. Technol., Part C, vol. 21, no. 1,
pp. 57–65, Jan. 1998.
[9] Y. K. Song and C. C. Lee, “Millimeter-wave coplanar strip (CPS) line flip chip packaging on PCBs,” in Proc. 55th Electron. Comp. Technol.
Conf., vol. 2. Lake Buena Vista, FL, May–Jun. 2005, pp. 1807–1813.
[10] M. Case, “SiGe MMICs and flip-chip MICs for low-cost microwave systems,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Denver, CO, Jun. 1997, pp. 117–120.
[11] G.-W. Xiao, X. Huo, and P. C. H. Chan, “RF circuit integration using high Q copper inductors on organic substrate and solder-bumped flip chip technology,” in Proc. 53rd Electron. Comp. Technol. Conf., New Orleans, LA, May 2003, pp. 487–492.
[12] W. Deal, “Coplanar waveguide basics for MMIC and PCB design,” IEEE
Microw. Mag., vol. 9, no. 4, pp. 120–133, Aug. 2008.
[13] H.-P. Chang, J. Qian, B. A. Cetiner, F. De Flaviis, M. Bachman, and G. P. Li, “Design and process considerations for fabricating RF MEMS switches on printed circuit boards,” J. Microelectromech. Syst., vol. 14, no. 6, pp. 1311–1322, Dec. 2005.
[14] M. Akram, A. Javed, and T. Z. Rizvi, “Dielectric properties of industrial polymer composite materials,” Turk J. Phys., vol. 29, no. 6, pp. 355–362, 2005.
[15] G. E. Ponchak, J. Papapolymerous, and M. M. Tentzeris, “Excitation of coupled slotline mode in finite-ground CPW with unequal ground-plane widths,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 713–717, Feb. 2005.
[16] H. H. M. Ghouz and E. El-Aharawy, “An accurate equivalent circuit model of flip chip and via interconnects,” IEEE Trans. Microw. Theory
Tech., vol. 44, no. 12, pp. 2543–2554, Dec. 1996.
[17] E. Y. Chang, G. T. Cibuzar, and K. P. Pande, “Passivation of GaAs FET’s with PECVD silicon nitride films of different stress states,”
IEEE Trans. Electron Devices, vol. 35, no. 9, pp. 1412–1418, Sep.
1988.
[18] Z. Feng, W. Zhang, B. Su, K. C. Gupta, and Y. C. Lee, “RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill,” IEEE Trans. Microw. Theory Tech., vol. 46, no. 12, pp. 2269–2275, Dec. 1999.
Li-Han Hsu was born in Tainan, Taiwan, in 1981.
He received the B.S., M.S., and Ph.D degrees from the Department of Materials Science and Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, in 2003, 2005, and 2010, respectively.
He is currently with Taiwan Semiconductor Man-ufacturing Company Research and Development, Taipei, Taiwan, working on TSV-based 3DIC tech-nologies. His current research interests include millimeter-wave packaging technology, including flip-chip interconnects, hot-via interconnects, and integration of V-/E-band MCM transceiver modules.
Oh Chee Way received the M.S. degree in materials
science and engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2007. In his studies, he was involved with the Flip-Chip Packaging Group of the Compound Semiconductor Device Laboratory.
Wei-Cheng Wu was born in Hsinchu, Taiwan, in
1979. He received the B.S. and Ph.D. degrees in materials science and engineering from National Chiao Tung University, Hsinchu, in 2001 and 2007, respectively.
He is currently with Taiwan Semiconductor Man-ufacturing Company Research and Development, Taipei, Taiwan, working on 3DIC-related technolo-gies. His current research interests include fabrica-tion, characterizafabrica-tion, and packaging technologies of compound semiconductor devices and integrated circuits for high-frequency applications, especially flip-chip interconnects and transition design.
Edward Yi Chang (S’85–M’85–SM’04) received
the B.S. degree from National Tsing Hua University, Hsinchu, Taiwan, and the Ph.D. degree from the University of Minnesota, Minneapolis, in 1977 and 1985, respectively, both in materials science and engineering.
He was with Unisys Corporation GaAs Compo-nent Group, Eagan, MN, from 1985 to 1988, and the Comsat Labs Microelectronic Group from 1988 to 1992. He worked on the GaAs MMIC programs with both groups. He was with National Chiao Tung University (NCTU), Hsinchu, in 1992. In 1994, he helped set up the first GaAs MMIC production line in Taiwan and became the President of Hexawave Inc., Hsinchu, in 1995. In 1999, he returned to NCTU with a teaching position, where he is currently a Professor and the Head of the Department of Materials Science and Engineering. His current research interests include new device and process technologies for compound semiconductor radio frequency integrated circuits for wireless communication.
Dr. Chang is a Senior Member and a Distinguished Lecturer of the IEEE Electronic Device Society.
Herbert Zirath (S’84–M’86) was born in Göteborg,
Sweden, on March 20, 1955. He received the M.Sc. and Ph.D. degrees from Chalmers University, Göte-borg, Sweden, in 1980 and 1986, respectively.
He is currently a Professor of high speed elec-tronics with the Department of Microtechnology and Nanoscience, Chalmers University. He became the Head of the Microwave Electronics Labora-tory in 2001. Currently, he is leading a group of approximately 30 researchers in the area of high-frequency semiconductor devices and circuits. He is also working part-time with Ericsson AB, Mölndal, Sweden, as a Microwave Circuit Expert. He has authored or co-authored more than 220 papers in international journals and conference proceedings and one book. He holds four patents. His current research interests include InP-HEMT devices and circuits, SiC and GaN-based transistors for high-power application, device modeling, including noise and large-signal models for FET and bipolar devices, and foundry-related monolithic microwave integrated circuits for millimeter-wave applications based on both III–V and silicon devices.
Chin-Te Wang was born in Taipei, Taiwan, on
November 6, 1983. He received the B.S. degree from the Department of Materials Science and Engi-neering, National Chung Hsing University (NCHU), Taichung, Taiwan, in 2006, where his research focus was electric materials. He was interested in electric materials when he studied in NCHU. He began pursuing the M.S. and Ph.D. degrees in 2006.
He joined the Compound Semiconductor Device Laboratory, National Chiao Tung University, Hsinchu, Taiwan, in 2006.
Szu-Ping Tsai was born in Pingtung, Taiwan, on
February 2, 1985. She received the B.S. degree in materials science and engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2007, where she is currently pursuing the M.S. degree.
She joined the Compound Semiconductor Device Laboratory, NCTU, working in the area of flip-chip technology, focusing on aspects of finite element thermo-mechanical modeling and simulation.
Wee-Chin Lim was born in Johor, Malaysia, in
1986. She received the B.S. degree from the Depart-ment of Materials Science, National University of Malaysia, Bangi, Malaysia, in 2008. She is currently pursuing the Masters degree with the Department of Materials Science and Engineering, National Chiao Tung University (NCTU), Hsinchu, Taiwan.
She is currently with the Compound Semiconduc-tor Device LaboraSemiconduc-tory, NCTU.
Yueh-Chin Lin was born in Taipei, Taiwan. He
received the B.S. degree in nuclear engineering and engineering physics and the M.S. degree in electrical engineering from Tsing Hua University, Hsinchu, Taiwan, and the Ph.D. degree in materials science and engineering from National Chiao Tung Univer-sity (NCTU), Hsinchu, Taiwan, in 1996, 2000, and 2006, respectively.
He was with NTT Basic Research Laboratories, Kanagawa, Japan, from 2004 to 2006, where he investigated the growth of AlGaSb/InAs HEMT on Si substrate by molecular beam epitaxy. He is currently a Post-Doctoral Researcher with the Department of Materials Science, NCTU. His current research interests include molecular beam epitaxy material growth and HEMT device design and fabrication for wireless communication.
