行政院國家科學委員會專題研究計畫 成果報告
多功能反轉移函數電路合成技術開發
研究成果報告(精簡版)
計 畫 類 別 ： 個別型
計 畫 編 號 ： NSC 99-2221-E-151-063-
執 行 期 間 ： 99 年 08 月 01 日至 100 年 10 月 31 日
執 行 單 位 ： 國立高雄應用科技大學電子工程系
計 畫 主 持 人 ： 王鴻猷
共 同 主 持 人 ： 蔣元隆
計畫參與人員： 碩士班研究生-兼任助理人員：楊子毅
碩士班研究生-兼任助理人員：邱俊偉
報 告 附 件 ： 出席國際會議研究心得報告及發表論文
公 開 資 訊 ： 本計畫涉及專利或其他智慧財產權，1 年後可公開查詢
中 華 民 國 100 年 11 月 06 日
中文摘要： 本計畫主要以先前的背景知識與研究的心得，了解目前電路轉
換合成的發展狀況，利用 Pathological Element 模型化電路
元件，開發應用於多功能反轉移函數電路轉換合成技術，包括
電流式電路與電壓式電路
英文摘要： Circuit analysis and synthesis are performed using
pathological element equivalent models.
Multi-function current-mode and voltage-mode can be
generated. Their functions are verified by HSPICE
simulator.
行政院國家科學委員會補助專題研究計畫
■成果報告
□期中進度報告
多功能反轉移函數電路合成技術開發
計畫類別：
■
個別型計畫 □整合型計畫
計畫編號：NSC
99-2221-E-151 -063
執行期間： 99 年 8 月 1 日至 100 年 7 月 31 日
執行機構及系所：
國立高雄應用科技大學電子工程系
計畫主持人：
王鴻猷
共同主持人：
蔣元隆
計畫參與人員：
黃文鐘、楊子毅
成果報告類型(依經費核定清單規定繳交)：
■
精簡報告 □完整報告
本計畫除繳交成果報告外，另須繳交以下出國心得報告：
□赴國外出差或研習心得報告
□赴大陸地區出差或研習心得報告
■
出席國際學術會議心得報告
□國際合作研究計畫國外研究報告
處理方式：
除列管計畫及下列情形者外，得立即公開查詢
■
涉及專利或其他智慧財產權，
■
一年□二年後可公開查詢
中 華 民 國 100 年 10 月 31 日
中文摘要:
本計畫目的為利用 Pathological Element 開發多功能反轉移函數電路之合成技術。在研
究電路轉換技術的過程中，我們利用 Pathological Element 模型化主動元件，由於利用
Pathological Element (Nullor 元件與 Mirror 元件)來代表主動元件比單純使用 Nullor 元件來
代表主動元件，可得到較簡易的電路，因此我們也開發出高效能電路符號分析方法，可簡
化電路符號分析過程而增進分析效率。同時，我們利用主動元件的 Pathological Element 等
效，也成功的開發出多功能反轉移函數電路之合成技術
關鍵字：特異元件、符號分析、電路合成
Abstract
The aim of this research is to develop a circuit synthesis technique for obtaining the inverse
transfer function of original circuit. The synthesis technique can be applied on voltage-mode and
current-mode circuits. In this study, the pathological elements (nullor and mirror elements) are
used to represent active devices. The nullor–mirror equivalent of a circuit may be simpler than its
nullor equivalent since the latter might possess a smaller node number. We successfully develop
an efficient symbolic analysis method which can be applied to nullor–mirror equivalents of
circuits. Besides, by using the proposed nullor–mirror equivalences of pathological network, the
circuit synthesis technique for inverse transfer function has also been developed successfully.
Keywords: Pathological Element、Symbolic analysis、Circuit synthesis
一、前言:
類比電路大都以電壓作為訊號的代表，近年來，電流式類比電路已被接受為電壓式
類比電路以外的另一可考慮的選擇，所謂電流式電路，是指以電流作為信號的代表，但廣
義的電流式電路定義為，電路的輸出或輸入變數中，出現以電流信號作為信號代表的，換
言之，即取電路的輸出或輸入變數為電流輸出或電流源輸入。電流式電路與電壓式電路的
比較上有幾個可能的優異點[1-2](即在某些電路應用上有如下優點)：
(1) 較高的頻寬：
雙極性電晶體(BJT)與場效電晶體(FET)都是電流輸出的元件，以電流式的訊號處理自
然有較大頻寬的能力，電晶體構成的電流放大器頻寬幾乎可工作到其單一增益頻寬f
T。
(2) 較寬的動態範圍(Dynamic Range)：
CMOS 積體電路技術的進步使得元件尺寸不斷的縮小，直流電壓準位的減小導致電
壓式電路信號動態範圍的縮小，其中一種克服此問題的方法即將其改變成電流式電路，如
此一來，信號的動態範圍可不直接受限於電壓準位，而是決定於設計者所選擇的輸入阻抗
準位。
(3) 算術運算上較低的電路複雜度：
由於電路的連接對電流而言可以做加減法運算，利用電流鏡(Current Mirror)電路可以
很方便的做訊號的放大，相對於電壓式類比電路使用運算放大器來做這些運算而言，電路
複雜度可以降低不少。
(4) 較快的操作速度：
在實際電路裡，寄生效應主要是寄生電容所主宰，寄生電容的影響造成電壓無法快
速變動，而電流的變動則不受寄生電容效應的影響。
除了電流式電路受到廣泛的注意外，電流式主動元件亦受到不少的注意，所謂電流
式主動元件是指其輸入與輸出變數包括了電流與電壓變數，這類主動元件包括電流傳輸器
(Current Conveyor, CC)、可控制電流傳輸器(Controlled Current Conveyor, CCCII)、電流回授
運算放大器(Current-Feedback Operational Amplifier, CFOA)、運算轉導放大器(Operational
Transconductance Operational, OTA) 、 運 算 浮 接 放 大 器 (Operational Floating Amplifier,
OFA)、差動電壓電流傳輸器(Differential Voltage Current Conveyor, DVCC)等...[3]，這類
主動元件之所以被使用來設計電路，乃因其輸出輸入埠具備電流或電壓的變數，可用來設
計電流式或電壓式電路，在電路設計時比完全以電壓為變數的主動元件(例如Op-Amp)，具
備更大的設計彈性，因此，文獻上很多使用這類元件的應用電路被提出[1, 3-6]。
二、研究目的:
在許多電路合成技術中，特異元件(Pathological Element)常被用來作為主動元件的模
型，在通訊、控制與儀表系統，許多時候會利用訊號處理器與傳輸器將訊號作線性或非線
性轉換，因此就需要將後端所接收到的失真訊號加以回復，此時就需要原電路的反轉移函
數電路，例如頻率調變(FM)系統中 Pre-emphasis 與 De-emphasis 處理、指數與對數放大器
(Exponential and Logarithmic Amplifiers )、乘法與除法運算(Multiplication and Division )。在
數位訊號處理中，已有數種技術來實現數位反轉濾波器(Inverse Filter)電路[7]，然而，已知
的方法與電路來實現連續時間類比反轉濾波器[8-11]卻較少見。本研究目的為開發多功能
反轉移函數電路之合成技術，此技術可應用於各種電流式電路與電壓式電路。
三、文獻探討:
在文獻[8]中，使用Nullor作為主動元件的模型，以獲得線性動態系統反轉移函數
(Transfer Function)，以及非線性電阻電路之反轉特性(Inverse Characteristic)。於[9]中，使用
Nullor的觀念、對偶轉換(Dual Transform)、反轉換(Inverse Transform)、Bruton轉換，而實
現利用FTFN (Four Terminal Floating Nullor)實現之電流式反轉濾波器。而[10] 中，則是利
用Nullor 的觀念、伴隨轉換(Adjoint Transform)、反轉換，來實現利用FTFN (Four Terminal
Floating Nullor)實現之電流式反轉濾波器。此方法因可適用於非平面電路，且轉換過程較
簡單，故比[9]所提出的方法更具實用性。在[11]中，則利用CFOA來完成四個電路設計，其
個別實現不同類型的反轉濾波器。包括反轉低通(Inverse Lowpass)、反轉帶通(Inverse
Bandpass)、反轉高通(Inverse Highpass)與反轉帶拒(Inverse Bandreject)濾波器，其電路架構
如圖1所示，而其轉移函數分別為:
2 1 2 1 3 2 2 2 1 2 1 0 2 01
1
1
R
R
C
C
R
C
s
s
R
R
C
C
R
R
V
V
in
3 1 2 1 2 2 2 2 2 0 2 0
1
1
R
R
C
C
R
C
s
s
R
C
s
R
R
V
V
in
(Inverse Bandpass) (圖 1b)
3 2 2 1 2 1 2 2 0 1 01
1
R
R
C
C
R
C
s
s
s
R
R
V
V
in
(Inverse Highpass) (圖 1c)
4 2 2 1 4 3 2 1 2 4 2 2 1 2 01
1
1
R
R
C
C
s
R
R
C
R
s
R
R
C
C
s
V
V
in
(Inverse Bandreject) (圖 1d)
(a) Inverse Lowpass Filter (b) Inverse Bandpass Filter
(c) Inverse Highpass Filter (d) Inverse Bandreject Filter
圖1 使用CFOA所設計的Inverse Filter
四、研究方法:
在研究電路轉換技術的過程中，我們利用 Pathological Element 模型化主動元件，由於
利用 Pathological Element (Nullor 元件與 Mirror 元件)來代表主動元件比單純使用 Nullor 元
件來代表主動元件，可得到較簡易(少節點)的電路，因此我們也開發出高效能電路分析方
法，可簡化電路符號分析的進行而快速的完成分析。其步驟如下:
1. 依照表 1 的特性，標示流過 Norator 與 Current Mirror 之電流，選定接地點與標示各節點。
2. 寫下各節點的矩陣導納方程式成 I = YV 形式。
3. 若 Nullator 連接於 p 與 q 節點間(p 與 q 節點均非接地點)，在 Y 中，自第 p 行元素加第 q
行元素並刪去第 q 行。
4. 若 Voltage Mirror 連接於 r 與 s 節點間(r 與 s 節點均非接地點)，在 Y 中，自第 r 行元素減
去第 s 行元素並刪去第 s 行。
5. 若 Norator 連接於 l 與 m 節點間(l 與 m 節點均非接地點)，自第 l 列方程式加第 m 列方程
式，再刪去第 m 列方程式。
6. 若 Current Mirror 連接於 n 與 o 節點間(n 與 o 節點均非接地點)，自第 n 列方程式減去第 o
列方程式，再刪去第 o 列方程式。
7. 若 Nullator(或 Voltage Mirror)連接於 k 節點與接地點間，在 Y 中刪去第 k 行。
8. 若 Norator (或 Current Mirror)連接於 i 節點與接地點間，刪去第 i 列方程式。
9. 解所得到的方程式
經過以上步驟後，我們所作的電路符號分析矩陣方程式較原矩陣方程式簡潔許多，所
以此時解節點方程式，可較快速的完成電路分析，因而增進了符號節點分析的效率。
同時，文獻中已有許多主動元件的等效模型，如表 1 所示，此外，也有不少的 Pathological
Element 等效電路發表於文獻中[12-15]，表 2 所示為文獻[12]中提出的 Pathological Element
等效電路之例子。
表 2 Pathological Element 等效例子
我們使用主動元件的等效模型，所開發出新的 Pathological Element 等效，如圖 2 所
示，圖 2(a)與(b)是分別應用於 Current Mirror/Norator 與 Voltage Mirror/Nullator 上的等效模
型。
=
=
I1 I1 I2 I1+I2 I1 I1+I2 I2 I1+I2 I1 I2=
=
(a) (b)圖 2 Pathological Element 等效
為示範所開發的多功能反轉移函數電路之合成技術，我們以圖 3 的多功能 Inverse Filter
為例，此 Inverse Filter 之轉移函數如下式:
2 4 1 3 0 4 out inV
y y
y y
V
y y
(1)
藉由使用不同導納來取代 y
0~y
4，其可實現單輸入多輸出的濾波器如表 3 所示。
由於 CFOA 等同於 CCII+加一 Voltage Buffer，觀察圖 3 的電路可發現 CFOA 的 w 端均
未與其他節點連結，因此我們可先使用 CCII+模型取代 CFOA，如圖 4(a)所示，CCII+以
Pathological Nullor 與 Current Mirror 取代，我們先使用 Adjoint Transform 可得其電流轉移
函數 I
out/I
in= (y
2y
4+y
1y
3)/y
0y
4，利用表 2 之 norator rearrangement 與圖 2(b)之等效，再使用
Inverse Transform 得到其電流轉移函數 I
out/I
in= y
0y
4/(y
2y
4+y
1y
3)，再使用 Adjoint Transform
可得圖 4(b)之電路，其電壓轉移函數 V
out/V
in= y
0y
4/(y
2y
4+y
1y
3)，其轉移函數為(1)式之反轉
移函數，由於(1)式可藉由使用不同導納取代 y
0~y
4以實現單輸入多輸出的多功能轉移函數
濾波器，因圖 4(b)電路的轉移函數為(1)式之反轉移函數，因此，我們可預期圖 4(b)電路亦
可藉由使用不同導納取代 y
0~y
4來實現單輸入多輸出的多功能轉移函數濾波器，所以，我
們成功開發出多功能反轉移函數電路之合成技術。
表 3 圖 3 中多功能 Inverse Filter 的各種可能實現
(a)圖 3 電路的 Pathological Element 等效 (b)應用等效與轉換所得之反轉移函數電路
圖 4 多功能反轉移函數電路之合成電路例
五、結果與討論:
本研究利用電路主動元件的 Pathological Element 模型，與我們所研發的 Pathological
Element 等效，搭配電路轉換技術，成功的開發出多功能反轉移函數電路之合成技術，此
技術適用於任何線性電路。在研究電路轉換技術的過程中，我們也開發出高效能電路分析
方法，可簡化電路符號分析的進行以增進分析效率[16]。我們以實例證明了所開發技術之
可行性。
參考文獻
[1] C. Toumazou, F.J. Lidgey, and D.G. Haigh, Analogue IC design: the Current-Mode Approach
(London: Peter Peregrinus), 1990.
[2] A.F. Arbel and L. Goldminz, “Output stage of current-mode feedback amplifiers, theory and
applications”, Analog Integrated Circuits and Signal Processing, 2, pp. 243-255, 1992.
[3] H. Schmid, “Approximating the universal active element”, IEEE Trans. Circuit and System –II,
vol. 47, pp. 1160-1169, 2000.
[4] B. Nauta, Analog CMOS Filters for Very High Frequencies, Kluwer Academic Publishers,
1993.
[5] A. Carlosena, and G. S. Moschytz, “Nullators and norators in voltage to current mode
transformations”, Int. J. Circuit Theory and Applications, vol. 21, pp. 421-424, 1993.
[6] P. Kumar and R. Senani, “Bibliography on nullors and their applications in circuit analysis,
synthesis and design”, Analog Integrated Circuits and Signal Processing, 33, pp.65-76, 2002.
[7] R. Kuc, “Introduction to digital signal processing” (McGraw-Hill,1988), Chap. 11
[8] A. Leuciuc, “Using nullors for realization of inverse transfer functions and characteristics”,
Electronics Letters
, vol. 33, pp. 949-951, 1997.
[9] B. Chipipop and W. Surakampontorn, “Realisation of currentmode FTFN-based inverse filter”,
Electronics Letters
, 35, pp. 690–692, 1999.
[10] H.Y. Wang and C.T. Lee, “Using nullors for realisation of currentmode FTFN-based inverse
filters”, Electronics Letters, 35, pp. 1889–1890, 1999.
[11] S. S. Gupta, D. R. Bhaskar, R. Senani and A. K. Singh, “
Inverse active filters employing
CFOAs
”, Electrical Engineering, 91, 1, pp. 23-26, 2009.
[12] G.H. Wang, Y. Fukui, K. Kubota, and K. Watanabe, “Voltage-mode to current-mode
conversion by an extended dual transformation”, IEEE Int. Symp. Circuits Syst., 1991, pp.
1833–1836.
[13] R. Palomera-Garcia, “Generation of equivalent circuits by FTFN relocation.” In Proc. IEEE
Int. Symp. Circuits Syst
., 2005, pp. 252–255.
[14] H.Y. Wang, C.T. Lee and C.Y. Huang, “Characteristic investigation of new pathological
elements.” Analog Integrated Circuits and Signal Processing, vol. 44, pp. 95–102, 2005.
[15] H.Y. Wang, C.Y. Liu, and S.H. Chang, “New nullor–mirror equivalences,”
InternationalJournal of Electronics and Communications (AEU)
, 64, pp. 828-832, 2010.
[16] H.Y. Wang, W.C. Huang, and N.H. Chiang, “Symbolic nodal analysis of circuits using
pathological elements,” IEEE Transactions on Circuits and Systems II: Express Briefs, 57,
11, pp. 874 – 877, 2010.
國科會補助專題研究計畫成果報告自評表
請就研究內容與原計畫相符程度、達成預期目標情況、研究成果之學術或應用價
值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）
、是否適
合在學術期刊發表或申請專利、主要發現或其他有關價值等，作一綜合評估。
1. 請就研究內容與原計畫相符程度、達成預期目標情況作一綜合評估
■
達成目標
□ 未達成目標（請說明，以 100 字為限）
□ 實驗失敗
□ 因故實驗中斷
□ 其他原因
說明：
2. 研究成果在學術期刊發表或申請專利等情形：
論文：■已發表 □未發表之文稿□撰寫中 □無
專利：□已獲得 □申請中 ■無
技轉：□已技轉 □洽談中 ■無
其他：（以 100 字為限）
3. 請依學術成就、技術創新、社會影響等方面，評估研究成果之學術或應用價
值（簡要敘述成果所代表之意義、價值、影響或進一步發展之可能性）（以
500 字為限）
本研究主要有 2 項成果，其中之一已產出 1 篇論文並發表於國際知名期
刊(IEEE Transactions on Circuits and Systems II: Express Briefs, 57, 11, pp.
874 – 877, 2010)，論文主題為: Symbolic nodal analysis of circuits using
pathological elements。本成果乃利用教科書提及的符號節點分析法，結合新
的 Pathological element，使電路符號節點分析更有效率，因電路符號分析常使
用節點分析法，利用矩陣與 Cramer＇s Rule 求解電路，利用我們研究成果，
可降低矩陣的階數，因而增加了電路分析效率，我們提出的方法適用於任何
電壓式或電流式電路，因此有機會被包括於教科書中。
另外 1 項成果是有關電路合成，藉由電路 Pathological Element 等效模型
的使用，可合成不同類型的電路，例如電流式與電壓式電路相互轉換，電路
轉移函數與反轉移函數的轉換，並可利用不同的主動元件來實現所轉換得到
的電路。
附件二
874 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010
Symbolic Nodal Analysis of Circuits Using
Pathological Elements
Hung-Yu Wang, Member, IEEE, Wen-Chung Huang, and Nan-Hui Chiang
Abstract—The nullor as a network element is useful in the
syn-thesis and analysis of active networks. It can be used to formulate the system of equations for symbolic nodal analysis. This brief presents a systematic analytical technique that performs efficient nodal analysis forRLC–nullor–mirror networks directly without replacing the mirror elements with their nullor equivalents. It is conducive to achieving high-performance symbolic nodal analysis since theRLC–nullor–mirror representation possesses reduced circuit complexity compared to theRLC–nullor equivalent. The feasibility and validity are demonstrated by two representative current-mode and voltage-mode circuits.
Index Terms—Pathological element,RLC–nullor–mirror
net-work, symbolic nodal analysis (NA).
I. INTRODUCTION
T
HE CONCEPT of the nullor as a network element is useful in the synthesis and analysis of active networks [1]–[6]. The main reasons for the popularity of the nullor elements are their ability to model active circuits independently of the particular realization of the active devices and the simplicity with which nodal analysis (NA) of these circuits can be carried out. Symbolic analysis at the circuit level is a formal technique used to calculate the behavior or a characteristic of a circuit with the independent variable (time or frequency), the dependent variables (voltages and currents), and (some or all of) the circuit elements represented by symbols. It is mainly used as a means to gain insights into the behavior of the circuits, to generate analytical models for automated circuit sizing, and in applications requiring the repetitive evaluation of circuit characteristics [7]–[9]. The nullor is often used to model all active devices to perform symbolic analysis by only applying NA [10]. Despite the ability of nullors to represent all active el-ements, without the use of resistors, they fail to represent some important analog elements. Therefore, two new pathological elements, i.e., the current mirror and voltage mirror are defined [11]. The new defined pathological mirror elements are basi-cally used to represent active devices with current or voltage reversing properties. Their usefulness to circuit synthesis has been demonstrated in the literature [2], [12]–[15].To take advantage of the symbolic NA of nullor networks [16]–[18], the nullor equivalents of mirror elements,
compris-Manuscript received May 16, 2010; revised August 2, 2010; accepted August 23, 2010. Date of publication October 28, 2010; date of current version November 17, 2010. This work was supported by the National Science Council of the Republic of China under Grant NSC 99-2221-E-151-063. This paper was recommended by Associate Editor A. Brambilla.
H.-Y. Wang and N.-H. Chiang are with the Department of Electronic Engi-neering, National Kaohsiung University of Applied Sciences, Kaohsiung 807, Taiwan (e-mail: hywang@cc.kuas.edu.tw; 1097405109@cc.kuas.edu.tw).
W.-C. Huang is with the General Education Center, Chung Hwa University of Medical Technology, Tainan 717, Taiwan.
Digital Object Identifier 10.1109/TCSII.2010.2082930
ing nullor elements and resistors, are proposed. For instance, the nonideal voltage mirrors and current mirrors are modeled by nullor elements and resistors to perform symbolic analysis [16]. The nullor-based models of the different kinds of current con-veyors and current feedback op-amp are presented for symbolic analysis in [18]. The symbolic analysis of mixed-mode analog circuits by virtue of the nullors is presented in [24]. In all the aforementioned approaches, the active elements are represented with nullors and passive elements. Compared with the nullor equivalents of active elements, the nullor–mirror equivalents may be simpler since the latter might possess a smaller node number [11], [14]. Therefore, the circuit complexity could be reduced if we were to useRLC–nullor–mirror networks rather thanRLC–nullor networks to represent circuits.
The primary purpose of this brief is to describe a systematic technique that can be used to obtain and solve the network equations of RLC–nullor–mirror networks. This method in-volves writing the nodal admittance matrix equations of a correspondingRLC–nullor–mirror network, and the dimension of the admittance matrix has been reduced by considering the property of every pathological element. Two practical circuit examples are given to demonstrate the feasibility of the pro-posed approach.
II. SYMBOLICNAOFRLC–NULLOR–MIRRORNETWORK
The symbols and definitions of the nullor and mirror ele-ments are shown in Table I. They are pathological eleele-ments that possess ideal characteristics and are specified on the basis of the constraints they impose on their terminal voltages and currents. The voltage mirror, shown in Table I(c), is a lossless two-port network element used to represent an ideal voltage reversing action. The current mirror, shown in Table I(d), is a two-port network element used to represent an ideal current reversing action. It is worth noting that each of the voltage mirror and the current mirror symbols shown in Table I has a reference node, which is set to ground. Although these elements are two-port network elements, they can be used as two terminal elements with the reference node unused [2]. The current mirror element shown in Table I(d) has the same symbol as the regular current mirror, but it is a bidirectional element and has a theoretical existence [2], [13].
The RLC–nullor networks have been used to perform the circuit analysis and generate a number of equivalent ideal-ized circuits [19]. Because the new proposed pathological el-ements are helpful in representing the active devices with lower complexity, the nullor–mirror equivalent of a circuit might be simpler than the nullor equivalent of a circuit. The direct analysis ofRLC–nullor–mirror networks will be conducive to
WANG et al.: SYMBOLIC NODAL ANALYSIS OF CIRCUITS USING PATHOLOGICAL ELEMENTS 875
TABLE I
SYMBOLS ANDDEFINITIONS OFNULLOR ANDMIRRORELEMENTS
efficient circuit analysis. The steps for the symbolic NA of
RLC–nullor–mirror networks are proposed below. They
in-volve the symbolic NA of an arbitrary interconnection of
RLC–nullor–mirror networks and independent current sources
in an (N + 1) node network and can be summarized as follows.
Step 1) According to the properties in Table I, denote the currents flow through allK norators and L current mirrors. It is known that no current flows through the nullators and voltage mirrors of the network. Select a ground node and label all other nodes from 1 toN. Step 2) For the(N + 1) node network, write the (N × N)
nodal admittance equations in matrix form:
I = YN×NV (1)
I = {I1, I2, . . . , IN}, where theith component Ii is defined as the sum of the currents flowing into theith node from the independent current sources, norators, or current mirrors.YN×N is the passive nodal admittance matrix. Furthermore, V is the unknown column vector{V1, V2, . . . , VN}of node voltages [19].
Step 3) For a nullator that is connected between the nodes p and q, for example, add the elements of columnq to the elements of column p and delete column q of Y. The number of columns of the Y matrix is thereby reduced by one. Repeat this process for every nullator not connected to the ground node. This operation is based on the voltages at the two terminals of a nullator with respect to the ground node being identical. Thus, we can omit one unknown voltage variable in theV column vector. Step 4) For a voltage mirror that is connected between the
nodesr and s, for example, subtract the elements of column s from the elements of columnr and delete
columns of Y. The number of columns of the Y matrix is also thereby reduced by one. Repeat this process for every voltage mirror not connected to the ground node. This operation is based on the voltage reversing property of a voltage mirror in Table I(c). Step 5) For a norator that is connected between nodesl and
m, for example, add the equation in row m to the
equation in row l and delete row m of the nodal equations. This involves adding Im to I1 and the
mth row of the admittance matrix to the lth row
of the admittance matrix. Repeat this process for every norator not connected to the ground node. This operation is based on the current property of a norator in Table I(b).
Step 6) For a current mirror that is connected between the nodesn and o, for example, subtract the equation in rowo from the equation in row n and delete row o of the nodal equations. This involves subtractingIo from In and the oth row of the admittance matrix from thenth row of the admittance matrix. Repeat this process for every current mirror not connected to the ground node. This operation is based on the current property of a current mirror in Table I(d). Step 7) For a nullator (or a voltage mirror) that is connected
between, e.g., node k and the ground node, delete the kth column of the admittance matrix. Repeat this process for every nullator and every voltage mirror connected to the ground node. This operation is based on the fact that the zero voltages at the two terminals of a nullator (or a voltage mirror) with respect to the ground node are known.
Step 8) For a norator (or a current mirror) that is connected between, e.g., node i and the ground node, delete the equation in the ith row. This involves deleting
Iiand deleting theith row of the admittance matrix
equations. Repeat this process for every norator and every current mirror. This operation is based on the number of equations being enough to solve the unknown independent node voltages after deleting the equations mentioned [19].
Step 9) The preceding eight steps result in the reduction of the (N × N) nodal admittance matrix of the orig-inal network to the(N − K − L) × (N − K − L) nodal admittance matrix. The corresponding (N −
K − L) equations may be solved for the
inde-pendent node voltages. (K + L) is the number of nullators (or voltage mirrors) and norators (or cur-rent mirrors) pairs [2].
III. APPLICATIONEXAMPLES
We first consider the DXCCII-based current-mode filter [20]. The nullor–mirror equivalent of this filter is comprised of nullators, voltage mirrors, and current mirrors, as shown in Fig. 1 [21]. We can perform symbolic NA following the pro-cedure in Section II. Based on steps 1 and 2 in the previous section, we denote the flows of current through the four current mirrors, as shown in Fig. 1. After labeling all nodes in Fig. 1, we can write the (6× 6) nodal admittance equations in matrix form as in (2) and (3), shown at the bottom of the next page.
876 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010
Fig. 1. DXCCII-based current-mode filter.
Applying the third and fourth steps leads to the derivation of the nodal admittance matrix equations of (3). The nodal admittance matrix in (3) has dimensions of (6× 2) due to the two unknown node voltages.
By applying the fifth and sixth steps, the nodal admittance matrix equations can be given by (4). The nodal admittance matrix in (4) has dimensions of (4× 2) because there are two ungrounded current mirrors
⎡ ⎢ ⎣ Iin 0 −IC3 −IC4 ⎤ ⎥ ⎦ = ⎡ ⎢ ⎣ sC1+ 2GM2 2GM3 2GM1 −sC2 −2GM1− 2GM2 0 0 2GM3 ⎤ ⎥ ⎦ V1 V4 . (4)
After applying the seventh and eighth steps, the nodal admit-tance matrix equations are given by (5). The nodal admitadmit-tance matrix in (5) has dimensions of (2 × 2) because there are two grounded current mirrors. Therefore, there remains the solvable set of two equations for two unknown independent node voltages Iin 0 = sC1+ 2GM2 2GM3 2GM1 −sC2 V1 V4 . (5) As described in step 9 of the proposed procedure, the order of the system of equations is equal to the number of ungrounded nodes minus the number of pairs of nullators (or voltage mir-rors) and norators (or current mirmir-rors) (i.e.,2 = 6 − 4). Solving forV1andV4by Cramer’s rule, we obtain
V1=s2C sC2Iin
1C2+ 2sC2GM2+ 4GM1GM3 (6)
V4=s2C 2GM1Iin
1C2+ 2sC2GM2+ 4GM1GM3. (7)
Fig. 2. R-nullor equivalent circuit of a voltage source.
Therefore, we can derive
IoLP = − IC4= 2GM3V4 =s2C 4GM1GM3Iin 1C2+ 2sC2GM2+ 4GM1GM3 (8) IoBP = − IC3= −2(GM1+ GM2)V1 =s2C −2(GM1+ GM2)sC2Iin 1C2+ 2sC2GM2+ 4GM1GM3. (9) The analyzed results are consistent with the expressions in [20, eq. (9a) and (9b)], and thus, the validity is verified.
The second application example, which takes into account the ICCII-based filter in [22, Fig. 10(b)], is a voltage-mode filter. It must be noted that the inputted voltage source can be replaced with the equivalent circuit in Fig. 2 [23], to apply the analytical method with current input described in Section II. The second filter example with its nullor–mirror equivalent that comprises a norator, a current mirror and two voltage mirrors, is redrawn in Fig. 3. According to steps 1 and 2 in Section II, we can write the following (6× 6) nodal admittance equations in matrix form as ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ Vin −IN2 −IN −IC −IN −IC ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 1 0 0 0 0 0 0 G1 −G1 0 0 0 0 −G1 G1 0 0 0 0 0 0 sC1 0 0 0 0 0 0 G2+ sC2 −G2 0 0 0 0 −G2 G2 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ V1 V2 V3 V4 V5 V6 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ . (10) After applying the third to eighth steps of the proposed procedure, the nodal admittance matrix equations can be given by ⎡ ⎣Vin0 0 ⎤ ⎦ = ⎡ ⎣−G11 G01 G2+ sC0 2 0 −sC1 G2 ⎤ ⎦ ⎡ ⎣VV13 V5 ⎤ ⎦ . (11) ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ Iin− IC2 −IC1 −IC3 −IC1 −IC4 −IC2 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦= ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ sC1+ GM2 0 −GM2 0 0 0 0 GM1 −GM1 0 0 0 −GM2 −GM1 GM1+ GM2 0 0 0 0 0 0 sC2 0 0 0 0 0 0 GM3 −GM3 0 0 0 0 −GM3 GM3 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ V1 V2 V3 V4 V5 V6 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ (2) ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ Iin− IC2 −IC1 −IC3 −IC1 −IC4 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦= ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ sC1+ 2GM2 0 2GM1 0 −2GM1− 2GM2 0 0 sC2 0 2GM3 ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ V1 V4 (3)
WANG et al.: SYMBOLIC NODAL ANALYSIS OF CIRCUITS USING PATHOLOGICAL ELEMENTS 877
Fig. 3. ICCII-based voltage-mode filter.
As it is described in step 9 of the proposed method, the (6 × 6) nodal admittance matrix of the original network is reduced to the resultant (3× 3) admittance matrix. The order of the system of equations is equal to the number of ungrounded nodes minus the number of pairs of nullators (or voltage mirrors) and norators (or current mirrors) (i.e., 3 = 6 − 3). Similarly, we can derive the following analyzed results as
V3 Vin = VLP Vin = G1G2 s2C1C2+ sC1G2+ G1G2 (12) V5 Vin = VBP Vin = sC1G1 s2C1C2+ sC1G2+ G1G2. (13) The results are in accordance with the circuit functions of [22].
IV. CONCLUSION
In this brief, an efficient symbolic NA technique using
RLC–nullor–mirror networks rather than RLC–nullor
net-works has been proposed since an RLC–nullor–mirror rep-resentation might have a simpler circuit structure than its
RLC–nullor equivalent of a circuit. Following the proposed
an-alyzed procedure, the dimension of the nodal admittance matrix has been reduced by virtue of the properties of each pathologi-cal element. This method can be applied to both voltage-mode and current-mode circuits of an arbitrary interconnection of resistance, capacitance, inductance, and pathological elements. Two representative circuits modeled by pathological elements have been used for illustration. The first one contains nullators, voltage mirrors, and current mirrors, and the other one contains a norator, a current mirror, and voltage mirrors. Therefore, the four basic pathological elements applied to symbolic NA are demonstrated. It can be expected that the proposed technique is helpful to enhancing the efficiency of symbolic NA in analog design automation.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation Center for the technical support and the reviewers for their useful comments.
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