Investigation of abnormal negative threshold voltage shift under positive bias stress in
input/output n-channel metal-oxide-semiconductor field-effect transistors with
TiN/HfO2 structure using fast I-V measurement
Szu-Han Ho, Ting-Chang Chang, Ying-Hsin Lu, Ching-En Chen, Jyun-Yu Tsai, Kuan-Ju Liu, Tseung-Yuen Tseng , Osbert Cheng, Cheng-Tung Huang, and Ching-Sen Lu
Citation: Applied Physics Letters 104, 113503 (2014); doi: 10.1063/1.4868532
View online: http://dx.doi.org/10.1063/1.4868532
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/104/11?ver=pdfcov Published by the AIP Publishing
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Kuan-Ju Liu,2Tseung-Yuen Tseng,1Osbert Cheng,3Cheng-Tung Huang,3 and Ching-Sen Lu3
1
Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
2
Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan
3
Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan
(Received 22 December 2013; accepted 28 February 2014; published online 17 March 2014) This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO2n-channel metal-oxide-semiconductor field-effect transistors using
fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (Vt) shifts
positively during fast I-V double sweep measurement. However, in I/O devices, Vt
shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting HfxZr1xO2as gate oxide, can reduce the charge/discharge
effect.VC 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4868532]
As metal-oxide semiconductor field-effect transistors (MOSFETs) continue to shrink, the scaling of SiO2 gate
dielectrics is reaching its critical limit of only a few atomic layers thick. This scale causes a rise in gate current, perform-ance degradation, and an increase in power dissipation. Many years of research and development has shown that one valid way to solve these problems is by replacing conventional SiO2 gate dielectric with high-k dielectric, especially with
HfO2gate dielectric. HfO2gate dielectrics have been
imple-mented at the 32 nm technology node and smaller, with manu-facturer Intel using high-k/metal gate beginning with their 45 nm node. Furthermore, high-k gate dielectric can be inte-grated with strained-silicon,1silicon on insulator (SOI),2–4and architectures to improve device characteristics. High-k dielec-tric can also be combined with thin-film transistor devices5–9 and memory devices.10–12HfO2dielectrics have been heavily
studied in recent years to replace SiO2-based dielectrics.13,14
Simultaneously, contemporary input/output (I/O) devices were integrated into the technology. SiO2 and high-k/metal
gate architectures have been incorporated for these I/O devi-ces, which face significant reliability challenges. While there have been a few studies investigating reliability in I/O devices using fast I-V measurement, this study mainly focuses on pos-itive bias stress (PBS) in HfO2 dielectric I/O n-MOSFETs
using fast I-V measurement. The causes of the abnormal threshold-voltage (Vt) shift are explained in this letter.
The HfO2/metal gate n-channel MOSFETs used in this
study were fabricated with a gate first process flow. First, a high quality 1-nm or 3-nm thick thermal oxide was grown as an interlayer. Second, 3 nm of HfO2dielectrics were
sequen-tially deposited by atomic layer deposition. Third, 10 nm-thick TiN metal gates were deposited by radio frequency physical vapor deposition because metal gates can eliminate gate
depletion and resist remote phonon scattering.15,16Next, poly-crystalline silicon was deposited as a low resistance gate elec-trode. Finally, the dopant activation was performed at 1025C. During PBS, Id-Vgsweep curves using fast I-V
tech-nology are measured with 30 mV drain voltage, 0.6 V 1.7 V gate voltage, an integral time of 7 106s, a step edge of 5 107s, and step number of 10. Id-Vgfor double sweep fast
I-V curves with fixed base level voltage (Vbase level) or fixed
high level voltage (Vhigh level) were measured with 30 mV
drain voltage, an integral time of 1 105s, step edge of 1 108s, and step number of 80. In addition, hold time and delay time were both 5 s in order to ensure the steady state in Vbase leveland Vhigh level. All experimental curves were
meas-ured using an Agilent B1500 semiconductor parameter ana-lyzer and a Cascade M150 probe station.
Figure 1(a) shows DVt-log (stress time) characteristic
curves with 30 mV drain voltage under PBS over 500 s in HfO2(3 mn)/SiO2(3 nm) I/O devices using fast I-V
measure-ment. Obviously, it exhibits an abnormal Vtshift in the
nega-tive direction after PBS. In addition, Vt shifts more with an
increase in the stress voltage (Vstress). Figure1(b)shows
sub-sequent DVt-log (recovery time) characteristic curves after
these stress conditions with a recovery voltage (Vrecovery) of
0 V. Clearly, Vtrecovers more after PBS at a larger voltage,
with Vt completely recovering at all voltages. Figure 1(c)
shows DVt-time under 500 s PBS and 500 s recovery for
dif-ferent stress voltages and the same recovery voltage (Vrecovery¼ 0 V). Distinctly, in conventional (slow)
measure-ment, there is no significant Vtshift for 500 s PBS and 500 s
recovery. On the contrary, in fast I-V measurement, there is an apparent Vtshift under these operations. This phenomenon
indicates that conventional measurement detects the Vtshift
after complete recovery since integral time is too slow to detect Vt degeneration. Figure 1(d) shows DVt-time with
Vstress¼ Vtþ 1.3 V and Vrecovery¼ 0 V, 0.8 V, 1.6 V under a)
500 s PBS and 500 s recovery over nine cycles. With a rise in Vrecovery, Vt recovery decreases. Moreover, after seven
stress/recovery cycles, Vt entirely recovers in the eighth and
ninth cycles with Vrecovery¼ 0 V. These processes are,
there-fore, indeed reversible and do not cause any degeneration. Hence, these results suggest that Vtshift after PBS is the
con-sequence of the charge/discharge process in pre-existing high-k bulk traps.
Figure 2(a) shows Id-Vg with different Vhigh level and
fixed Vbase level from a fast I-V double sweep measurement
with 30 mV drain voltage. Clearly, reverse sweep Vt
(Vt,reverse sweep) is smaller than forward sweep Vt (Vt,forward sweep). Furthermore, subthreshold swings are similar. Thus,
electrons escape from pre-existing high-k bulk traps to the gate or substrate rather than from interface traps. With an increase in Vhigh level, forward sweep Vt is invariable while
reverse sweep Vt becomes smaller, as well asjDVt,hysteresisj
increasing, as shown in the right and left insets of Fig.2(b), respectively (DVt,hysteresis¼ Vt,reverse sweep- Vt,forward sweep).
Therefore, the higher the Vhigh level, the more electrons escape
from high-k bulk traps. Figure2(b)shows the Ig-Vgcurve at
30C. Obviously, gate current is insignificant since the inter-layer (SiO2) is too thick to tunnel through, resulting in
chan-nel electrons being unable to inject into high-k bulk traps. For the same reason, electrons in high-k bulk traps also cannot escape to the substrate, leading to only one escape route, that
FIG. 1. (a) DVt-log (stress time)
char-acteristic curves under different PBS. (b) DVt-log (recovery time)
character-istic curves after different PBS when Vrecovery¼ 0 V. (c) DVt-time under
500 s PBS and 500 s recovery with dif-ferent stress voltages and the same re-covery voltage (Vrecovery¼ 0 V). (d)
DVt-time with Vstress¼ Vtþ 1.3 V and
Vrecovery¼ 0 V, 0.8 V, 1.6 V under
500 s PBS and 500 s recovery for nine cycles.
FIG. 2. (a) Id-Vgat different Vhigh level
and fixed Vbase levelusing fast I-V
dou-ble sweep measurement with 30 mV drain voltage. (b) Ig-Vgcurve at 30C.
The left inset shows DVt,hysteresis
-Vhigh level. The right inset shows
Vt-Vhigh levelin forward/reverse sweep.
(c) Id-Vgwith fixed Vhigh leveland
differ-ent Vbase level using fast I-V double
sweep measurement. (d) Vt-Vhigh levelin
forward/reverse sweep. The inset shows DVt,hysteresis-Vbase level.
113503-2 Ho et al. Appl. Phys. Lett. 104, 113503 (2014)
same while forward sweep Vt becomes larger, and
jDVt,hysteresisj increases, as shown in Fig.2(d) and its inset,
respectively. Thus, the lower Vbase level, the more electrons
inject into high-k bulk traps. Moreover, only one inject source, the metal gate, offers electrons injecting into high-k bulk traps in Vbase leveldue to the insignificant gate current.
Combining the results above with a previous paper inves-tigating trap energy level distribution in HfO2, which are
0.5 eV, 1 eV, 1.5 eV, 2 eV below conduction band,17 the energy band diagram of the model for charge/discharge elec-trons from high-k bulk traps can be acquired, as shown in Fig. 3. Figures 3(a), 3(c), 3(b), and 3(d) show energy band dia-grams assuming Vbase level¼ 3 V, 0 V and Vhigh level¼ 2 V,
3 V, respectively. Fixed Vbase level and varied Vhigh level are
shown in Figs.3(a),3(b), and 3(d). When Vbase level¼ 3 V,
electrons injecting from metal gate to high-k bulk traps of 1.5 eV and 2 eV energy level attain a steady state, resulting in an invariable forward sweep Vt. Subsequently, a comparison
of Figs.3(b)and3(d)indicates that the higher Vhigh level, the
more electrons escape from bulk traps, leading to a decrease in reverse sweep Vt. For the same reason, varied Vbase level
and fixed Vhigh level are shown in Figs.3(a), 3(c), and 3(d).
When Vhigh level¼ 3 V, electrons escaping from high-k bulk
traps of 1.5 eV and 2 eV energy level to the metal gate attain a steady state, causing no change in reverse sweep Vt. At this
moment when Vhigh level¼ 3 V, these bulk traps are empty.
Next, electrons inject into bulk traps at Vbase level. The lower
Vbase level, the more electrons inject to bulk traps, resulting in
an increase in forward sweep Vt.
To further understand the transient charge and discharge phenomenon, fitting curves are necessary. The formula is expressed below. In a large-area device, discharge rate of carriers in the high-k bulk traps is given by18–20
Qðx; tÞ ¼ qNtðx; 0Þexp t sðxÞ ; (1) DVtðtÞ ¼ Qðx; tÞ CðxÞ dx ¼ ð qNtðx; 0Þ eHK x 1 exp t s xð Þ dx; (2)
where C(x) is the corresponding capacitance for trapped charges located at x from the metal gate/high-k interface to traps and eHK is permittivity for high-k dielectric. The
rela-tionship between tunneling time and distance can be approxi-mated by21,22 sðxÞ ¼ s0expðakxÞ; ak¼ 2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2mHKq/B p h ; (3)
where s0is an electron tunneling characteristic time, mHKis
carrier effective mass for high-k dielectric, and qaB is the
effective tunneling barrier height. Then formula(3)is substi-tuted into formula (2). Because the double exponential exp[t/s(x)] ¼ exp[(t/s0) exp(akx)] in the integrand
changes abruptly from 0 to 1 around x¼ (ak)1ln(t/A), it can
be approximated by a step function written as20
exp t s0 expðakxÞ 0 for x ðakÞ 1 ln t s0 1 for x ðakÞ1ln t s0 : 8 > > > > < > > > > : (4)
Assuming Nt(x,o) uniform distribution and combining
for-mulae(2),(3),(4), DVtcan be acquired by
DVtðtÞ q eHK ð ðakÞ1lnðs0tÞ 0 Ntðx; 0Þxdx ¼ qNt eHK 1 2 1 ak ln t s0 2 : (5)
With derivative of DVtat t, the formula can be described by
dðDVtðtÞÞ dt q eHK 1 ak 1 tNt½ 1 ak lnðt s0 Þ ¼ q eHK 1 ak 1 t½xef fNt: (6) Assuming that the process for electrons discharging from high-k bulk traps near the metal gate is too fast to be detected, the distance (xeff) of high-k bulk traps discharging
electrons contributing to DVtis average. Variable xeffis the
average distance from the metal gate/high-k interface to high-k bulk traps. Next, ln(dVt(t)/dt) can be expressed by
ln dðDVtðtÞÞ dt ð1ÞlnðtÞ þ ln q eHK 1 ak ½xef fNt : (7)
Figures4(a)and4(b)show ln(dVt(t)/dt)-ln(t) fitted by formula
time range is from 104s to 101s for fitting curves. Obviously, the slopes in Figs.4(a)and4(b)are about1 for different stress voltages. This means that carriers are charged and discharged by high-k bulk traps via the tunneling mecha-nism. In addition, the energy levels of these high-k bulk traps are larger than 1 eV. Thus, the charge and discharge path through Frenkel-Poole mechanism can be ruled out. Figures 4(c) and 4(d) show the xeffNt-Vstress fitted curves from the
intercept of Figs.4(a)and4(b)by formula (7). The parameter for fitting curves of electrons escaping from the bulk traps under PBS in Fig.4(c)is mHK,e¼ 0.03m0,23,24eHK¼ 25e0, and
aB,e¼ am,TiN(4.2 eV 4.6 eV) vHfO2(2.55 eV)¼ 1.65 eV–
2.05 eV. am,TiNis assumed to be from about mid-gap (4.6 eV)
to minima of am,TiN(4.2 eV) for n-channel MOSFET.25The
parameter for fitting curves of holes escaping from the bulk traps when Vrecovery¼ 0 V in Fig. 4(d) is mHK,h¼ 0.18m0,26
eHK¼ 25e0, and aB,h¼ Eg(6 eV) aB,e. am,TiN is the metal
work function. vHfO2is the electron affinity in HfO2. aB,eand
aB,hare the effective tunneling barrier height for electron and
hole, respectively. mHK,e and mHK,h are the high-k dielectric
effective mass for electron and hole, respectively. Clearly, with an increase in Vstress, xeffNtincreases. In other words, the
amount of carriers charged and discharged by bulk traps increases. This result conforms to the observations above.
Furthermore, the amount of carriers is about 1 1012cm2–6
1012cm2. According to previous letters,27–29this is reason-able. In addition, Figs.4(c)and4(d)indicate that with a rise in aB,e, aB,h,and mHK, the amount of carriers contributing to DVt
increases. Therefore, the more time for carriers to escape from high-k dielectric, the more carriers can be detected in DVt.
Fig.5(a)shows Id-Vgcurves with different Vhigh levelusing
fast I-V double sweep measurement for the HfO2(3 nm)/
SiO2(1 nm) device (standard performance device) when
Vbase level¼ 0 V. Obviously, with an increase in Vhigh level,
for-ward sweep Vt remains the same while reverse sweep Vt
becomes larger, and DVt,hysteresis increases, as shown in Fig.
5(a)and its inset, respectively. This is because channel elec-trons inject into high-k bulk traps, as shown in previous let-ters.30,31 Fig. 5(b) shows a comparison of DVt,hysteresis
(trising time¼ tfalling time) for different devices with a constant
electric field (Vbase level¼ VFB E1EOT, Vhigh level
¼ VFBþ wsþ E2EOT). trising timeand tfalling timeare rising time
and falling time, respectively. VFB is the flat band voltage.
EOT is the equivalent oxide thickness. E1and E2are electric
fields. wsis surface potential at Vt. The DVt,hysteresisis
insignifi-cant in the SiO2(3 nm) device as the result of there being no
charge/ discharge effect. The DVt,hysteresisis negative in value
in the HfO2(3 nm)/SiO2(3 nm) device due to electrons escaping
FIG. 4. (a) and (b) shows ln(dVt(t)/dt)
-ln(t) fitted by formula (7) from Figs.
1(a) and 1(b); (c) and (d) shows the xeffN-Vstress fitted curves from the
intercept of Figs.4(a)and4(b)by for-mula (7).
FIG. 5. (a) Id-Vgfor different Vhigh level
and fixed Vbase levelfrom fast I-V double
sweep measurement in the HfO2(3 nm)
/SiO2(1 nm) device. The inset shows
DVt,hysteresis Vhigh level. (b) DVt,hysteresis
(trising time¼ tfalling time) in a
compari-son of different devices with constant electric field.
113503-4 Ho et al. Appl. Phys. Lett. 104, 113503 (2014)
ces. In other words, DVt,hysteresisis insignificant in conventional
(slow) measurement as a consequence of DVtalmost wholly
recovering during the measurement, as shown in Fig.1(c). In summary, Vt shifts abnormally in the negative
direc-tion after PBS while using fast I-V measurement due to the electrons’ reversible charge/discharge effect in pre-existing high-k bulk traps. In addition, the direction of Vtshift in I/O
device is contrary to that in the standard performance device since electrons escape from high-k bulk traps to metal gate by the tunneling mechanism in I/O device rather than channel electrons injecting to bulk traps, owing to the large interlayer thickness. According to these results, the charge/discharge effect is reduced with a decrease in pre-existing high-k bulk traps. In previous literature,32,33 the method of Zr doping in HfO2dielectric efficiently reduced high-k bulk traps in
stand-ard performance devices. For this the same reason, the abnor-mal Vtshift of I/O device performed by fast I-V measurement
can be ameliorated by this method.
Part of this work was performed at United Microelectronics Corporation, at National Science Council Core Facilities Laboratory for Science and Nano-Technology in Kaohsiung-Pingtung area, NSYSU Center for Nanoscience and Nanotechnology. The work was supported by the National Science Council of the Republic of China under Contract No. NSC-102-2120-M-110-001.
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