A total standard WIP estimation method for wafer fabrication

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Theory and Methodology

A total standard WIP estimation method for wafer fabrication

Yu-Hsin Lin

a,b,*

_{, Ching-En Lee}

b

a_{Department of Industrial Engineering and Management, Ta Hwa Institute of Technology, Hsin Chu, Taiwan, ROC} b_{Department of Industrial Engineering and Management, National Chiao Tung University, Hsin Chu, Taiwan, ROC}

Received 15 October 1996; accepted 17 October 1999

Abstract

The standard work-in-process (WIP) level in a wafer fabrication factory is an important parameter which can be properly used to trigger the decision of when to release speci®c wafer lots. There are many WIP-based release control policies which have been proven to be eective for wafer fabrication manufacturing, few methods have been proposed to ®nd the suitable WIP-level as a parameter for these release policies. This paper proposes a queueing network-based algorithm to determine the total standard WIP level so that the Fixed-WIP release algorithm to determine the total standard WIP level so that the Fixed-WIP release control policy can apply. A numerical example is provided to elaborate the algorithm. A simulation model of a real-world wafer fabrication factory in Taiwan is built and analyzed. Results of simulation experiment indicate that under the Fixed-WIP control policy, the total standard WIP level es-timated from this study achieves a target throughput rate while keeping the corresponding cycle time relatively low. Results also demonstrate that the queueing network-based algorithm is a very useful method to determine the standard WIP level eciently. Ó 2001 Elsevier Science B.V. All rights reserved.

Keywords: Wafer release; Fixed-WIP; Total standard WIP level; Queueing network theory

1. Introduction

Semiconductor manufacturing is probably the most complex manufacturing process in the world. The semiconductor manufacturing process is a multistage process which transfers silicon in the form of thin, polished disk into integrated circuits. The entire process basically includes four main

steps: raw wafer manufacturing, wafer fabrication, probe and die, package and test (Miller, 1990). The wafer fabrication is most time-consuming and complicated one, consisting primarily of at least six major types of phases: Diusion, Lithography, CVD, Thin Film, Etching and Ion Implantation. The wafer passes through these six major phases numerous times. The ¯ow time (cycle time) of a wafer piece is typically 30±45 days. The entire fabrication process involves hundreds of operation steps performed on a variety of machines. Wafers are grouped in lots and transferred in a standard cassette. A wafer must visit some machine groups

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*_{Corresponding author. Tel.: 72673; fax:}

+886-35-722392.

E-mail address: bghlin@msl9.hinet.net (Y.-H. Lin).

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more than once. This is known as a reentrant process. For instance, a wafer may have to visit the photolithography machine 9±25 times for all layers of circuitry to be fabricated. Owing to the com-plexity of the wafer fabrication process, wafer re-lease and dispatching decisions are extremely dicult to achieve. In addition, the cycle time is dicult to make.

The maximization of critical resource utiliza-tion as well as throughput rate and the minimi-zation of cycle time are the primary goals of the release and dispatching policy in wafer fabrication because of its capital-intensive nature and the need to attain a competitive advantage. Goldratt and Cox (1986) recognized that the workstation with the lowest capacity (bottleneck) often governs the production rate of the entire manufacturing line. Thus, it is crucially important in wafer fabrication to maximize the bottleneck workstation's utiliza-tion to achieve high throughput rate while main-taining reasonable cycle time. However, the WIP level in the system aects both the cycle time and the throughput (Miller, 1990). WIP and cycle time are convex increasing functions of throughput. In®nite WIP level maximizes throughput which cannot exceed capacity of the bottleneck work-station (Buzacott, 1971). Queueing theory (Gross and Harris, 1974) has shown that minimal WIP levels produce the minimal cycle time in the steady state. The inherent con¯ict in the determination of a proper WIP level is obvious when attempting to both maximize throughput and minimize cycle time. The proper management of WIP level is critical to the success of manufacturing operations (Enns, 1995). It can regulate the material ¯ow, make full use of bottleneck capacity, and act as a valuable parameter for wafer release control.

Simulation studies indicate that the wafer re-lease mechanism has a stronger impact on system performance than the dispatching rule (Glassey and Resende, 1988a,b; Wein, 1988; Miller, 1990). Therefore, most researchers and practitioners in wafer fabrication focus primarily on wafer release control strategies. The wafer release control policy can be classi®ed as closed-loop and open-loop. The closed-loop control policy is generally better than the open-loop one (Miller, 1990). The idea of the closed-loop control policy is to keep an

opti-mal WIP level (i.e. workload) in the factory. The wafer release decisions will then be made accord-ing to the discrepancy between the actual and projected WIP levels (Graves et al., 1995). Star-vation avoidance (SA) (Glassey and Resende, 1988a,b), Workload Regulating (WR) (Wein, 1988), Two-Boundary (TB) (Lou, 1989; Lou and Kager, 1989; Yan et al., 1996), CONWIP (Spear-man et al., 1989, Spear(Spear-man and Zazanis, 1992), Fixed-WIP (Burman et al., 1986; Glassey and Resende, 1988a,b; Lozinski and Glassey, 1988; Wein, 1988; Roderick et al., 1992), and Load-Oriented order release (Bechte, 1988a,b, 1994; Wiendahl et al., 1992; Wiendahl, 1995) are several well-known closed-loop control policies. The WIP level in a closed-loop control policy can be de®ned as either the total WIP in the system or the WIP level between two speci®c operation steps (Huang, 1995). In this paper, the WIP level is de®ned as the former one. Although the WIP level is crucial to wafer fabrication releasing decisions, few methods have been proposed to ®nd the suitable WIP amount.

Miller (1990) used simulation to determine the number of lots in a fabrication line under Fixed-WIP control policy. He pointed out that a simu-lation model was applicable to a speci®c system only to the extent that the features it contained adequately represented that system, and it was time-consuming to run a simulation model. Fur-thermore, simulation models can take a long time to build and debug (Suri et al., 1995). It is im-portant to recognize that simulation model con-struction is only just in case for a speci®c system. Applying the model hinges on the de®nition of simulation objectives, the availability and accuracy of data and assumptions, the veri®cation and validation of the model for the speci®c system under study, and the analysis and interpretation of simulation results (Miller, 1990).

Queueing network model has been proven to be useful to analyze the performance of complex systems (Whitt, 1983). Burman et al. (1986) de-veloped a queueing network model for ICmanu-facturing processes. He found that the performance measures (WIP and throughput time) of the queueing network model deviated by 7±20% from those of the simulation model, but the run

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times were only one-tenth of that of the simula-tions. Chen et al. (1988) also constructed a simple queueing network model to predict speci®c key system performance measures. His modeling ap-proach is the use of a mixed network model, composed of a serial of M/M/1 queues and closed with respect to non-monitor lots, in which the Fixed-WIP level is viewed as a design parameter and the throughput rate is viewed as a perfor-mance characteristic. The values predicted by his model were found to be within about 10% of those actually observed. He concluded that queueing network models could provide a useful quantita-tive guidance to designers in wafer fabrication factories. In fact, the queueing network-based method is ecient to estimate a wider range of manufacturing parameters, such as WIP level, and it can answer questions accurately and quickly under some conditions and ignore certain details of the manufacturing system (Burman et al., 1986; Askin and Standrige, 1993; Suri, 1995; Connors et al., 1996). According to studies by Suri et al. (1995), faculty members of US and European business schools agreed that the queueing-based approach was more ecient that simulation. Therefore, this paper proposes a queueing net-work-based algorithm to determine the total standard WIP level so that the Fixed-WIP release control policy can apply.

The production planner and the manufacturing engineer can monitor and control the WIP level and trigger the wafer release decision at the right time by using the estimated WIP level information. If the total WIP level falls below the de®ned standard WIP level, wafers must be released into the factory to avoid the bottleneck from starvation and keep the target throughput rate to be satis®ed. The WIP level estimated by the proposed method herein and the corresponding wafer release control mechanism can achieve target throughput rate with a reasonable cycle time. To validate the re-sult, a simulation model with real factory data (actual average processing times and routings) is experimented.

The remainder of this paper is organized as follows. Section 2 describes assumptions of the proposed method. Section 3 illustrates the stan-dard WIP level estimating model. A numerical

example is then given. In Section 4, a simulation model is built and results of simulation experiment are presented. Conclusions of this study are con-tained in Section 5.

2. Model assumptions

In this paper, a queueing network model to es-timate the total standard WIP level in the wafer fabrication factory is developed. Some transfor-mations and assumptions are made to suit the ap-plication to the queueing network. In the next two subsections, the corresponding transformations and assumptions will be discussed, respectively. 2.1. Processing time estimation

Wafers generally move through machines in lots in a wafer fabrication factory. The operational batch sizes range from a single wafer to several lots. Processing times depend mainly on the op-eration types. For lot splitting opop-erations, such as photolithography, the processing time depends on the number of wafers in a lot. For batch opera-tions, such as diusion, no matter how many lots are loaded at a time (the number of lots batched must be smaller than the maximal batch size which is usually 6), the processing time generally does not vary with the number of lots batched.

The batch operation plays an important role in semiconductor manufacturing processes and have attracted many researches (Glassey and Weng, 1991; Fowler et al., 1992; Gurnani et al., 1992; Weng and Leachman, 1993; Robinson et al., 1995). A lot of researches (Neuts, 1967; Medhi, 1975) on batch operations use exponential services for computational tractability although the service time of batch operation may not be really dis-tributed by an exponential. A single lot processing time is assumed in our queueing network model. For simplicity, the average processing time of a single lot at batch-type operation is estimated by dividing the processing time of a batch operation by its average batch sizes and is assumed expo-nential distributed.

The information of PM (preventive mainte-nance) duration, PM interval, machine breakdown

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duration, and machine breakdown interval have a signi®cant in¯uence in the cycle time estimation (Uzsoy et al., 1992). To more adequately estimate the processing time of a single lot, these interrup-tions have to be included. To do so, we assume that the service time at a machine is the summation of its actual processing time and the average du-ration of breakdowns and PMs that occur within the speci®c service. We de®ned it as the ``eective service time'', the same name as de®ned by Chen et al. (1988). The eective service time will be ap-plied to the queueing network model as the service time of each machine.

The eective service time of workstation j ESTj is de®ned as

mj1 Dd=Dn Pd=Pm; 1

in which mj is the average processing time of a

single lot in workstation j which does not include machine breakdowns and PMs; Dn the average

time interval between machine breakdowns (mean time between failure, MTBF); Dd the average

du-ration of machine breakdowns (mean time to re-pair, MTTR); Pmthe average time interval between

machine PMs (mean time between PM, MTBPM); Pd is the average duration of machine PMs (mean

time to ®nish a PM, MTTPM).

The ESTj represents the long-run average

ser-vice time of workstation j. The ESTj may not

necessarily be consistent with an assumption of exponentiality, one still gets a good approximation (Chen et al., 1988). Such a system, the eective service time is applied, can be revised as an equivalent network without service interruptions (Vinod and Altiok, 1986; Chen et al., 1988). Other relevant assumptions will be described in the next section.

2.2. General assumptions

We assume that each product type has its own distinct ®xed route. Each route comprises several workstations. Each workstation may contain one to several machines. The average processing time of each machine in a speci®c workstation is

as-sumed the same and is exponentially distributed. The ®rst-in-®rst-out (FIFO) discipline is assumed at each workstation.

In building a queueing network model for the wafer fabrication factory, each wafer lot is de-®ned as an arriving customer and each worksta-tion is viewed as a single or multi-server in the model. Because the studied case is a new factory, the service time variability at each workstation is relatively large. Therefore, each workstation is thought of as an M/M/S model. The entire fac-tory therefore comprises a network of M/M/S queues. The bottleneck workstation, which will be de®ned in the next section, dominates the activi-ties of other workstations. M/M/S queues of non-bottleneck workstations are independent of each other. Sucient capacity is available to complete the arriving wafers at each workstation. That is, it is assumed that the service rate is greater than the arrival rate. Finite queues exist at the steady state.

3. Standard WIP level estimating model

One of the most important features of this model is to apply the concept of ``the bottle-neck workstation controls the throughput rate'' (Goldratt and Cox, 1986). We treat the through-put rate, a, as a design parameter. In fact, the throughput rate (wafer out rate) is a very im-portant production target which needs to be set and reviewed periodically by production control department in any wafer fabrication factories according to their rated capacity. After setting the target throughput rate, the arrival rate of the bottleneck workstation can be determined by means of multiplying the throughput rate of each individual product with the corresponding num-ber of times that the bottleneck workstation is visited. The entire wafer fabrication route can be viewed as a virtual route ¯ow illustrated in Fig. 1. As shown in Fig. 1, the wafer fabrication route is divided into loops based on the bottleneck workstation. The bottleneck workstation is viewed as the starting point in each loop. The wafers ¯ow through the bottleneck workstation and enter the next routing loop and the next until

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they ®nish their operations. That is, the entire wafer fabrication routing is composed of a series of virtual loops. The number of loops that a product requires depends on the number of times that the bottleneck workstation is visited by that speci®c product. Every loop of a product is un-ique. There are some operation steps between the wafer start and the ®rst visiting of the bottleneck workstation. The ending operation step of the last loop of each product is wafer out. Since the wafer ¯ow is controlled by the bottleneck work-station, the bottleneck workstation acts like a wafer distribution center. A wafer lot is distrib-uted into a speci®c process loop through the bottleneck workstation.

Although there are many WIP-based release control policies which have been proven to be ef-fective (Bertrand and Wortmann, 1981; Glassey and Resende, 1988a,b; Wein, 1988; Spearman et al., 1989; Lou, 1989; Lou and Kager, 1989; Graves et al., 1995; Yan et al., 1996) for wafer fabrication, few methods have been proposed to ®nd the suitable WIP-level as a parameter for those policies. Among those lot release control policies, Fixed-WIP is a simple but very eective control mechanism in reducing cycle time and increasing mean throughput rate (Wein, 1988; Miller, 1990; Roderick et al., 1992). Simulation software packages (e.g. Autoched, Mansim, and Pacemaker etc.) are common tools to determine the WIP levels in practice. However, it is

time-consuming and case speci®c as discussed in Section 1. There are many queueing network-based software packages like CAN-Q (Suri et al., 1995), QNA (Whitt, 1983), and PANACEA (Ramakrishnan et al., 1982) etc. in a number of applications. However, their applications in semiconductor manufacturing are very few. It is the objective of this research to propose a queueing network-based algorithm to determine the total standard WIP level so that the Fixed-WIP release control policy can apply. The wafer release decisions are made in accordance with the total WIP level. Wafer lots are released into the factory when the actual WIP level drops below the estimated standard WIP level. Because the number of operations from the wafer start to the ®rst visiting of the bottleneck workstation are relatively few, these operation steps are not considered in our WIP estimation model. 3.1. Heuristic algorithm

The proposed algorithm is throughput-rate and bottleneck oriented. The total standard WIP level is calculated by summarizing each individual workstation`s queue. As mentioned in Section 2.2, each individual workstation can be treated as an M/M/S model. According to Gross and Harris (1974) to calculate the WIP level of each machine the information of arrival rates, service rates, and the number of workstations is needed. Because the performance of a bottleneck workstation is much more important than that of others and the entire throughput rate is determined by bottleneck workstation, the WIP in front of the bottleneck workstation is determined ®rst. The WIPs of non-bottleneck workstations will be derived according to the equivalence property and Jackson's network (Jackson, 1963).

In order to clearly describe the proposed al-gorithm, the following indexes are de®ned ®rst. The bottleneck workstation is indexed by B, the non-bottleneck workstations by K, the product types by i, and the loops by l. The standard WIP level of the entire factory is represented by std WIP and the corresponding de®nitions are given below.

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The heuristic algorithm is divided into eight steps. First of all, the bottleneck workstation have to be identi®ed. APICS (1992) indicates that the bottleneck workstation can be de®ned as ``a same function of the machine group whose capacity is equal to or less than the demand placed on it''. In this paper, the bottleneck workstation is de®ned as the one with the average greatest loading of an aggregate lot place on it. The ¯ow chart of the heuristic method is illustrated in Fig. 2 and its detail is elaborated thereafter.

Step 1: Calculating the average throughput rate of each product type i by multiplying the average overall throughput rate a and the product mix ratios Di:

ai a Di: 2

Step 2: Computing the expected average arrival rate, kiB, of product type i visiting the bottleneck

workstation based on the projected average throughput rate of product type i:

kiB ai NiB: 3

Summarizing the average arrival rates of all product type i visiting the bottleneck workstation to get the average arrival rate, kB, of all products

visiting the bottleneck workstation: kB

X

i

kiB: 4

a overall average throughput rate of the factory. It is expressed in lots per hours ai average throughput rate at which lots of

product type i are processed through the factory

Di fraction of product type i processed through

the factory

kj average number of lots visit workstation j

per hour

lj eective service rate per machine at

work-station j, that is the average number of lots completed per hour

Sj number of machine at workstation j

Wj average WIP level in from of workstation j,

including the processing wafer lot

NiB number of visits to bottleneck workstation

B by product type i

Ni number of loops for product type i;

Ni NiB

Pijk number of visits to non-bottleneck

work-station K in loop l of product type i R0

il probability of entering the loop l of product

type i when ®nishing the operation at the bottleneck workstation

ROil output rate of the bottleneck workstation to

loop l of product type i when ®nishing the operation at the bottleneck workstation

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Step 3: Applying the queueing theory (Gross and Harris, 1974) to compute the WIP level in front of the bottleneck workstation, WB:

WB LBk_lB B P0kB=lBSBkB=SB lB SB!1 kB=SB lB2 k_lB B; 5 where P0 1 PSB 1 n0 kB=lBn=n! kB=lBSB=SB! 1 kB=SB lB 1 :

Step 4: Computing the probability R0

il; For a

speci®c product type i, it is assumed that the probability of entering each loop l from the bot-tleneck is the same and the fraction is 1=Ni. The

probability R0

ils for loops l of a product type i are

independent of each other and can be represented as follows: R0 il PDi Ni j Dj Nj _N1 j Di P jDj Nj : 6 Step 5: Calculating the product type i's output rate at the bottleneck workstation to loop l ac-cording to the probability R0

il and kB:

ROil R0il kB: 7

Step 6: Calculating the anticipated arrival rate, kK, of non-bottleneck workstation K. For a

spe-ci®c product type i, the output rate at the bottle-neck workstation to loop l ROil is equal to the

arrival rate of loop l. In loop l of product type i, the non-bottleneck workstation K may be visited several times Pilk. Thus, the average arrival rate

at non-bottleneck workstation K in the loop l of product type i is derived from multiplying the av-erage arrival rate at non-bottleneck workstation K by the corresponding number of times that it is visited. By summarizing the arrival rates of all products at non-bottleneck workstation K in each loop, the anticipated arrival rate, kK, at

non-bot-tleneck workstation K can be derived:

kK X i X l ROil PilK: 8

Step 7: Applying Eq. (5) in step 3 to compute the WIP levels in front of all non-bottleneck workstations K; WK:

Step 8: Summarizing the WIP levels in front of all workstations j to get the total standard WIP level of the entire factory

std WIP X

j

Wj: 9

3.2. Numerical case

In this section, a wafer fabrication factory of a global company is analyzed. This is a new factory located in the Science Based Industrial Park in Taiwan. In the beginning stage of their manufac-turing, ®ve major types of products: A, B, C, D, and E are focused on to be analyzed. The product mixes are 15.71%, 16.67%, 4.76%, 34.76%, and 28.01%, respectively. Each product type has its own distinct route. Each route is composed of 218±315 operation steps. Moreover, these opera-tion steps are performed on 60 kinds of worksta-tions. Tables 1 and 2 give the average processing time of a single lot, PM information, and break-down information on each type of workstation. The average processing times, PM, and break-down information are gathered from the real fac-tory. The eective service time of workstation is derived from Eq. (1) and is given in Table 1.

The recently established wafer fabrication fac-tory sets an initial production target (throughput rate) of 318 lots per month. Each lot contains 25 pieces of wafers. The daily mean throughput rate is equal to 10.6 lots (318 lots=month 30 days/ month 10.6 lots/day). According to the pro-posed algorithm, the bottleneck workstation has to be identi®ed ®rst. The rough-cut capacity esti-mation method is used to compute the average loads of an aggregate wafer lot place on worksta-tions, which do not consider the timing of lot re-leasing. The workstation number 25 is identi®ed as the bottleneck (see Table 3).

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According to the algorithm presented in Sec-tion 3.1, the average throughput rate of each product type i; ai, is calculated ®rst. The

throughput rates of ®ve product types are 1.665, 1.767, 0.505, 3.685, and 2.979 lots per day corre-sponding to products A, B, C, D, and E, respec-tively. The expected average arrival rates, kiB, of

each product type i visiting the bottleneck work-station can be derived. Because the number of times that product types A±E visit the bottleneck workstation are 11, 8, 7, 10, and 9, the average arrival rates of products A±E visit the bottleneck workstation are 18.315 1:665 11, 14:136 1:7678; 3:5350:5057; 36:8503:68510, and 26:8112:9799 lots per day. Thus, the average arrival rate of all products to visit the bottleneck workstation is 99.647 lots per day. This expected value shows that the production target (10.6 lots per day) will be reached if the average arrival rate at the bottleneck workstation is 4.152 lots per hour (Table 5).

In step 4, the probability R0

ils are determined

and shown in Table 4. Through steps 5 and 6, the

anticipated arrival rate at each workstation is de-rived and is given in Table 5. By summarizing the WIP levels in front of all workstations, presented in Table 6, the total standard WIP (145 lots) is estimated.

In the next section, a simulation model apply-ing Fixed-WIP lot release policy and simulation experiment is designed to demonstrate how the derived standard WIP level performs well.

4. Simulation experiment

The most common modelling technique in semiconductor manufacturing is simulation (Day-ho and Atherton, 1984; Atherton and Day(Day-ho, 1986; Burman et al., 1986; Miller, 1990; Glassey and Resende, 1988a,b; Wein, 1988). Thus, a sim-ulation model is adopted to analyze the eective-ness of the standard WIP level determined through the proposed algorithm under the Fixed-WIP lot release policy.

Table 1

The average and eective processing time of a single lota

Workstation j 1 2 3 ₄ ₅ ₆ ₇ ₈ ₉ ₁₀ APTj(min/lot) 10.00 10.00 10.00 60.00 35.00 46.96 6.25 38.92 60.00 12.50 ESTj(min/lot) 10.99 10.87 10.10 60.61 58.33 47.43 6.94 40.97 81.08 13.16 Workstation j 11 12 13 14 15 16 17 18 19 20 APTj(min/lot) 25.34 31.00 27.64 60.00 15.00 10.00 65.02 20.67 30.00 62.98 ESTj(min/lot) 25.60 31.31 30.38 60.61 15.15 10.10 75.61 30.40 30.30 71.57 Workstation j ₂₁ ₂₂ ₂₃ ₂₄ ₂₅ ₂₆ ₂₇ ₂₈ ₂₉ ₃₀ APTj(min/lot) 86.86 10.67 10.00 10.00 40.00 3.00 57.35 74.06 90.00 53.47 ESTj(min/lot) 105.92 14.22 10.10 10.10 41.67 3.03 63.72 77.96 93.75 62.18 Workstation j ₃₁ ₃₂ ₃₃ ₃₄ ₃₅ ₃₆ ₃₇ ₃₈ ₃₉ ₄₀ APTj(min/lot) 10.02 63.63 22.01 13.25 10.90 12.65 8.77 10.00 84.41 25.00 ESTj(min/lot) 11.51 69.93 22.23 17.21 13.80 13.04 10.20 10.10 88.85 26.32 Workstation j 41 42 43 44 ₄₅ ₄₆ ₄₇ ₄₈ ₄₉ ₅₀ APTj(min/lot) 25.00 25.00 10.00 10.00 66.75 42.22 49.51 17.05 73.76 100.00 ESTj(min/lot) 27.17 25.25 10.10 10.53 87.83 46.40 50.01 17.86 99.68 109.89 Workstation j ₅₁ ₅₂ ₅₃ ₅₄ ₅₅ ₅₆ ₅₇ ₅₈ ₅₉ ₆₀ APTj(min/lot) 57.11 67.79 10.00 55.00 55.00 120.00 200.00 15.00 40.91 57.19 ESTj(min/lot) 62.08 68.47 10.10 58.51 67.90 121.21 235.29 15.15 54.55 61.50 a_APT

jrepresents the average processing time of a single lot at workstation j which does not include machine breakdowns and PMs;

ESTjrepresents the eective service time of a single lot at workstation j; * represent batching process workstations. The average batch

size of workstation number 4, 7, 21, 22, 45, 59, and 60 is 2 lots; the average batch size of workstation number 8, 10, 32, 47, 50, 51, and 57 is 3 lots; the average batch size of workstation number 31, 34, 35 and 36 is 4 lots.

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4.1. Simulation model descriptions

Because the studied wafer fab is newly installed, the service time variability at each workstation is relatively large. Therefore, the exponential distri-bution is also assumed. In the simulation model, real average processing time as an exponential distribution's mean at each workstation for a speci®c product is applied. As indicated in Section 1, the WIP level in a system aects both cycle time and throughput rate (Miller, 1990). There is in-herent con¯ict in WIP level decisions when at-tempting to both maximize throughput and minimize cycle time. Therefore, simulation exper-iments are designed to analyze throughput rate and cycle time performance under dierent WIP

levels, represented by times of total standard WIP level estimated from our proposed algorithm. Ten experiments for dierent WIP levels

0:5 std WIP; 0:6 std WIP; 0:7 std WIP; 0:8 std WIP; 0:9 std WIP; 1:0 std WIP; 1:1 std WIP; 1:2 std WIP; 1:3 std WIP; 1:4 std WIP

are experimented. The lot release mechanism is Fixed-WIP and the lot dispatching rule is FIFO. The wafer lot to be released is randomly generated according to the product mix ratio. The batching

Table 2

The PM and breakdown information of workstations

Workstations 1 2 3 4 5 6 7 8 9 10 Pd(h) 158 17,520 17,520 17,520 10 17,520 17,520 90 14 17,520 Pm(h) 0.30 1.00 1.00 1.00 3.45 1.00 1.00 3.30 2.75 1.00 Dd(h) 55 325 500 300 10 185 98 156 20 40 Dn(h) 5.33 28.35 5.05 10.00 3.22 1.83 10.83 2.48 3.10 2.10 Workstations 11 12 13 14 15 16 17 18 19 20 Pd(h) 17,520 16,520 75 17,520 200 17,520 62 12 75 183 Pm(h) 0.15 0.50 1.00 1.00 1.00 1.00 10.90 3.10 0.50 3.00 Dd(h) 140 190 70 300 200 500 590 15 75 25 Dn(h) 1.42 1.90 6.00 3.03 1.00 5.05 1.40 3.20 0.25 3.00 Workstations 21 22 23 24 25 26 27 28 29 30 Pd(h) 55 6 17,520 17,520 163 420 79 114 130 23 Pm(h) 6.86 1.51 1.00 1.00 1.50 2.00 5.00 3.00 2.57 1.00 Dd(h) 37 30 500 500 46 420 69 190 104 36 Dn(h) 3.50 2.43 5.05 5.05 1.50 2.00 3.30 5.00 2.28 3.60 Workstations 31 32 33 34 35 36 37 38 39 40 Pd(h) 20 64 12,520 21 10 600 16 17,520 34 115 Pm(h) 1.33 4.86 1.50 1.50 1.21 1.50 2.00 1.00 0.90 0.30 Dd(h) 30 156 150 104 35 95 60 500 312 100 Dn(h) 2.50 3.60 1.50 23.67 5.00 2.70 2.27 1.00 6.60 5.00 Workstations 41 42 43 44 45 46 47 48 49 50 Pd(h) 17 290 17,520 40 11 150 1250 95 15 42 Pm(h) 1.00 1.00 1.00 1.10 2.80 1.10 1.00 1.00 2.54 3.00 Dd(h) 69 300 500 40 65 120 320 100 69 109 Dn(h) 1.80 2.00 1.00 1.00 4.00 11.00 3.00 1.00 3.45 3.00 Workstations 51 52 53 54 55 56 57 58 59 60 Pd(h) 61 600 17,520 14 25 240 39 85 12 90 Pm(h) 5.00 3.00 1.00 0.85 2.60 1.20 6.10 0.50 3.00 2.00 Dd(h) 195 600 500 650 50 235 70 85 24 48 Dn(h) 1.00 3.00 1.00 25.00 6.46 1.20 1.40 0.33 1.90 2.55

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operations in diusion, etching, thin ®lm, and ion implant areas are also implemented in this simu-lation model, although a single lot operation is assumed in our queueing network model, to ap-proach the real wafer fabrication process.

The performance measures, average through-put rate and cycle time, are compared under these 10 simulation experiments. Ten simulation runs are made for each experimental WIP level. Com-mon random number streams, one of the

variance-Table 3

The average loading of each workstationa

Workstations 1 2 3 4 5 6 7 8 9 10 Number of machines 1 3 4 1 2 3 4 1 1 2 T_load (min) 82.99 177.28 174.84 60.61 175.00 300.39 12.00 104.36 81.08 165.79 A_load (min) 82.99 59.09 58.28 60.61 87.50 100.13 6.00 104.36 81.08 82.89 Workstations 11 12 13 14 15 16 17 18 19 20 Number of machines 3 1 3 2 1 1 2 2 2 5 T_load (min) 218.12 71.73 259.49 181.82 90.77 50.51 226.82 163.71 80.95 556.06 A_load (min) 72.71 71.73 86.50 90.91 90.77 50.51 113.41 81.82 40.48 111.21 Workstations 21 22 23 24 25 26 27 28 29 30 Number of machines 2 2 3 2 3 1 2 3 2 2 T_load (min) 204.54 130.11 10.10 172.68 355.95 42.56 180.69 122.20 234.84 170.09 A_load (min) 102.27 65.05 3.37 86.34 118.65 42.56 90.35 40.73 117.42 85.04 Workstations 31 32 33 34 35 36 37 38 39 40 Number of machines 1 2 2 2 1 1 1 1 2 1 T_load (min) 31.31 147.31 197.98 54.24 21.35 61.27 46.55 17.94 106.54 99.76 A_load (min) 31.31 73.66 98.99 27.14 21.35 61.27 46.55 17.94 53.27 99.76 Workstations 41 42 43 44 45 46 47 48 49 50 Number of machines 2 1 2 2 1 2 2 1 3 2 T_load (min) 69.36 108.94 55.17 79.50 87.83 90.37 97.42 66.24 276.74 61.75 A_load (min) 34.68 108.94 27.59 39.75 87.83 45.19 48.71 66.24 92.25 30.87 Workstations 51 52 53 54 55 56 57 58 59 60 Number of machines 2 2 1 1 1 1 2 1 1 2 T_load (min) 230.88 196.29 40.88 42.07 3.23 5.77 235.29 30.30 39.22 130.60 A_load (min) 115.44 98.15 40.88 42.07 3.23 5.77 117.65 30.30 39.22 65.30

a_{T_load: represents the average loading of a single lot placed at a workstation. A_load: represents the average loading of each}

machine. Workstation 25 is the identi®ed bottleneck at those cells with values given in italics.

Table 4 The probability R0 ilof product A, B, C, D and E Loops 1 2 3 4 5 6 7 8 9 10 11 Product A 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 Product B 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 Product C0.0051 0.0051 0.0051 0.0051 0.0051 0.0051 0.0051 Product D 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 Product E 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299

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reduction techniques (Law and Kelton, 1991), are used. In each simulation run, 365 days were sim-ulated and the throughput rate and cycle time were collected. Startup statistics were discarded for the ®rst 265-day warm-up period to minimize the po-tential startup bias. Data was then collected for the rest of 100 additional days.

4.2. Experimental design

As described in the previous section, simulation experiments are designed to analyze the line per-formance under dierent standard WIP levels. A

total of 10 distinct WIP level cases are tested, varying the number of WIP lots in the factory from 50% of standard WIP level to 140% of standard WIP level. Each WIP level is simulated to observe the average throughput rate and cycle time of the factory. It takes 13±23 hours in general, depending on the amount of WIP level in the system, to run a simulation experiment on a Pen-tium-133 PC. Hypothesis tests are conducted for the dierences on average throughput rates and cycle times among these 10 WIP levels. 45 10 9 2 paired t-tests are conducted for each of the two performance measures. The results are presented in the next section.

Table 6

The WIP levels in front of each workstation

Workstation j 1 2 3 4 5 6 7 8 9 10 Wj(lots) 1.256 1.491 1.461 0.804 2.195 4.555 0.074 3.098 1.476 2.248 Workstation j 11 12 13 14 15 16 17 18 19 20 Wj(lots) 1.878 1.054 3.248 2.417 9.716 0.287 1.609 2.010 0.690 5.692 Workstation j 21 22 23 24 25 26 27 28 29 30 Wj(lots) 2.612 1.345 0.074 1.963 25.089 0.396 2.373 1.183 10.471 1.672 Workstation j 31 32 33 34 35 36 37 38 39 40 Wj(lots) 0.333 2.348 3.292 0.394 0.221 0.810 0.560 0.135 1.064 2.047 Workstation j 41 42 43 44 45 46 47 48 49 50 Wj(lots) 0.462 1.427 0.381 0.574 1.823 0.606 0.662 0.792 2.604 0.706 Workstation j 51 52 53 54 55 56 57 58 59 60 Wj(lots) 9.683 2.149 0.447 0.694 0.085 0.163 12.647 0.125 1.216 1.756 Table 5

The arrival rates of each workstation

Workstation j 1 2 3 4 5 6 7 8 9 10 kj(lots/h) 3.040 7.409 7.850 0.441 1.323 2.996 0.637 1.107 0.441 5.924 Workstation j 11 12 13 14 15 16 17 18 19 20 kj(lots/h) 3.706 0.983 4.147 1.323 2.693 1.323 0.882 2.445 1.233 3.262 Workstation j 21 22 23 24 25 26 27 28 29 30 kj(lots/h) 0.779 4.241 0.441 7.281 4.152 5.613 1.250 0.857 0.901 1.094 Workstation j 31 32 33 34 35 36 37 38 39 40 kj(lots/h) 1.302 1.134 4.002 1.323 0.788 2.059 2.111 0.706 0.584 1.531 Workstation j 41 42 43 44 45 46 47 48 49 50 kj(lots/h) 0.970 1.397 2.187 3.040 0.441 0.723 0.723 1.485 1.147 0.347 Workstation j 51 52 53 54 55 56 57 58 59 60 kj(lots/h) 1.744 1.118 1.834 0.420 0.069 0.069 0.441 0.441 0.420 1.134

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4.3. Analysis results

4.3.1. Analysis of mean throughput rate, cycle time and standard deviation of cycle time

Results (p < 0:0001) of ANOVA indicate that signi®cant distinction exist in the performance of WIP levels with respect to mean throughout rate, mean and standard deviation cycle time at a 0:05. A Dunce's multiple test (Kirk, 1982) is then conducted on the WIP levels and results are presented in Tables 7±9 for mean throughput rate, mean cycle time, and standard deviation of cycle time at a 0:05, respectively. According to Table 7, no signi®cant dierences arise in mean throughput rates at WIP levels of 1:1 std WIP; 1:2 std WIP; 1:3 std WIP and 1:4 std WIP. Although the mean throughput rate at the 1:0 std WIP falls in Duncan Group B, the

highest percentage improved over that of 1:0 std WIP is 1.69%. However, when the WIP levels are below 1:0 std WIP, the mean throughput rates are signi®cantly smaller than the mean throughput rate at 1:0 std WIP and above. Table 7 and Fig. 3 reveal that as the WIP level drops further from 1:0 std WIP, the per-centage lost in mean throughput rate becomes faster (from 3.01% decrease at 0:9 std WIP to 40.54% decrease at 0:5 std WIP).

When WIP levels are at and below the standard WIP level, their corresponding mean cycle times are signi®cantly smaller than those of the above (see Table 8 and Fig. 3). The higher the WIP level is, the longer the mean cycle time presents. As the WIP level exceeds 1:0 std WIP, the percentage increased in mean cycle time over 1:0 std WIP ranges from 8.85% to 37.80%. Little's results

Table 7

Duncan's multiple range test results for daily mean throughput rate

WIP levels N (replications) Mean (days) Duncan grouping % Improvement in mean TP (over 1.0 std_WIP) 1:4 std WIP 10 11.068 A 1.69 1:3 std WIP 10 11.048 A 1.51 1:2 std WIP 10 11.028 A 1.32 1:1 std WIP 10 11.036 A 1.40 1:0 std WIP 10 10.884 B ± 0:9 std WIP 10 10.556 C 3.01 0:8 std WIP 10 9.912 D 8.93 0:7 std WIP 10 8.952 E 17.75 0:6 std WIP 10 7.840 F 27.97 0:5 std WIP 10 6.500 G 40.54 Table 8

Duncan's multiple range test results for daily mean cycle time

WIP levels N (replications) Mean (lots/day) Duncan grouping % improvement in mean CT (over 1.0 std_WIP) 1:4 std WIP 10 18.226 A 37.80 1:3 std WIP 10 16.964 B 28.26 1:2 std WIP 10 15.646 C 18.30 1:1 std WIP 10 14.396 D 8.85 1:0 std WIP 10 13.226 E ± 0:9 std WIP 10 12.386 F 6.35 0:8 std WIP 10 11.656 G 11.87 0:7 std WIP 10 11.342 H 14.24 0:6 std WIP 10 11.084 I 16.20 0:5 std WIP 10 11.262 H 14.85

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(Gross and Harris, 1974) suggest that the linear model should exist between mean cycle time and WIP for the region of WIP std WIP. A F -test (Montgomery and Peck, 1992) is made. It is found that the F -ratio ( 7821.139) is greater than F0:05; 1; 5 6061. Therefore, the result of this study

con®rms to Little's results.

For WIP levels exceeding 1:0 std WIP, as indicated above, the highest percentage improved in mean throughput rate over that at 1:0 std

WIP is only 1.69%. Meanwhile, it may pay up to 37.80% increase in mean cycle time, which is not worth it. Moreover, Table 9 demonstrates that the standard deviation of cycle time at the standard WIP level is signi®cantly smaller than those at 1:1 std WIP and above. This ®nding suggests that those the derived standard WIP level (1:0 std WIP) is more robust in cycle time per-formance than higher WIP-level situations which may therefore result in a better order promising performance. For WIP levels below 1:0 std WIP, their reductions on mean cycle times cannot compensate for the loss of mean throughput rate and the loss of expensive capacity at bottleneck workstation (as shown in Table 10, the utilization of bottleneck workstation drops from 95.12% at 1:0 std WIP to 56.24% at 0:5 std WIP). Therefore, the obtained standard WIP level, al-though it cannot guarantee the optimal, is a safe and reliable amount to achieve a high mean throughput rate with an acceptable short mean cycle time.

Both large and small batch sizes produce long ¯ow times. That is, the batch size and the ¯ow time form a U-shaped curve relationship (Karmarkar

Table 10

Utilization of bottleneck workstation under dierent WIP levels

WIP levels 0:5 std WIP 0:6 std WIP 0:7 std WIP 0:8 std WIP 0:9 std WIP

Utilization 0.5624 0.6806 0.7810 0.8627 0.9173

WIP levels 1:0 std WIP 01:1 std WIP 1:2 std WIP 1:3 std WIP 1:4 std WIP

Utilization 0.9512 0.9658 0.9661 0.9670 0.9674

Table 9

Duncan's multiple range test results for daily mean cycle time

WIP levels N (replications) Mean (h) Duncan grouping % improvement in std of mean CT (over 1.0 std_WIP) 1:4 std WIP 10 54.698 A 26.93 1:3 std WIP 10 51.870 B 20.36 1:2 std WIP 10 49.596 C 15.09 1:1 std WIP 10 45.920 D 6.56 1:0 std WIP 10 43.094 E ± 0:9 std WIP 10 40.662 F 5.64 0:8 std WIP 10 38.448 G 10.78 0:7 std WIP 10 37.484 G 13.02 0:6 std WIP 10 37.154 G 13.78 0:5 std WIP 10 38.414 G 10.86

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et al., 1985; Jacobs and Bragg, 1988; Glassey and Weng, 1991). Small lot sizes produce longer ¯ow times due to excessive setup requirements. Exper-imental results point toward a similar U-shaped phenomenon. When WIP levels are below 0:6 std WIP, their mean cycle times increase owing primarily to the batching eect. A low total WIP level requires more time to accumulate a sucient number of wafer lots to trigger a batch-ing operation, thereby leadbatch-ing to a longer cycle time. The phenomenon that a lower WIP level does not guarantee a shorter average cycle time is also con®rmed in this research.

Previous studies indicated that queueing net-work models had an accuracy within 5±10% on throughput rate (Solberg, 1977; Lazowaska et al., 1984; Chen et al., 1988). Solberg (1977) found that the discrepancy of throughput rate prediction be-tween a queueing network model and a detailed simulation model was within 2.2%. In this study, the initial production target is at 10.6 lots daily. According to simulation results, the mean throughput rate is 10.884 lots daily under the es-timated std_WIP level. The discrepancy is only 2.70%.

The actual throughput rate of the studied new wafer fab is 325 lots a month (10.833 lots per day). Its actual average WIP level is about 225 lots, i.e. nearly 1.55 times of the estimated standard WIP level. The actual average cycle time is around 21.2 days. The actual average throughput rate is very close (2.45% dierence) to the simulated result after extrapolation by setting the WIP level to be 1:55 std WIP. However, when the WIP level is 1:55 std WIP, the actual cycle time (21.2 days) exceeds the extrapolated one (18.857 days). The cycle time discrepancy is attributed primarily to the dis-patching decisions made almost arbitrarily by shop operators and some other unpredictable shop disturbances. Therefore, a WIP reduction plan (including a wafer releasing and dispatching policy and the corresponding shop management procedures) is currently taken.

In summary, it can be concluded that the standard WIP level estimated from this proposed algorithm can achieve a high throughput rate with a reasonable cycle time.

4.3.2. Theoretical and observed value comparisons on utilization of bottleneck workstation, arrival rates, R0

ils, and individual WIP levels at each

workstation

The simulated result of bottleneck utilization (Table 10), 0.9512, is fairly close (1.02% dierence) to the theoretical value kB=SB lB, 0.9610. The

arrival rate at each workstation estimated in Sec-tion 3.1 is called theoretical arrival rate. The ob-served arrival rate is collected from each simulation run. Table 11 presents both theoretical and observed arrival rates at each workstation. The average dierence between theoretical and observed arrival rates is only 6.44%. For a speci®c product type i, the theoretical probability of en-tering loop l; R0

il, is derived from Eq. (2). The

simulated result of probability, R0

il, and the

theo-retical one are given and compared in Table 12. The average discrepancy between theoretical and observed R0

ils is 0.8% which is very small.

The comparison of WIP level at each work-station between the simulated and the queueing network-based predictions are presented in Table 13. Larger dierences of WIP levels at worksta-tions between the results of simulation and queueing model occur mostly at heavier loading workstations. Although the discrepancy of WIP level at each workstation is not very close (32% items' discrepancies of individual WIP values be-tween the queueing network-based model and the simulation model are within 10%), the purpose of this research is to determine the total standard WIP level so that the Fixed-WIP release policy and achieves a high throughput rate with a reasonable short cycle time. If one only concerns with such an aggregate WIP characteristic, the queueing net-work-based model is quite adequate (the total discrepancy on total WIP estimation is only 2.90%).

5. Conclusions

Although there are many WIP-based release control policies which have been proven to be ef-fective for wafer fabrication, few methods, have been proposed to ®nd the suitable WIP-level as a parameter for those release policies. This paper

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proposes a queueing network-based algorithm to determine the total standard WIP level in a wafer fabrication factory so that a eective WIP-based release control policy, Fixed-WIP release control policy, can apply

A simulation model with real numerical data of a newly installed wafer fabrication factory in the Science Based Industrial Park in Taiwan is tested. The experimental result shows that the std_WIP level derived from the heuristic

algo-rithm performs well. It serves as a suitable pa-rameter for the Fixed-WIP lot control policy and achieves a high throughput rate with a reasonable short cycle time under that control policy. Results also demonstrate that the queueing network-based model can be applied to the total standard WIP estimation problem and the proposed algorithm is a very ecient method to determine the standard WIP level for wafer fabrication.

Table 11

Comparisons of observed and theoretical arrival rates (lots/h)

Workstation j 1 2 3 4 5 6 7 8 9 10 Observed 3.589 8.101 8.556 0.455 1.368 3.059 0.656 1.149 0.457 6.572 Theoretical 3.040 7.409 7.850 0. 441 1.323 2.966 0.637 1.107 0.441 5.924 Workstation j 11 12 13 14 15 16 17 18 19 20 Observed 4.279 1.014 4.281 1.366 2.776 2.275 1.365 2.570 1.229 3.821 Theoretical 3.706 0.983 4.147 1.323 2.693 1.323 0.882 2.445 1.233 3.262 Workstation j 21 22 23 24 25 26 27 28 29 30 Observed 0.803 4.453 0.455 7.515 4.281 6.250 1.293 0.886 0.927 1.128 Theoretical 0.779 4.241 0.441 7.281 4.152 5.613 1.250 0.857 0.901 1.094 Workstation j 31 32 33 34 35 36 37 38 39 40 Observed 1.346 1.170 4.586 1.441 0.813 2.131 2.179 0.728 0.604 1.582 Theoretical 1.302 1.134 4.002 1.323 0.788 2.059 2.111 0.706 0.584 1.531 Workstation j 41 42 43 44 45 46 47 48 49 50 Observed 1.000 1.971 2.712 3.590 0.455 0.746 0.745 1.529 1.185 0.358 Theoretical 0.970 1.397 2.187 3.040 0.441 0.723 0.723 1.485 1.147 0.347 Workstation j 51 52 53 54 55 56 57 58 59 60 Observed 1.798 1.150 1.895 0.433 0.071 0.071 0.456 0.455 0.433 1.171 Theoretical 1.744 1.118 1.834 0.420 0.069 0.069 0.441 0.441 0.420 1.134 Table 12

Comparisons of observed and theoretical R0 ils Product Loops 1 2 3 4 5 6 7 8 9 10 11 A Theoretical 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 0.0167 Observed 0.0170 0.0168 0.0168 0.0168 0.0167 0.0167 0.0166 0.0166 0.0165 0.0164 0.0162 B Theoretical 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 0.0177 Observed 0.0179 0.0178 0.0178 0.0177 0.0177 0.0176 0.0176 0.0175 CTheoretical 0.0051 0.0051 0.0051 0.0051 0.0051 0.0051 0.0051 Observed 0.0052 0.0052 0.0051 0.0051 0.0051 0.0051 0.0050 D Theoretical 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 0.0370 Observed 0.0376 0.0374 0.0374 0.0373 0.0371 0.0370 0.0370 0.0368 0.0367 0.0362 E Theoretical 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 0.0299 Observed 0.0303 0.0302 0.0301 0.0299 0.0299 0.0298 0.0297 0.0296 0.0295

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Acknowledgements

The authors acknowledge department manager Richard Huang for the support of production planning department of UMCFab 3 and are grateful to B.M. Sonug and Fransia Hsu for the discussion on the model building. The work was supported in part by the National Science Council, Taiwan, ROC, under project number NSC 88-2213-E-233-003.

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