Structural fault based specification reduction for testing analog circuits

Structural Fault Based Specification Reduction for Testing Analog Circuits

SOON-JYH CHANG AND CHUNG LEN LEE

Department of Electronic Engineering & Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China

soon@dragon.ee.nctu.edu.tw cllee@cc.nctu.edu.tw

JWU E. CHEN

Department of Electrical Engineering, Chung-Hua University, Hsin-Chu, Taiwan, Republic of China

jechen@chu.edu.tw

Received October 5, 2001; Revised May 8, 2002 Editor: K.J. Antreich

Abstract. Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to

reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.

Keywords: analog test, test cost reduction, specification-based test, fault-based test

1. Introduction

Analog circuit testing has been a difficult problem, pri-marily due to the non-deterministic nature of compo-nent parameters and limited accessibility of internal nodes for the CUT. Analog testing techniques are tra-ditionally classified into two categories, i.e., structural (fault)-oriented testing and functional (specification)-based testing. For the structure-oriented testing, a fault model, usually at the circuit level, is adopted and pat-terns (signals) are applied to the CUT to exploit the specific structural difference between the defective and non-defective circuits. However, there are no univer-sally accepted fault models for analog circuits because the nature of analog faults is not constant and cannot be definitely and precisely modeled. For the

functional-based testing, it is to measure some specified perfor-mance specifications of the CUT, such as DC gain, cut-off frequency, and slew rate, etc., and to determine “pass” or “fail” of the CUT based on whether the mea-sured results are within specified ranges. This test ap-proach is straightforward and is easy to be applied. However, it lacks precise metrics to indicate the struc-tural fault coverage and is inherently expensive since it involves expensive dedicated test equipment and long testing time.

Several researches [1, 10, 17] that alleviate the diffi-culty of test generation, fault classification, test quality improvement for analog and mixed-signal testing have been presented by linking the information of structural fault and circuit specifications. One important goal on testing research is to reduce the test time. In the digital

domain, this corresponds to deriving the efficient test set which maximizes fault detection. In the analog do-main, due to the difficulty in defining faults as men-tioned above, there were only a few works on this topic. Huss et al. [4] studied the problem by ordering specifi-cation tests so that faulty circuits are detected early in the test sequence to reduce the average test time. This approach is efficient to reduce test time if a CUT is defective but does not gain advantage when the circuit is normal. Milor and Sangiovanni-Vincentelli [9] also proposed an algorithm for finding an ordering of speci-fication tests to increase the efficiency of the functional testing. This algorithm eliminates the non-critical spec-ifications based on the yield prediction but it is hard to derive the accurate yield and it is time-consuming when correlations between specifications are consid-ered. Souders and Stenbakken [15] presented an ap-proach to select a minimal set of basis vector to calcu-late the entire behavior for analog-to-digital converter. This method reduces the test time but needs extra inter-nal test points for the CUT. Lindermeir et al. [7] pro-posed a characteristic observation inference test design approach for analog circuit. For the approach, for each given specification, it simulates training samples and computes a test inference criterion based on a logis-tic discrimination analysis. With obtained test criteria, satisfaction or violation of the original circuit specifi-cations are inferred from characteristic observations of the circuit under test.

In this paper, we approach this problem by study-ing the relationship between the performance specifi-cations with component parameters of the analog CUT and reaching the conclusion that some of specifications of the circuit can be removed for the testing purpose. By removing the specification, the testing time can be reduced. Also, a statistical approach is employed by taking into account of circuit fabrication process fluc-tuation to show that the specification reduction depends on the testing confidence.

The paper is organized as follows: The fault model and the procedure to derive the relationships between analog faults and specifications are first presented with a simple low pass filter as an illustration example. Then, Monte Carlo simulation is used to find the ef-fect of the manufacturing process fluctuation on the above relationships, and a specification reduction pro-cedure is described. An illustrative case study on the continuous-time state-variable filter benchmark circuit [6] is included to demonstrate the effectiveness of the approach.

2. Mapping Between Faults and Specifications

As mentioned previously, there is no universal and well-defined fault model for testing analog circuits. A common practice is to resort to the circuit level to define a fault to be an “open” or “short” of a circuit component such as a resistor, capacitor or a transistor etc. (catastrophic faults), or a deviation on the value of the above circuit components (parametric faults). These faults are used because they generally can be clearly attributed from physical manufacturing defects and deduced from the computer-aided analysis such as Inductive Fault Analysis (IFA) [8, 11, 14, 18]. They are relatively well defined and easier to be handled. They can be served as a metric for evaluating the testing coverage and the effectiveness of tests for testing ana-log circuits. It has been shown [9, 16] that parametric faults are significantly more important to be considered since they dominate catastrophic faults and are harder to be detected. In this work, specifications are stud-ied to be reduced while considering parametric faults as the metric. Circuit parameters such as resistances, capacitances, inductances passive components and VT

(threshold voltage), W (channel width) and L (chan-nel length) of the MOS transistors are within their al-lowable range, i.e. within specified fluctuations of the manufacturing process. When a parametric fault oc-curs, possibly caused by a local defect or manufactur-ing equipment error, the value of the circuit parameter is outside of the range of the specified range.

2.1. Mapping Specifications to Circuit Parameters Consider a circuit of m parameters, P= [p1, p2, . . . ,

pm], where pi could be resistances of resistor,

ca-pacitance of capacitor, W/L ratio of transistor, and VT of transistor, etc. The performance of the circuit

is bounded by n specifications, S = [s1, s2, . . . , sn]. Su_{= [s}u 1, s u 2, . . . , s u n] and S l _{= [s}l 1, s l 2, . . . , s l n] are

de-noted to the upper and lower bounds for these spec-ifications. For the design with the nominal P value: P0 _{= [p}0

1, p02, . . . , p0m], we can find a corresponding

point, S0 _{= [s}0

1, s20, . . . , sn0], in the specification space.

Fig. 1 shows the abstract graph of mapping between the parameter space and the specification space. Also, it is an aim to conversely find the accepted tolerances of parameters from the allowed ranges of specifications.

Under the single fault assumption, the accepted tol-erance of each parameter can be obtained through de-duction if the relationship between specifications and

Fig. 1. Mapping between the parameter and the spec-ification space [10, 17].

parameters are explicit and simple or through simula-tion combined with back-inference. A simple example will be used to explain this later.

For a specification, say, the j th specification sj ∈

S, it is a function of all parameters p’s. If, un-der the single fault condition, we consiun-der parameter pi, sj can be represented as sj( pi)= f (p1, p2, . . . , pi−1, pi, pi+1, . . . , pm) where all pi’s are fixed

ex-cept pi which is allowed to vary. We assume that sj

is bounded by su j and s

l

j, the accepted process

toler-ance range of pifor sj can be deduced by solving the

inequalities: sj( pi)= f  p0₁, p0₂, . . . , p0i−1, pi, p0i+1, . . . , p0m  ≤ su j sj( pi)= f  p0₁, p0₂, . . . , p0i₋₁, pi, p0i₊₁, . . . , p0m  ≥ sl j

We denote the obtained upper and lower bounds of accepted range of pifor sjto be pui jand p

l

i jrespectively.

A simple low pass filter of Fig. 2 is used as the ex-ample to explain as follows:

The transfer function of the low pass filter is: Vout(s)

Vin(s) =

−R2/R1 1+ sCR2

Assume that the parameters we consider are R1, R2, and C and the specifications are DC gain A0, cut-off frequency fc, input resistance Rin, respectively. For

R1= 2 (M), R2= 2 (M), and C = 100 (pF), A0 = |−R2 R1 | = 1, fc= 1 2π R2C = 795.8 (Hz) and Rin= R1 = R₁ R₂ C V_OUT V_IN Design parameters: R1 = 2 (MΩ) … p10 R2 = 2 (MΩ) … p20 C = 100 (pF) … p30 Specifications: 0.8 ≤ A0≤ 1.2 … s1 600 (Hz) ≤ fc≤ 1 (KHz) … s2 Rin≥ 1 (MΩ) … s3

Fig. 2. A low pass filter example to explain the deduction of rela-tionship between parameters and specifications.

2 (M). The ranges for each specification are as shown in the figure. By solving 0.8 ≤ s1( p1) = |−2 (M)R1 | ≤ 1.2, we obtain that the accepted range of p1 for s1 is 1.667 (M) ≤ R1 ≤ 2.5 (M), i.e., p11u = 2.5 (M) and pl

11 = 1.667 (M). The upper and lower bounds of accepted range of R1for s2is pu12= ∞ and p

l

12= −∞

since s2( p1)= _{2π R}1₂C is independent of R1. Similarly,

we can obtain pu₁₃= ∞, and pl₁₃= 1 (M) by solving s3( p1)= R1 ≥ 1 (M).

The above deductive approach is efficient if the re-lationships between parameters and specifications are explicit and simple. However, these relationships are usually implicit and hard to be derived when circuits are large and active components are involved. For these cases, simulation-based approach needs to be used. That is: the deviations of specifications w.r.t. param-eters are directly simulated. The relationships between specifications and parameters can be obtained in ta-ble or curve forms and bounds of the parameters can be found by applying the constraints of specifications on these relationships. Fig. 3 shows such a curve of specification Aoof the low pass filter circuit of Fig. 2

w.r.t. parameter R1. The upper and lower bounds for R1 for this specification Aocan be extracted to be 2.5 and

1.67 (M) respectively. In a similar way, the bounds of all other parameters w.r.t. the respective specifications can be derived and are shown in Table 1.

2.2. Procedure of Specification Reduction

A circuit is defined as “fault-free” if it satisfies all the constraints of specifications. Thus, the final upper ( pui)

Fig. 3. Relationship curve of specification Aow.r.t. parameter R1

Table 1. Upper and lower bounds of R1, R2and C w.r.t. specifi-cations A0, fcand Ri n. A0 fc Ri n LB UB LB UB LB UB R1 () 1.67 M 2.5 M −∞ ∞ 1 M ∞ R2 () 1.6 M 2.4 M 1.58 M 2.65 M −∞ ∞ C (F) −∞ ∞ 79.3 p 133 p −∞ ∞

UB: upper bound. LB: lower bound.

and lower bounds ( pli) of accepted range for i th

param-eter should be:

piu = minimum  p_{i 1}u, p_{i 2}u, . . . , pinu  pil = maximum  p_{i 1}l , pl_{i 2}, . . . , plin 

For the low pass filter example shown above, the final upper and lower bounds of R1 should be given to be minimum(2.5 M, ∞, ∞) ⇒ 2.5 (M) and maximum(1.67 M, −∞, 1 M) ⇒ 1.67 (M) re-spectively. Hence, if the resistance deviation, caused by a defect, of R1 is within the range of 2.5 (M) and 1.67 (M), the circuit will pass all specifica-tions s1, s2 and s3 and will be considered to be good.

In the above, s1 is the most significant specification in determining the lower bound for the R1 decrease-ment fault since it is the specification which determines the lower bound for R1. This specification is the “Es-sential Lower Bound Specification for parameter i”, denoted to be ELBSi, which is given by the general

form:

ELBSi = sj|pl i j=pli, ∀ j

Similarity, the “Essential Upper Bound Specification for parameter i”, the most significant specification for i th parameter increasement fault, denoted by EUBSi,

is given by:

EUBSi = sj|pu i j=piu, ∀ j

As a result, the “Essential Test Specifications”, the indispensable specifications for all parameter faults, denote by ETS, will be the union of all ELBSs and EUBSs: ETS= m  i₌₁ {ELBSi∪ EUBSi}

Table 2. Tolerance range and the most significant specifications for decreasement and increasement faults of each parameter.

FLB ELBSi FUB EUBSi

R1 () 1.67 M s1 2.5 M s1 R2 () 1.6 M s1 2.4 M s1

C (F) 79.3 p s2 133 p s2

FLB: final lower bound; FUB: final upper bound.

Table 2 summarizes the tolerance range of all pa-rameters and the most significant specifications for the decreasement and the increasement faults of each parameter. From the table, apparently, s1 and s2 are the essential test specifications which need to be con-sidered in testing as all the parameters: R1, R2, and C are considered, but s3 can be ignored. That is: specifications are reduced from s1, s2, and s3 to s1 and s2.

3. The Impact of Manufacturing

Process Fluctuations

As feature size of MOSVLSI moves into the deep sub-micron range, the device characteristics and yield be-come more sensitive to manufacturing process fluctua-tions. When there are variations in the parameter space due to the process fluctuation, correspondingly, there will be variations on the specification space of the cir-cuit. The specification and the parameter relationship such as that of Fig. 3 will become a band instead of a single curve due to value variations, which are caused by the process fluctuation, of all parameters as shown in Fig. 4. If the variations of all parameters are as-sumed to be random, the distribution of the band will be Gaussian [2]. There may be a probability, which is small, that the circuit, originally considered to be good, will not pass the specification due to the process fluc-tuation. If there is a fault on R1, i.e., it deviates to a value, for example, 1.67 (M), the probability that the circuit will not pass A0becomes even larger. However, there may be also a small probability that the circuit still pass A0 due to value variations of other parame-ters caused by the process fluctuation even though R1is faulty.

The above is explained in Fig. 5 for a general case: Generally, specification sjhas a distribution, due to the

Fig. 4. The relationship between specification A0 and parameter R1 becomes a band due to the process fluctuation. j-th Spec. (s_j) s_ju s_jl p_i=p_i0 p_i=K µ=µj( pi0) µ=µj(K) σ=σ_j( p_i0₎ σ=σ_j(K)

Fig. 5. The distributions of a specification due to parame-ter variations for the normal circuit ( pi= pi0) and the faulty

circuit ( pi= K ). There is probability that the normal

cir-cuit does not pass the specification due to the parameter variations, and for the faulty circuit, there still also exists a small probability that the circuit pass the specification.

following form: sj(x, pi)= 1 √ 2πσj( pi) e −(x−µ j (pi ))2 2σ 2_j( pi ) ₍₁₎

where x is the value of specification sj located,µj is

the mean value andσj2is the variance of specification

sj. If there is a fault on pi, i.e., pi deviates to a new

value, K , sj will have a new distribution but with a

form similar to that of Eq. (1). That the circuit passes specification sj is slj ≤ sj(x, pi) ≤ suj. Hence, the

probability that the circuit passes sj when pi = K ,

represented as Prob( pi= K −→ pass sj), is: Probpi = K pass −→ sj  =√ 1 2πσj(K )  su j sl j e −(x−µ j (K))2 2σ 2j(K ) _dx (2)

And, the probability of failing to pass sjis

Probpi = K fail −→ sj  = √ 1 2πσj(K )  sl j −∞e −(x−µ j (K))2 2σ 2j(K ) _{d x} +√ 1 2πσj(K )  _∞ su j e −(x−µ j (K))2 2σ2j(K ) _{dx (3)} Naturally, Probpi = K pass −→ sj  + Probpi = K fail −→ sj  = 1 (4) The above probabilities can be obtained either di-rectly from the relationship between the specification and the parameter of the circuit or computed through Monte Carlo simulation. In the previous low pass filter circuit, ifµ and ±3σ of R1distribution are 2 (M) and ±10% respectively, the probability curves, computed both from equation derivation (solid line) and computer simulation (dotted line), of the circuit to pass specifica-tion (0.8 ≤ A0≤ 1.2) are shown in Fig. 6 with respect to the value of R1.

In the above curves it can be seen that, when R1 equals to its nominal value (=2 M) and all other

Pass 1.4 1.8 2.2 2.4 2.6 2.8 0.2 0.4 0.6 0.8 1.0

Fail Pass Fail

1.738 1.597 2.395 2.607 0.9 0.1 (BP1) (BF1) (BP2) (BF2) Prob(R1---->A0) 2.0 Resistance of R1 1.6

Fig. 6. Probability of the low pass circuit to pass specification

A0with respect to the value of R1, where the nominal value is 2.0 (M). Bounds for parameter R1 to pass or fail A0 during testing for a 90% confidence level are shown. The central region is the pass region, the two outside regions are fail regions, and the two gray regions are uncertain regions.

parameters vary randomly within their respective±3σ around their nominal values, the filter always pass spec-ification A0, but will only “partially” pass A0if R1is smaller than 1.8 (M) or larger than 2.3 (M). For example, if R1= 2.4 (M), the circuit has an approxi-mate 90% probability to pass A0, and if R1= 1.6 (M), it only has an approximate 10% probability to pass this specification. If R1 is greater than 2.7 (M) or smaller than 1.5 (M) the circuit will definitely fail to pass A0.

The bounds of accepted and rejected range for pa-rameters can be obtained by solving Eqs. (2) and (3) under a given testing confidence (that is, after the test-ing, even if the circuit passes all specification tests, the circuit still has a certain probability of not work-ing). For example, if the testing confidence is 90%, four bounds solved for R1for A0are shown in Fig. 6. They are BF1= 1.597 (M), BP1 = 1.738 (M), BP2 = 2.395 (M) and BF2 = 2.607 (M) respectively, where BF1 and BF2 are the lower and upper bound-ary values respectively of the fail band, and BP1 and BP2 are lower and upper boundary values respectively of the pass region. The circuit will pass A0(the DC gain specification) with over a 90% probability when R1is between BP1= 1.738 (M) and BP2 = 2.395 (M), and will fail, with over a 90% probability, if R1is be-low BF1 = 1.597 (M) or over BF2 = 2.607 (M). Within the two gray regions, i.e., BF1= 1.597 (M) and BP1= 1.738 (M), and BP2 = 2.395 (M) and BF2= 2.607 (M), the circuit cannot be determined to be “pass or fail” due to random variations, which are caused by the process fluctuation, of other parameters. If we reduce the testing confidence, these two regions will shrink. For example, if we only ask for a testing confidence of 50%, these two regions will shrink to zero and the problems of setting the fault boundaries, consequently the specification reduction, will be sim-plified to that as stated previously in Section 2.

For the general i th parameter ( pi) for the j th

speci-fication, we denote the above four bounds to be BP1i j,

BP2i j, BF1i j, and BF2i j respectively. If a circuit is

fault-free, it should satisfy “all” specifications, and the bounds of the accepted range for the i th parameter are given by:

BP1i = maximum(BP1i 1, BP1i 2, . . . , BP1in)

BP2i = minimum(BP2i 1, BPi 2, . . . , BP2in)

On the other hand, a circuit is considered to be faulty if it violates one of specifications. Hence, the bounds

BP1_ki Pass Fail Pass Fail S_i S_j p_k BF1_ki BP1_kj BF1_kj p_k0 Fail Fail BP2_ki BP2_kj BF2_kj BF2_ki Pass Fail Pass Fail S_i S_j p_k (b) p_k0 Fail Pass Fail Fail Fail S_k (a) BP1_ki Pass Fail Pass Fail S_i S_j p_k BF1_ki BP1_kj BF1_kj p_k0 Fail Fail BP2_ki BP2_kj BF2_kj BF2_ki (c) p_kf

Fig. 7. Elimination of specifications based on the locations of pass, fail, and uncertain regions between specifications for a parameter pk.

of rejected range for the i th parameter are: BF1i = maximum(BF1i 1, BF1i 2, . . . , BF1in)

BF2i = minimum(BF2i 1, BF2i 2, . . . , BF2in)

Hence, a specification Si can be neglected, for a

pa-rameter pk, when its bounds of pass range are outside

bounds of another specification Sjsince a circuit which

passes Sjwill always pass Sias shown in Fig. 7(a). For

the case in Fig. 7(b), Sj can be ignored because it is

“dominated” by Sifor pklower bound fault and, on the

other hand, “dominated” by Skfor pkupper bound fault.

However, for the case of Fig. 7(c), neither Sjnor Skcan

be neglected since there are overlap between their re-spective gray regions. When the parameter value, for example, pkf, falls into these gray regions, there is

al-ways a probability that the CUT will not pass either of the specifications.

Hence, for the testing purpose, we can define “redundancy” for specifications as following:

Definitions.

(a) A specification Sjis “lower bound redundant” for

a parameter pk, if a specification Si,i= jexists such

that BF1ki ≥ BP1k j.

(b) A specification Sjis “upper bound redundant” for

a parameter pk, if a specification Si,i= jexists such

Fig. 8. (a) The 2-dimensional probability bell for passing specifica-tion Sjtest for the double-parameters ( pm, pn) fault; (b) The circlet,

which is cut from the 2-dimensional cone of (a) for a test confidence of 90%.

(c) A specification is “redundant” for testing, i.e., it can be removed, if it is both lower bound redundant and upper bound redundant for all parameters. In above, we presented the approach of specification reduction based on soft (parametric) faults. However, the above approach also applies to hard faults since when a hard fault occurs, the circuit often fails at least one specification.

In the above, in order to obtain the probability curves, Monte Carlo simulation needs to be done, which is a time consuming process. Time complexity may be a problem large size circuits are considered. One ap-proach to alleviate this difficulty is to partition the CUT into several small blocks and the simulation is done hierarchically [3].

Also, in the above, we deal with only single parame-ter fault [5, 13]. When more than two parameparame-ter faults are considered, the case will be more complex. To ex-plain, for simplicity, a double fault ( pm, pn) case is

used as an example. When a double parameters fault is considered, the probability curve for one specification, say Si, will become a three-dimensional cone as shown

in Fig. 8(a) rather than the two-dimensional curve of Fig. 6. For a given confidence level, a circlet will be cut on the cone as shown in Fig. 8(b). Similarly, when another specification, saying Sj is also considered for

reduction, another circlet can also be obtained. If the circlet of Sj covers the circlet of Si, then Sj is

domi-nated by Sifor this double ( pm, pn) fault. As a result, Sj

can be neglected when testing for the double-parameter fault.

4. Example

To further illustrate the above specification reduction approach, a benchmark continuous-time state-variable

filter circuit [6], as shown in Fig. 9(a), is used to demon-strate the procedure, as well as its efficiency.

For this circuit, the band-pass output (BPO) is taken as the output and R1= R2 = R3 = R4 = R6 = 1 M, C1 = C2 = 200 p, R6 = 300 K, and R7 = 700 K. The central frequency for the band-pass output (BPO),

fc = (2π

√

R3C1R4C2)−1 = 795 Hz with a gain equal to 1.11. The frequency response of the circuit is shown in Fig. 9(b). The operational amplifiers in this circuit are the benchmark operational amplifier [6], as shown in Fig. 10. It is adopted for the purpose to make the study more practical. The technology file used for all computer simulation in the study is TSMC CMOS 0.8 um SPDM technology file of under a±2.5 V supply voltage. The specifications of the filter are shown in Table 3.

With the fault model described previously, the num-ber of parameters (R, C, and W /L and VTof each

tran-sistor) is 66. To study the effects on specifications of all the faults of parameters, a Monte Carlo simulation by considering a 10% (=3σ) variation on parameter values has been performed. Table 4 summarizes the simulated results where the mean and variance of each specification are listed. The results are in two groups: one group is for parameters in operational amplifiers, and the other group is for passive component param-eters outside operational amplifiers. In the table, the variance of each specification caused by the parame-ters inside operational amplifiers is much smaller than that caused by the passive components outside oper-ational amplifiers. This is obvious since devices and components in an operational amplifier are insensitive to the characteristics of the operational amplifier due to negative feedback. Hence, in the forgoing study, only the passive components (R1–R7, C1, C2) outside op-erational amplifiers are considered.

Table 5 shows the bounds (BF1, BP1, BP2, BF2) ob-tained from simulations for all specifications w.r.t. C1 under 99%, 90% and 50% testing confidence. From the table, it is seen that C1 is insensitive to specifications 1 and 7 because, even if a large deviation occurs in C1, the circuit always passes testing for these specifica-tions. Also, decreasing the testing confidence reduces the uncertain ranges (BF1–BP1 and BP2–BF2) and a 50% testing confidence gives a zero uncertain range. The essential lower bound specification (ELBS) and essential upper bound specification (EUBS) for C1 are also derived. For the 99% testing confidence case, the maximum{BF1’s} is 154 (pF) from specification S2 (this means that if a defect causes C2 smaller than 154

Fig. 9. (a) The circuit of the benchmark continuous-time state-variable filter. (b) Frequency response of band-pass output.

(pF), there is a 99% probability that the circuit will fail the test). However, for S1, S3, S6, S7, S9 and S10, their BP1 values are all smaller than 154 (pF), i.e., these specifications can be ignored when considering the C1

Fig. 10. Schematic representation and element values of benchmark CMOS operational amplifier.

decrease fault. Hence, the ELBS’s are S2, S4, S5 and S8. On the other hand, the EUBS’s are S2, S4, S5, S6 and S9 because their BF2 values are smaller than the minimum{BF2’s} = 260 (pF), which is derived from

Table 3. Specifications of the filter circuit and their nominal values (NV), lower bounds (LB), and upper bounds (UB).

Specifications NV UB LB

S1: Gain @ fc 1.11 1.3 1

S2: Central frequency ( fc) 794 900 700

S3: Low cutoff frequency 515 600 400 S4: High cutoff frequency 1231 1400 1000 S5: 3 dB bandwidth 716 1000 500 S6: Quality factor 1.11 1.3 0.9 S7: Gain @ 100 Hz 0.13 0.2 0 S8: Gain @ 700 Hz 1.07 ∞ 0.9 S9: Gain @ 900 Hz 1.07 ∞ 0.9 S10: Gain @ 10 KHz 0.08 0.2 0

Table 4. Means and variances of specifications caused by variations of device parameters inside operational amplifiers and by passive component parameters outside operational amplifiers.

Caused by the variations of device Caused by the variations of passive parameters in opamps R and C outside opamps

Specifications Mean Variance Mean Variance

S1: Gain @ fc 1.11 2.19× 10−9 1.10 2.19× 10−3

S2: Central frequency ( fc) 794 6.40× 10−25 793 1150

S3: Low cutoff frequency 515 7.82× 10−5 512 555

S4: High cutoff frequency 1231 5.17× 10−4 1228 3361

S5: 3 dB bandwidth 716 9.71× 10−4 716 2340 S6: Quality factor 1.11 2.33× 10−9 1.11 3.60× 10−3 S7: Gain @ 100 Hz 0.13 1.16× 10−13 0.13 5.64× 10−5 S8: Gain @ 700 Hz 1.07 1.74× 10−9 1.06 2.41× 10−3 S9: Gain @ 900 Hz 1.07 1.75× 10−9 1.05 2.46× 10−3 S10: Gain @ 10 KHz 0.08 2.67× 10−13 0.08 2.6× 10−5

Table 5. Bounds of pass and fail range for all specifications w.r.t. C1 under 99%, 90% and 50% testing confidence (unit: pF) (∞ : infinity).

99% confidence 90% confidence 50% confidence

Spec. BF1 BP1 BP2 BF2 BF1 BP1 BP2 BF2 BF1 BP1 BP2 BF2 S1 −∞ −∞ ∞ ∞ −∞ −∞ ∞ ∞ −∞ −∞ ∞ ∞ S2 154 158 256 260 156 156 256 260 156 156 258 258 S3 74 152 278 586 92 134 348 518 114 114 432 432 S4 150 184 228 312 158 176 246 294 168 168 270 270 S5 130 156 244 330 136 150 262 310 144 144 286 286 S6 116 148 244 294 122 142 256 282 132 132 270 270 S7 −∞ −∞ ∞ ∞ −∞ −∞ ∞ ∞ −∞ −∞ ∞ ∞ S8 44 176 336 476 74 148 368 444 110 110 406 406 S9 18 90 228 314 28 68 248 296 42 42 272 272 S10 76 84 ∞ ∞ 78 82 ∞ ∞ 80 80 ∞ ∞

S2 also. Combining ELBS’s and EUBS’s, we obtain the essential test specifications (ETS) for the C1 deviation fault are S2, S4, S5, S6, S8 and S9.

In a similar way, the ETS’s for all component pa-rameters can be obtained. The final reduced test spec-ification set is a set of the union of the ETS’s of all component parameters. Table 6 shows the ETS’s for all component parameters, the final reduced test speci-fications and the ignored test specispeci-fications under 99%, 90% and 50% testing confidence, respectively. It can be seen that in general certain number of test speci-fications can be reduced for a component parameter and when all parameters are considered, there are still

some specifications can be ignored. Also, as the testing confidence is decreased, the number of ignored speci-fications increases.

To study the effect of hard faults, a total of 36 short (bridging) faults between nine circuit nodes (4 internal nodes, HPO, BPO, LPO, input and ground) are sim-ulated. For a short fault, a short resistance of 10 () is assumed. Table 7 lists the number of short faults detected when all the above specifications are consid-ered. All of 36 short faults can be detected. Even for S1 testing, it can detect 33 faults and for S2 testing, it can detect 32 faults. With S1 and S2 testing simultaneously, all 36 short faults are detected. This demonstrates that

Table 6. Essential test specifications for each component parameter under 99%, 90% and 50% testing confidence.

Component 99% confidence 90% confidence 50% confidence

R1 1, 4, 6, 8, 9 1, 8, 9 1 R2 1, 2, 3, 4, 5, 8, 9 1, 2, 3, 4, 8, 9 4, 9 R3 2, 3, 4, 5, 6, 8, 9 2, 4, 6, 9 2, 4 R4 2, 3, 4, 8, 9 2, 3, 8 2, 3 R5 1, 2, 3, 4, 8, 9 1, 2, 3, 4, 8 2, 8 R6 1, 3, 4, 5, 6, 8, 9 1, 6, 8, 9 1 R7 1, 3, 4, 5, 6, 8, 9 1, 6, 8, 9 1 C1 2, 4, 5, 6, 8, 9 2, 4, 6, 9 2, 4 C2 2, 3, 4, 8, 9 2, 3, 8 2, 3

Final test specs. 1, 2, 3, 4, 5, 6, 8, 9 1, 2, 3, 4, 6, 8, 9 1, 2, 3, 4, 8, 9

Ignored test specs. 7, 10 5, 7, 10 5, 6, 7, 10

Table 7. Number of detected hard faults for each specification.

Specifications All spec. S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S1+ S2

Detected 36 33 32 31 32 31 32 17 32 32 15 36

the specification test can easily detect hard faults. If a hard fault can not be detected by all specification test, this fault can be effectively considered as a redundant fault since it does not affect the performance of the circuit.

5. Conclusion

In this paper, we have presented an approach to reduce the number of test specifications for analog circuits. The approach starts with derivation of the relationship between specifications and device and/or component parameters then defines upper and lower bounds for parameters to find essential test specifications. Then the variations on component parameters due to fab-rication process fluctuations are considered by using a statistical model to reduce test specifications with a testing confidence probability. A continuous time state-variable filter example circuit has been used to demon-strate the specification reduction procedure and it has been shown that 2, 3 or 4 out of 10 specifications can be ignored during specification testing under the 99%, 90% and 50% testing confidence level respectively. The procedure is effective and can be used in manufacturing specification test for analog circuits to reduce test time.

Acknowledgment

We acknowledge the many discussions we had on the subject of this paper with Prof. C.C. Su of the National Central University, Taiwan.

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Soon-Jyh Chang was born in Taiwan 1969. He received his M.S.

degree in Electronic Engineering from National Chiao-Tung Univer-sity, Hsin-Chu, Taiwan, in 1996. He is currently working towards his Ph.D. degree at NCTU. His research interests including test generation and design for testability for analog and mixed-signal circuits.

Chung-Len Lee received BS degree in electrical engineering from

National Taiwan University, Taiwan, R.O.C., in 1968. He obtained his M.S. and Ph.D. Degree in Electrical Engineering, Carnegie-Mellon University, U.S.A., in 1971 and 1975 respectively. From 1975, he has been a professor of Electronic Engineering at National Chiao-Tung University in Taiwan, and was the director of Semiconductor Research Center of the university in the period of 1980–1983. From 1989 to present, he is the director of the Training Center for Sub-micron Professionals of the university and supervised more than 100 M.S. and Ph.D. students to complete their thesis work that result in more than 200 journal and conference papers published. His re-search interests are in the area of semiconductor processes, material and devices, integrated circuit design, VLSI testing, and integrated optics. He has been involved in various technical activities in the above areas in Taiwan as well as in Asia. He is a senior member of IEEE and member of editorial board, Journal of Electronic Testing:

Theory, and Application.

Jwu E. Chen received BS, MS, and Ph.D. degrees in electronic

en-gineering from National Chiao-Tung University, Taiwan, in 1984, 1986 and 1990 respectively. Presently, he is an sssociate professor of Electrical Engineering of Chung-Hua University, Taiwan. His re-search interests are in reliability, fault tolerant and test quality of circuits.