IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 7, JULY 1998 259
A Novel Process to Form Cobalt Silicided p
Poly-Si Gates by
Implantation into Bilayered
CoSi/a-Si Films and Subsequent Anneal
W. K. Lai,
Student Member, IEEE, H. W. Liu, M. H. Juang, N. C. Chen, and H. C. Cheng,
Member, IEEEAbstract— A novel process that implantsBF2+ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided p+poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide.
I. INTRODUCTION
S
URFACE-CHANNEL p-MOSFET’s with p poly-Si gates have been investigated [1] in place of the buried-channel devices with n poly-Si gates due to superior short-channel behavior, better turn-off characteristics, lower threshold voltage operation, much less sensitivity to process tolerances [2], and improved hot-carrier reliability [3]. However, it has been reported that boron impurities from the -doped poly-Si gate could readily diffuse through the gate oxide during high-temperature anneals [4]–[7]. This boron penetration can result in flat-band voltage shift, increase of the subthreshold swing and leakage current, and deterioration of the gate oxide quality. Hence, different structures have been investigated, such as the as-deposited a-Si gate [8] in place of the poly-Si gate, the stacked a-Si (or poly-Si) gate structures [9]–[11], and various nitrided gate oxides [12]–[14], to retard the boron diffusion into underlying Si substrate.In this letter, a novel process that forms the CoSi on the amorphous silicon layer and then implants dopants into such a thin bilayer followed by an anneal is proposed to suppress the boron penetration and form a cobalt silicided poly-Si gate structure.
II. EXPERIMENTS
(100) oriented, 3–5 -cm, n-type Si wafers were used. Field oxides of 450 nm thickness were thermally grown for
pat-Manuscript received January 28, 1998; revised April 1, 1998. This work was supported in part by the R.O.C. National Science Council under Contract NSC-87-2215-E-009-047.
W. K. Lai, H. W. Liu, and H. C. Cheng are with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
M. H. Juang is with the Department of Electronics Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C.
N. C. Chen is with Holtek Microelectronics Inc., Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier S 0741-3106(98)04779-X.
terning the active region of metal-oxide-semiconductor (MOS) capacitors. Thin gate oxide of 8 nm thickness was grown at 900 C in a dry O ambient. Immediately, undoped a-Si and poly-Si of 100 nm thickness were deposited on respective samples by low-pressure chemical-vapor-deposition (LPCVD) at 550 and 620 C, correspondingly. The gate electrode was patterned for the utilization of selective etching. Some specimens with poly-Si films, used as the control samples, were first -implanted at 40 keV to cm . Then, thin Co films of about 13.5 nm thickness, which would form 45-nm CoSi films, were deposited by an -beam evaporation system for all the samples. Thin Mo films of 18 nm thickness were subsequently deposited to serve as a passivation layer for the first-step silicidation anneal. The anneal was performed at 450 C for 60 s by rapid thermal annealing (RTA). Mo and the unreacted Co layer on field oxide were selectively removed in a 5:1:1 mixture of H O:H O :NH OH and a 6:1:1 mixture of H O:H O :HCl, correspondingly, at 55–60 C. After the self-aligned silicide process, the samples with bilayered CoSi/a-Si and CoSi/poly-Si films, except the control specimens, were -implanted at 55 keV to cm . The second-step anneal was by RTA at temperatures ranging from 700 to 1000 C (60 s for 700, 800, and 900 C, and 30 s for 1000 C). The resultant gate oxide integrity was characterized by current–voltage ( – ) and capacitance–voltage ( – ) measurements.
III. RESULTS AND DISCUSSION
From the previous shallow-junction studies [16]–[17], the usage of CoSi as an implant barrier as well as a boron diffusion source could effectively reduce the boron diffusion. Hence, this process is supposed to retard the boron penetration through gate oxide. In addition, a-Si films are preserved during the initial silicide formation to further suppress the boron pene-tration [8]. The resulting sheet resistance of the polycide films decreases with increasing second-step annealing temperature and is still stable even at higher annealing temperature of 1000 C.
Fig. 1 shows the quasi-static – curves for the samples with the poly-Si layer only, the bilayered CoSi/poly films, and the bilayered CoSi/a-Si films, respectively, annealed at 900 C for 60 s. The – curve for the poly-Si samples is much distorted and shifted to the right as compared to the CoSi/poly and CoSi/a-Si ones, indicating a large amount of
260 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 7, JULY 1998
Fig. 1. Normalized quasi-staticC–V curves for the specimens with poly-Si, CoSi/poly, and CoSi/a-Si films, respectively, annealed at 900C for 60 s.
boron penetration has occurred [5]. In addition, a significant capacitance reduction for the poly-Si samples is found in the inverse bias region, which is caused by the gate depletion layer formation. The slightly distorted – curve is also observed in the CoSi/poly samples. On the other hand, such a dramatically distorted - curve in the poly-Si sample is not observed in the CoSi/poly and CoSi/a-Si specimens, reflecting the fact that the boron penetration is suppressed.
The implanted-dopant diffusion from the silicides into the underlying poly-Si layer should be sufficient to avoid possi-ble polysilicon depletion effect after post-implant annealing. Boron penetration effect on and polysilicon depletion were investigated over a wide range of RTA temperatures, as shown in Fig. 2, where the poly-Si, the CoSi/poly, and the CoSi/a-Si samples were compared. Polysilicon depletion effect is monitored by plotting , where
(defined at V) is the quasi-static inversion capacitance just prior to the deep inversion region [15] and (defined at V) is the oxide capacitance. The values in the CoSi/a-Si samples are much lower than the CoSi/poly ones at RTA temperatures below 800 C. The undoped a-Si films of 100 nm thickness were deposited by LPCVD at about 550 C. Since the first-step annealing for forming CoSi was only 450 C, the silicide films were still amorphous after the CoSi formation. Moreover, the a-Si films have been reported to be capable of retarding the boron diffusion [8]. Therefore, the resultant doping concentration in the poly-Si layer may be inadequate and may cause the depletion effect after a low annealing temperature below 800 C. Obviously, such a depletion phenomenon for the CoSi/a-Si specimens is greatly reduced when the annealing temperature is above 900 C. In addition, large shifts were found in the poly-Si samples, especially at RTA temperatures above 900 C, indicating severe boron penetration through thin gate oxide. However, the shifts were largely reduced in the CoSi/poly samples, which implied that the CoSi implantation
Fig. 2. Flat-band voltage(Vfb) and polysilicon depletion effect, as moni-tored by normalized inversion capacitance(CQS;inv=Cox), on the specimens
with poly-Si, CoSi/poly, and CoSi/a-Si films, respectively, as a function of post-implant anneal temperatures.
Fig. 3. Dependence of charge to breakdownQbd on RTA temperature for the poly-Si, CoSi/poly, and CoSi/a-Si samples, respectively.
barrier could effectively retard the boron penetration during subsequent post-implant annealing. Furthermore, the CoSi/a-Si samples exhibited significantly smaller shift, as compared to the CoSi/poly samples, attributable to considerably sup-pressed boron penetration. As a result, with the effective retardation of boron penetration from using CoSi as the implantation barrier, the a-Si layers could be further used to achieve even better results.
The dependences of charges to breakdown on RTA temperature were shown in Fig. 3. At least ten capacitors, with the area of cm , for each sample were taken to evaluate the measurements. The stress current density of 100 mA/cm was used. The value for the poly-Si samples
LAI et al.: A NOVEL PROCESS TO FORM COBALT SILICIDED p POLY-SI GATES 261
Fig. 4. Comparison of the gate voltage shift (1Vg) under the constant
current (100 mA/cm2) stress for the poly-Si, CoSi/poly, and CoSi/a-Si samples, respectively, annealed at 900C for 60 s.
was extremely low even at RTA 700 C. It is attributed to the readily boron penetration caused by dopant implantation (40 keV) into such a thin poly-Si layer, i.e., 100 nm in thickness. However, the CoSi/poly samples could exhibit much better value than the poly-Si samples, especially at RTA temperatures lower than 900 C. Furthermore, the CoSi/a-Si samples could achieve much better , implying the effectiveness of this process in preventing the boron penetration. In addition, Fig. 4 shows the gate voltage shifts during the constant current (100 mA/cm ) stress for the poly-Si, CoSi/poly, and CoSi/a-Si samples, respectively, annealed at 900 C. The electron trapping rate of gate oxide in the CoSi/a-Si samples is found to be much lower than those for the poly-Si and CoSi/poly ones, indicating the generation of less electron traps.
IV. CONCLUSION
In conclusion, the novel process that implants dopants into thin bilayered CoSi/a-Si films and subsequent anneal has been used to form cobalt silicided p poly-Si gates with excellent thin gate oxide integrity and very small shifts. Here, a low-temperature annealing to form the CoSi is required to keep the amorphous silicon underlayer, i.e., the CoSi/a-Si bilayer. Thus the usage of such bilayer films could significantly suppress the boron penetration, by combining both effects of the a-Si layer and the CoSi implantation barrier. As a result, the scheme shows good feasibility for further deep submicron dual gate CMOS technology.
ACKNOWLEDGMENT
The authors would thank the National Nano Device Labora-tory (NDL) of R.O.C. NSC and the Semiconductor Research Center (SRC) of National Chiao Tung University for the technical support.
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