Analysis and Design of Two Low-Power
Ultra-Wideband CMOS Low-Noise
Amplifiers With Out-Band Rejection
Ching-Piao Liang, Pei-Zong Rao, Tian-Jian Huang, and Shyh-Jong Chung, Senior Member, IEEE
Abstract—Two 3–5-GHz low-power ultra-wideband (UWB)
low-noise amplifiers (LNAs) with out-band rejection function using 0.18- m CMOS technology are presented. Due to the Fed-eral Communications Commission’s stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile com-munications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band prop-erties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.
Index Terms—Complementary metal–oxide semiconductor
(CMOS), low-noise amplifier (LNA), out-band rejection, ultra-wideband (UWB).
I. INTRODUCTION
U
LTRA-WIDEBAND (UWB) systems realize high data rate in the short-range wireless transmission, which are suitable for integration in various consumer electronics such as PCs, cellular phones, digital cameras, and PDAs. The minimum received power in the UWB channel is 47 and 67 dB, in the worst case, lower than those of the wireless local area network (WLAN) interferer powers at 5.2 and 2.4 GHz, respectively [1]. In addition, a tone is measured at 1.87 GHz in a smart phone currently on the market, and the power level is 35 dB higher than the UWB signal [2]. All of these interferers, as shown in Fig. 1, have a harmful effect on the received UWB signal; they can especially lead to the receiver gain compression and their possible intermodulation products can fall in-band. Although the interferers may further be attenuated by the baseband filter in the receiver, this does not address the problems of the intermodula-tion distorintermodula-tion and the receiver gain desensitizaintermodula-tion. In order to achieve reasonable performance for the above considerations, as summarized in Table I, more than 10-dB attenuation over the bandwidth of each interferer with 20-dB peak attenuation Manuscript received January 13, 2009; revised August 30, 2009. First pub-lished January 15, 2010; current version pubpub-lished February 12, 2010. This work was supported by the National Science Council of Taiwan under Contract NSC96-2752-E009-003-PAE.The authors are with the Department of Communication Engineering, Na-tional Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: sjchung@cm. nctu.edu.tw).
Digital Object Identifier 10.1109/TMTT.2009.2037855
Fig. 1. Spectrum of the UWB system with large interferers. TABLE I
NOTCHFILTERSPECIFICATIONS
is appropriate in the front-end [3]–[7]. On the other hand, a larger attenuation in the front-end can also relax the baseband filter achieving an implementation with the smaller group-delay variations and lower dc power consumption [5].
Recently, a design of multiple-stopband filters is presented for the suppression of interfering signals such as global system for mobile communicatins (GSM), WLAN, and worldwide interop-erability for microwave access (WIMAX) in UWB applications [3]. The coupled resonator stopband filter sections with bent res-onators were adopted in order to more effectively suppress har-monics and the maximum rejection is about 25 dB at 1.8 GHz. However, this prototype of the filter, which was fabricated on the basis of the standard printed circuit board (PCB) process, will increase the entire UWB system area. Moreover, the multiple re-ceivers with equal-gain combining were employed to eliminate the narrowband interferers received in the two paths and com-bined out-of-phase to cancel each other by selecting the optimal local oscillator (LO) phase [4]. A maximum 28-dB attenuation of the interferers was measured, but it is unavoidable to increase the system’s complexity.
On the other hand, the topologies utilized for wideband am-plifiers generally include the distributed configuration [8], [9], resistive shunt-feedback structure [10]–[12], common-gate termination [13]–[15], and LC input network [16], [17]. The distributed amplifiers are attractive for their ultra-wide band-width; however, the major drawbacks are the large area and high dc power consumption, which make them unsuitable for many ap-plications. The resistive shunt-feedback and common-gate 0018-9480/$26.00 © 2010 IEEE
by using the CMOS technology. In the first UWB LNA, a new wideband input impedance-matching network, which is based on the LC structure with focus on the improvement of out-of-band rejection capability, is presented. By suitably introducing two additional capacitors in the traditional LC input network, two transmission zeros at 1.8 and 8.5 GHz are generated to achieve the out-band rejection property without suffering from dete-rioration of the in-band performance. As an improvement of the first approach, the second proposed UWB LNA introduces a capacitive feedback path to the input LC network for further enhancing the rejection capability at the lower band transmission zero (1.8 GHz). A maximum 32-dB improvement is attained due to the usage of a feedback capacitor. A dual-band notch filter made of active inductors, which occupies only a small chip area, is also employed after the LNA core so as to attenuate the WLAN interferers at 2.4 and 5.2 GHz without influencing the noise figure (NF) of the LNA. The proposed active inductors are designed based on the cascode gain-boosting stage with a feedback re-sistor, which are with low consumption power while maintaining a sufficient value. The introducing of both the feedback capac-itor and the dual-band notch filter achieves maximum rejections of about 50 dB on the out-band interferers, which is superior to those presented in the literature [3], [4], [18], [19]. This paper is organized as follows. Sections II and III present the analyses of the first and second UWB LNAs, respectively. The circuit imple-mentation and experimental results are illustrated in Section IV, followed by a conclusion in Section V. In this study, the circuit simulation is performed via Agilent’s Advanced Design System (ADS) software with a TSMC design kit.
II. FIRSTUWB LNA
The first 3–5-GHz CMOS UWB LNA proposed here adopts a source-degenerated cascode configuration, as shown in Fig. 2. An LC input network for wideband operation is utilized with two new capacitors and for increasing the higher and lower out-band rejections, respectively. The load inductor in series with the resistor helps to enhance the gain flatness. The buffer transistor with a purely resistive load is em-ployed for testing purposes.
A. Power Gain
The overall gain of the proposed LNA can be easily obtained as follows after a straightforward derivation:
(1)
Fig. 2. Complete schematics of the first UWB LNA with out-band rejection.
where
(2) with
(3)
is the 50- source resistance, , and is
the total capacitance between the drain of the transistor and ground. is the reflection coefficient at the input port. From (1), it is seen that extra transmission zeros (i.e., ) can be created when the following conditions are satisfied:
or (4)
in which means that the input impedance of the LNA is short circuit, and it occurs as the impedance , i.e., the impedance of the tank in series with the capacitor (see Fig. 2) is equal to zero, where
(5) By using (2), (4), and (5), the locations of transmission zeros can be predicted as
(6)
B. Optimum Out-Band Rejection
The above ratiocination reveals that the additional capaci-tors and will bring about two transmission zeros to ameliorate the out-band performance. However, the out-band rejection characteristics are restricted by the series resistance of the on-chip inductor. As seen from(6), the higher and lower out-band transmission zeros are associated with the inductors and , respectively. These component values influence not
Fig. 3. (a) Simulated power gain(S ) and (b) input return loss (1=S ) for different values ofL with L = 2:0 nH, C = 0:82 pF, and C = 2:95 pF. The transmission zero! is kept constant.
only the zeros’ frequencies, but also the out-band suppression levels, as shown below.
Fig. 3(a) shows the power gain versus frequency with different values of . To begin with, it can be anticipated that the higher frequency out-band elimination efficiency is mainly deter-mined by the impedance of the tank at the resonant fre-quency (i.e., the larger impedance, the superior out-band suppres-sion). Therefore, the first step is to assign a larger to arrive at larger resonant impedance [20, Ch. 14]. In addition, a preferable power gain in the target frequency range can be procured contem-poraneously by using a larger , as shown in Fig. 3(a). However, an overlarge will lead to over abounded input impedance, as shown in Fig. 3(b), thus decreasing the input matching band-width of the LNA, which is not desirable for this design.
As is clear from (5), the impedance in Fig. 2 produces one series and one parallel resonance from which the lower transmission zero can be created. It is expectable that a smaller impedance at the series resonant frequency will accomplish the superior out-band elimination efficiency. Fig. 4 shows the re-lation between the impedance and frequency for different values. As is seen, a smaller results in a smaller . This, in turn, does cause a deeper suppression level at (1.8 GHz), as can be observed from the power gain versus frequency diagram shown in Fig. 5(a). Nevertheless, a drawback that may make the design unsatisfactory is that a diminishing , and thus, a deceasing , may reduce the input impedance, and thus, dete-riorate the matching condition, as demonstrated in Fig. 5(b).
Fig. 4. ImpedanceZ versus frequency with different values of L . The trans-mission zero! is kept constant.
Fig. 5. (a) Simulated power gain(S ) and (b) input return loss (1=S ) for different values ofL with L = 2:0 nH, L = 0:5 nH, C = 0:17 pF, and C = 0:23 pF. The transmission zero ! is kept constant.
From the above discussion, it should be taken into account punctiliously by choosing appropriate values of and to achieve the tradeoff between the input match and out-band re-jection performances.
It is interesting to see the influence of the input network on the LNA’s NF. After a straightforward derivation following the procedure in [21], the NF of the circuit shown in Fig. 2 can be obtained as
Fig. 6. Simulated NF of the first UWB LNA due to the active gain stages and the losses of the input network.
Obviously, the proposed UWB LNA will produce double-peak maxima in noise factor at the two transmission zeros. Conse-quently, it must be cautious to prevent from worsening the noise property in the desired frequency range when designing the lo-cations of the zeros. Fig. 6 shows the simulation results of the NFs due to the active gain stage only,
with the input network, and the total circuit. It can be observed that the dominant noise contributor is the active gain stage. The out-band rejection input network has a minor influence on the total NF as long as the designed transmission zeros are not too close to the in-band. To reduce the noise contribution from the active gain stage, the width of the transistor will be chosen for optimum noise property [22].
III. SECONDUWB LNA
The first UWB LNA improves the higher and lower out-band performances by introducing the capacitors and . However, a tradeoff between the input matching and out-band rejection should be carefully considered so as to make an optimum design. In the second approach, we utilize a feedback capacitor and active dual-band notch filter, as shown in Fig. 7, to attenuate the out-band interferers without deterio-rating the input matching bandwidth.
A. Effect of the Feedback Capacitor
The capacitor will engender the lower band transmis-sion zero such as 1.8 GHz, but the rejection characteristic is restricted by the series resistance of on-chip inductor. For fur-ther suppression of the unwanted signal at 1.8 GHz, we intro-duce a feedback capacitor to the input LC network. As shown in Fig. 7, the voltage gain at node is equal to if appro-priate device sizes of and are selected so that the ratio equals unity. This makes the signal at node 180 out-of-phase with the input signal . On the other hand, the
tank, which provides a parallel resonance at the in-band operation, behaves as an equivalent inductor at 1.8 GHz. Con-sequently, a suitably designed feedback capacitor in series with the equivalent inductor can produce a series resonance at 1.8 GHz so that the out-of-phase signal at can be brought back to further cancel the input 1.8-GHz unwanted signal. In short,
Fig. 7. Principle of the interferer-canceling technique with a feedback capac-itorC and active dual-band notch filter.
Fig. 8. Simulated power gain(S ) of the second UWB LNA with and without the additional capacitorC .
the tank behaves like an open circuit in the in-band, and thus, has little influence on the input impedance, while it may introduce an out-of-phase feedback signal to eliminate the un-wanted 1.8-GHz signal. Fig. 8 shows the simulation results of the power gain with and without the additional capacitor . It can be observed and demonstrated that a maximum 32-dB de-crease in power gain is attained at 1.8 GHz while maintaining an identical in-band characteristic.
B. Dual-Band Notch Filter
An on-chip dual-band notch filter is to be placed before the output of the second LNA, as shown in Fig. 7. Here, to avoid the deterioration in NF due to the loss of this notch filter, the filter stage is chosen to place after the gain stage. Fig. 9 illus-trates the schematic of the proposed dual-band notch filter. The impedance shown in the figure can be derived as
Fig. 9. Dual-band notch filter circuit.
Fig. 10. Simulated transmission coefficientS of the notch filter for different values ofL .
The notch frequencies of the filter can be obtained by letting the numerator equal null or
(9) which results in two transmission zeros and satisfying (10) (11) Also, from (8), the impedance contains a pole at
(12) In this study, we contrive that , , and correspond to 2.4, 5.2, and 3.9 GHz, respectively. We will determine the ap-propriate values of , , , and for the dual-band notch filter circuit in order to attenuate the WLAN interferers. It is noted that, after the decision of the positions of zeros and pole, we get three equations, i.e., (10)–(12), for the four filter compo-nents, which means that there is still one degree of freedom, let us say , left for the circuit design. Fig. 10 shows the transmis-sion coefficients of the notch filter with different values. As the value of increases, the in-band performance from 3.1 to 4.8 GHz will be improved; this means that we may use a larger inductance to maintain a better property in the target frequency
Fig. 11. Simulated transmission coefficientS of the notch filter for different values ofQ with L = 5 nH.
Fig. 12. (a) Schematic and (b) equivalent circuit of the active inductor with a resistor in the feedback path.
range. To achieve a 10-dB attenuation in both 2.4- and 5.2-GHz bands without suffering from deterioration of the in-band per-formance, the value of nH in the proposed notch filter will be chosen. On the other hand, the quality factor of the inductor also influences the performance of the filter, as can be observed from Fig. 11, where the transmission coefficients of the filter for different inductor values are shown. It is seen that a low quality factor will deteriorate the maximum attenuation of the notch filter. To obtain a 20-dB attenuation of the notch filter for the required specifications, the value of the quality factor must be higher than 100. In general, the negative-resistance cell by using cross-coupled transistors can be employed to amelio-rate the value of the on-chip inductor. However, the larger in-ductors with cross-coupled transistors will concurrently occupy an overlarge chip area and dc power. Therefore, we are inclined to utilize active circuitry to substitute for the integrated passive inductors.
C. Low-Power Active Inductors
The realization of inductances and is based on the active inductor with a feedback resistor proposed in [23].
Fig. 13. Complete schematics of the proposed second UWB LNA.
Fig. 12(a) and (b) illustrates the circuit schematic and corre-sponding equivalent circuit. Through a simple derivation, the components of the equivalent circuit can be obtained as
(13) (14) (15) (16) with , , and being the gate–source capacitance, output conductance, and transconductance of the corresponding transistors, respectively. In general, the quality factor of the ac-tive inductor can be promoted by decreasing the values of and . From (14), the use of the feedback resistor does reduce the value of the parallel conductance by introducing
the factor . In addition, a larger is
re-quired, as shown in (15), to get lower value of . However, this will increase the whole dc power consumption in the active inductor since is proportional to the current of transistors. To overcome this drawback, here we modify the active inductor circuit by using the gain-boosting technique [24] to achieve a small amount of dc current while maintaining a sufficient value. This is accomplished by using a cascode stage and
to replace the only common-source transistor , resulting in a new active inductor configuration, as shown in the complete schematic of the second UWB LNA in Fig. 13. The voltage gain in (15) can thus be substantially augmented and the value of will be obtained as
(17)
Fig. 14. Simulated quality factor of the proposed active inductorsL and L .
Therefore, a low-power active inductor is easily accomplished due to the use of the cascode gain-boosting stage with a feed-back resistor. Fig. 14 illustrates the simulated factor of the proposed active inductor, which shows that the active inductor exhibits a factor larger than 1000 at both 2.4- and 5-GHz bands. These high- inductors undoubtedly provide a larger at-tenuation at the interferer frequencies, as can be observed from Fig. 11. Only 0.55-mA (for ) and 0.8-mA (for ) dc currents are required in the second UWB LNA circuit shown in Fig. 13, which are smaller than those in the previous literature [23]–[25]. Moreover, it is obvious in (13) that the inductance of an active inductor is related to the transconductances, and thus, the bias currents, of the transistors. Consequently, the notch frequencies will be effectively tuned by adjusting the bias currents of the active inductor. The externally controlled bias voltages and in Fig. 13 are designed here for adjusting the bias currents to compensate the frequency shift due to the process variation.
Fig. 15. Microphotograph of: (a) the first UWB LNA with 0.782 0.8 mm die area and (b) the second UWB LNA with 0.92 0.85 mm die area.
Fig. 16. Measured and simulated power gain (S ) and input return loss (1=S ) of the first UWB LNA.
Fig. 17. Measured and simulated NF of the first UWB LNA.
For further design, these control voltages and can be utilized together with a feedback mechanism demonstrated in [6] and [7] and [26] and [27] for automatically calibrating the frequency drift of the notch filters.
IV. IMPLEMENTATION ANDMEASUREMENTS
The proposed out-band rejection UWB LNAs are designed and fabricated using the TSMC 0.18- m CMOS process. More-over, on-wafer probing is performed to measure the character-istics of the LNA circuits.
Fig. 18. Measured and simulated power gain (S ) and input return loss (1=S ) of the second UWB LNA.
Fig. 19. Measured and simulated NF of the second UWB LNA.
Fig. 20. MeasuredIP of the proposed UWB LNAs.
A. First UWB LNA With Capacitors and
For the first UWB LNA shown in Fig. 2, the width of the transistor m is optimized with 2.5-mW power dissi-pation to achieve good noise property. The size of the cascode transistor m is selected to be as large as possible to reduce its voltage headroom requirement, which is conducive to low-voltage operations. In addition, the design of the input network will engender the tradeoff between the input match and out-band rejection characteristics, which can be observed
in Figs. 3 and 5. Hence, it should be chosen cautiously to obtain a reasonably out-band rejection performances in the target input matching bandwidth. In this study, the components values of the
input network are nH, nH, nH,
pF, pF, pF, and
pF . The load consists of the on-chip inductor in series with the resistor to achieve flat gain over the whole band-width. The components values of the load are nH and . Moreover, the value of in this and the following LNAs is set as 50 to achieve output match for testing pur-poses. A die microphotograph of the first UWB LNA is shown in Fig. 15(a) and the die area including pads is 0.78 0.8 mm . The first UWB LNA drew a 2.8-mA dc core current from the 0.9-V supply voltage. The -parameters of the designed LNAs were measured using the Agilent 8510C vector network ana-lyzer. The simulated and measured results of power gain and input return loss are depicted in Fig. 16. The measured peak gain is 11.5 dB with a 3-dB bandwidth of 3.4 GHz from 2.8 to 6.2 GHz and the input return loss is better than 8.7 dB in the op-eration bandwidth. Moreover, due to the addition of the capac-itors and , extra transmission zeros are created and measured at 1.7 and 10 GHz. The NF was measured using the Agilent N8975A NF analyzer with Agilent 346C noise source. The simulated and measured NFs at the same bias condition are depicted in Fig. 17. It is seen that the minimum value of the measured NF is equal to 3.8 dB at 3.6 GHz.
B. Second UWB LNA With a Feedback Capacitor and Active Dual-Band Notch Network
For the second UWB LNA shown in Fig. 13, the components values of the active inductors are as follows: m ,
m, m, m,
m, m, m,
m, m, , and k . A
die microphotograph of the second LNA is shown in Fig. 15(b) and the die area including pads is 0.9 0.85 mm .
The total dc power of the second UWB LNA without an output buffer is 5 mW, drawn from 0.9- and 1.8-V power supply. The simulated and measured results of power gain and input return loss are depicted in Fig. 18. The measured peak gain is 15 dB from 3 to 4.8 GHz and the input return loss is better than 10 dB in the operation frequencies while the maximum rejec-tions at 1.8, 2.4, and 5.2 GHz are 55, 48, and 45 dB, respectively. The simulated and measured NFs are depicted in Fig. 19 and the measured minimum NF is 3.5 dB at 3.9 GHz. The input-referred 1-dB compression point ( ) of the proposed LNAs per-formed with an Agilent 83640B signal generator and 8564EC spectrum analyzer are depicted in Fig. 20. Minimum values of the measured in the first and second UWB LNAs are 16 and 18 dBm, respectively. The presented LNAs are com-pared with a recently published CMOS LNA and summarized in Table II.
V. CONCLUSION
In this paper, we proposed two UWB LNA configurations with out-band rejection ability and demonstrated them by using the TSMC 0.18- m CMOS process. Extra transmission zeros are created in the first UWB LNA due to the use of an LC input network with additional capacitors and for im-proving the higher and lower out-band performances, respec-tively. Furthermore, using a feedback capacitor and dual-band notch filter made of the low-power active inductors can achieve the maximum rejections of about 50 dB at the out-band inter-ferers, which was demonstrated in the proposed second UWB LNA. The measured results, including the power gain, return loss, and NF, agree quite well with the simulated results.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Implemen-tation Center (CIC), Taiwan, for the help of chip fabrication.
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Ching-Piao Liang was born in Changhwa, Taiwan,
in 1980. He received the B.S. and M.S. degrees in communication engineering from Yuan Ze University, Taoyuan, Taiwan, in 2003 and 2005, respectively, and is currently working toward the Ph.D. degree in communication engineering from National Chiao Tung University, Hsinchu, Taiwan.
His primary research interests include RF inte-grated circuits and monolithic microwave inteinte-grated circuits.
Tian-Jian Huang was born in Taichung, Taiwan, in
1983. He received the B.S. and M.S. degrees in com-munication engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2008, re-spectively.
His research focuses on RF integrated circuit de-sign.
(LTCC)-based RF components and modules, packaging effects of microwave circuits, vehicle collision warning radars, and communications in intelligent transportation systems (ITSs).
Dr. Chung was the treasurer of the IEEE Taipei Section (2001–2003) and the chairman of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Taipei Chapter (2005–2007). He was the recipient of the 2005 Out-standing Electrical Engineering Professor Award of the Chinese Institute of Electrical Engineering and the 2005 Teaching Excellence Award of National Chiao Tung University.
