A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

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1388 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

A 1.8-V 10-Gb/s Fully Integrated CMOS Optical

Receiver Analog Front-End

Wei-Zen Chen, Member, IEEE, Ying-Lien Cheng, and Da-Shin Lin

Abstract—A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applica-tions. The AFE is fabricated using a 0.18- m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV_(pp). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB and 3 dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is 12 dBm at a bit-error rate of10 12 with a

231 _{1 pseudorandom test pattern. Three-dimensional symmetric} transformers are utilized in the AFE design for bandwidth en-hancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 m 1796 m.

Index Terms—Limiting amplifier, optical receiver, three-dimen-sional symmetric transformer, transimpedance amplifier.

I. INTRODUCTION

T

HIS paper presents a 10-Gb/s fully integrated optical re-ceiver that incorporates both a transimpedance amplifier (TIA) and a limiting amplifier (LA) in a single chip. In con-trast with a conventional stand-alone TIA and a LA in sepa-rate packages [1]–[3], with our design the tiny photo currents generated from a photo detector can be on-chip amplified to a logic level to avoid off chip noise interference. To achieve both wide-bandwidth and high-gain design goals, three-dimensional (3-D) symmetric transformers [4] are utilized for bandwidth en-hancement. Compared to using two asymmetric or one planar symmetric counterparts in a fully differential architecture, 3-D symmetric transformers greatly reduce chip size requirements. In addition, an automatic gain-control circuit (AGC) is built in to adjust the conversion gain of TIA, avoiding any timing jitter in-duced by signal overload. To the authors’ knowledge, this is the first 10-Gb/s CMOS optical receiver AFE that integrates both a TIA and a limiting amplifier on a single chip.

Manuscript received June 3, 2004; revised December 22, 2004. This work was supported by Projects under Contract NSC-93-2220-E009-004, 93-EC-17-A-07-S1-001, ITRI/STC, and MediaTek Inc.

W.-Z. Chen is with the Integrated Circuits and System Laboratory, In-novative Package Research Center, Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu 300, Taiwan, R.O.C. (e-mail wzchen@alab.ee.nctu.edu.tw).

Y.-L. Cheng is with VIA Networking Technologies, Inc., Hsin-Tien, Taipei 231, Taiwan, R.O.C.

D.-S. Lin was with the Institute of Electronics, National Chiao-Tung Uni-versity, Hsin-Chu 300, Taiwan, R.O.C., and is currently with MediaTek Inc., Hsin-Chu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/JSSC.2005.845970

This paper begins with a description of the receiver AFE ar-chitecture and the use of inductive peaking for bandwidth en-hancement in the broad-band amplifier design. Then the novel 3-D fully-symmetric transformer utilized in the AFE design is explained. Compared to the prior designs of planar symmetric [5] or stacked asymmetric [6], [7] structures, the chip area needed can be drastically reduced using the proposed 3-D transformers. Following the narrative on the 3-D transformer, the designs of the transimpedance amplifier, the AGC and the limiting ampli-fier are discussed. The gain-bandwidth requirement and power optimization are investigated in detail as well. Finally, the ex-perimental results and our conclusion are presented.

II. RECEIVERANALOGFRONT-ENDARCHITECTURE

Fig. 1 shows the receiver architecture, which integrates a tran-simpedance amplifier, an AGC, and a limiting amplifier on a single chip [8]. To alleviate bandwidth degradation caused by the parasitic capacitors of the photo detector and the IC package, a regulated cascode (RGC) topology is adopted as the input stage [9]. The TIA architecture is in a pseudodifferential config-uration with a shunt-feedback for higher common-mode noise immunity. Furthermore, an AGC loop is built in to avoid data jitter induced by signal overload. As the TIA’s output swings below a predetermined voltage level, the tunable feedback re-sistors and are switched off and the TIA is operated in the high-gain mode for low-noise performance. Otherwise, the AGC is activated to keep the output amplitude constant. The AGC is composed of an amplitude detector, a comparator, and an integrator [10]. The comparator generates a compensating current to charge or discharge the integrator, and the conversion gain of TIA can be adjusted by reducing the shunting resistance in the input stage. The single-ended TIA output is converted to a fully differential signal by the amplifier in conjunction with the and low-pass filter.

The LA consists of a chain of five gain cells, an offset cancel-lation circuit , a low-pass feedback filter ( , , , , , , , ), and a current-mode output buffer to drive a 50- output load. In the feedback path, an additional gain cell is utilized to isolate the loading effects produced by the feedback network. and are MOS capacitors while is placed externally so it can have a lower _{dB frequency. The} gain stage is chosen as a compromise between gain and band-width requirements [8].

In this design, the TIA converts the photo currents generated from the photo detector into a voltage signal for post amplifica-tion, and the LA amplifies the voltage swing to a logic level for data recovery. The TIA is directly coupled to the LA on the chip,

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CHEN et al.: A 1.8-V 10-Gb/s FULLY INTEGRATED CMOS OPTICAL RECEIVER ANALOG FRONT-END 1389

Fig. 1. Optical receiver analog front-end architecture.

so no external coupling capacitors are required to avoid noise in-terference. Additionally, no broad-band matching networks are required in the input stage of the LA and the output stage of the TIA, resulting in reduced power dissipation and alleviating gain loss in the buffer stage. Herein, an automatic dc-level con-trol circuit is incorporated at the output stage of the TIA for dc matching between the TIA and the post amplifier.

III. 3-D TRANSFORMER

As the supply voltage continues to scale down along with the shrinkage of device size, the design of a wide-band and high-gain amplifier becomes more and more challenging due to the limitation of voltage headroom. An attractive solution for low-voltage broad-band amplifier design is by means of inductive peaking [11], which is applied in the designs of both the TIA and the LA. As the LA is composed of several gain stages and thus requires many bulky inductors, it occupies significant chip area. To achieve a low-cost design goal, a single innovative 3-D inverting-type transformer is utilized instead of two inductors in the fully differential gain stage.

Fig. 2(a) illustrates the 3-D transformer architecture and Fig. 2(b) displays its cross-sectional view. The metal wire winds downward with a right-half turn on the upper layer interleaved with a left-half turn on the adjacent lower layer and vice versa. When the wire reaches the bottom layer, it winds upward along the counter-path. The inverting type transformer is formed by center-tapping the middle point of the metal wire to a common-mode voltage, which is in this design.

The distributed and lumped-circuit models of the 3-D trans-former are illustrated in Fig. 3(a) and (b) respectively. Here, and represent the distributed resistance of and on metal layer . and denote the parasitic ca-pacitance of and between metal layer ,

Fig. 2. (a) 3-D symmetric transformer architecture. (b) Cross-sectional view of 3-D transformer.

, and substrate . The outer radius of the loops on the adjacent layers are offset by the metal width, so that loops on M6, M4, and M2 have the same radius, while that of loops on M5 and M3 is smaller. Thus, the parasitic capaci-tance between the adjacent metal layers can be eliminated.

In addition, and are reduced by increasing the distance between metal plates, and the electrical potential be-tween the top and bottom plates can be minimized [4]. Thus, the effective parasitic capacitance of the 3-D transformer can be reduced, resulting in better self-resonant frequency . Fur-thermore, by means of the interleaving architecture in a rela-tively smaller area, the effective inductance in each branch is

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(a) (b)

Fig. 3. (a) 3-D symmetric transformer distributed model. (b) 3-D symmetric transformer lumped model.

Fig. 4. Planar versus 3-D symmetric transformer performance comparison.

increased by enhancing the mutual coupling of the transformer , including the magnetic coupling on the same layer and adjacent layer – . Thus, the total wire length of the 3-D transformer can be reduced and configured in a small area.

Fig. 4 compares the simulated performance of the proposed 3-D transformer with that of a conventional planar counterpart by ADS momentum. For an inductor pair with an inductance of 2.85 nH in each branch, five turns, metal width m, metal spacing m, and an inner diameter of 110 m, the chip area of 3-D transformer is 47% smaller than that of its planar counterparts. Also it manifests a higher self resonant frequency (12 GHz versus 9 GHz) due to a smaller effective parasitic ca-pacitance [4]. Although its quality factor may be degraded due to the use of lower metal layer, along with higher series resis-tance introduced by vias, this is not an issue for bandwidth en-hancement applications.

IV. CIRCUITDESIGN

A. TIA Circuit Schematic

Fig. 5 provides a detailed circuit schematic of the TIA, which is composed of a regulated cascode (RGC) input stage

– , followed by a common-source gain stage – with a shunt feedback [9]. and are made up of poly re-sistors. The right half circuit – is a replica of TIA for

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Fig. 5. Transimpedance amplifier circuit schematic.

dc level and automatic gain control. The input common-mode voltage of the shunt-feedback gain stage is preset to by the local feedback amplifier, and is utilized as a reference voltage for the AGC.

The closed-loop conversion gain of the TIA can be approxi-mated by (1), shown at the bottom of the previous page, where

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(3) (4) (5) Here , denotes the total capaci-tance at the input node, denotes the total parasitic capaci-tance at the drain of , denotes the total parasitic capac-itance at the drain of , and is the parasitic capacitance at the output node of . The TIA is basically a fifth-order filter. The second term in (1) is contributed by the regulated cascode input stage, while the third term is determined by the shunt feed-back amplifier in the second stage. The RGC input stage pro-vides low input impedance in order to alleviate the severe band-width degradation caused by the parasitic capacitance of the photo detector [9]. In addition, the RGC input stage intro-duces another zero, , which can be placed at the roll-off region of the gain curve for bandwidth extension.

On the other hand, the pole is introduced by the parasitic capacitance at the output of the common gate gain stage. The

zero, which is generated by an inductive peaking technique, can be placed at the vicinity of to alleviate its impact on bandwidth limitations. Thus, (1) can be simplified as

(6) where

(7) Since the RGC input stage is transparent to the photo current by choosing , it turns out that the TIA bandwidth can be extended to using shunt feedback and inductive peaking. At the same time, is chosen for a maximally-flat Butterworth response.

The price paid in the RGC input stage is the extra noise intro-duced by the RGC feedback amplifier. The input-referred noise can be derived as [9]

(8) where is the noise factor of the MOSFET, is the parasitic capacitance at the input node, and and respectively

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rep-1392 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Fig. 6. Amplitude detector for AGC.

resent the total parasitic capacitance at gate of M5 and drain of M1. To mitigate this drawback, the transconductance of M2 is chosen to be as large as possible to reduce the input-referred noise coming from M2 and M3’s thermal noise [9]. Addition-ally, the tail current source needs to be sufficiently large to tol-erate the input dynamic range.

B. Automatic Gain Control Circuit

In the high-input current state, the common-source amplifiers in the second stage of the TIA may be driven into the deep triode region, which results in overload-induced data jitter. To miti-gate this effect, the feedback resistors are adjusted by turning on the shunting resistance of and . On the contrary, when the input current is below a predetermined threshold level, the shunting transistors are turned off for low-noise operation.

Fig. 6 shows the detailed circuit schematic of the AGC, which is comprised of a peak detector (M1, M2, C1, C2) followed by an operational transconductance amplifier (OTA) for amplitude comparison – , a lossy integrator stage ( , , ), and a low-pass filter ( , ) [10]. The loop bandwidth of the AGC is mainly determined by . Here acts as the nonlinear rectifying element on the output signal of the TIA. The threshold voltage of AGC is determined by . When the input photo current is low, the OTA is fully switched and the is pulled low. Thus, the feedback resistor and in the TIA core are switched off for high-gain and low-noise perfor-mance. On the contrary, as the photo current becomes higher, the TIA’s output node, , is driven to be lower. Thereafter, the OTA – would sense the voltage difference and gen-erate the compensation current to charge or discharge the inte-grator, whose output is utilized to control the turn-on resis-tance of and in the TIA core. Fig. 7 shows the simulated transimpedance gain and output swing (single ended) under var-ious input current levels by the automatic gain control loop. The figure reveals a conversion gain of 450 in the nominal case and 150 in the high-current state.

C. Limiting Amplifier Circuit Schematic

For an LA design, how to determine the number of gain stages with gain-bandwidth tradeoffs is an important issue. Assuming

Fig. 7. Transimpedance gain and output swing versus input current.

each gain cell is identical and approximated by a two-pole am-plifier, and its conversion gain can be described by , where

(9) Here denotes the small-signal dc gain, is the corresponding damping factor, and is the natural frequency. Let the 3-dB bandwidth of a single-stage amplifier be , then the 3-dB bandwidth of the stage’s cascaded limiting amplifier is re-duced to . It can be derived that

(10) For a flat response, we want to have . Also, the bandwidth requirement for a single-stage amplifier in terms of the cascaded amplifier’s 3-dB bandwidth can be derived as

(11) On the other hand, the gain requirement of the individual stage, , in terms of the LA’s conversion gain, , can be ex-pressed as

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Fig. 8. Gain cell of limiting amplifier.

Under the above assumptions, one can easily derive the required unity gain bandwidth ( ) for the individual stages in terms of the targeted and , where

(12) To achieve a conversion gain of 40 dB and 3-dB bandwidth of 10 GHz , a five-stage limiting amplifier demands a of 24 GHz per stage, which is feasible for a 0.18 m CMOS tech-nology. Since the last two stages of cascaded amplifiers behave more like current switches as the gate drive of differential pairs becomes larger and larger, the bandwidth degradation caused by the last two stages becomes negligible [12]. The actually re-quired would be more relaxed. On the other hand, although the for each stage can be reduced by choosing a larger , the total power consumption and noise would be increased grad-ually [2], [8]. Thus, a five-stage architecture is chosen in this design.

Fig. 8(a) shows the LA’s core circuit, which is based on the Cherry–Hooper circuit architecture [13] with inductive peaking. By shunt-shunt feedback, all the nodes in the cir-cuit become low impedance nodes for wide bandwidth oper-ations. The input stage of the LA is shown in Fig. 8(b), and it functions as both an input buffer and an offset subtractor. The offset voltage derived from the low-pass loop filter is con-verted to a compensation current and subtracted from the input signal. In addition, the input/output common-mode voltages of the transconductance and transimpedance amplifiers are de-signed to be equal for dc-coupling as the cascaded amplifiers are hooked up.

For the wide-band multistage amplifier, each gain cell is designed with an emphasis on minimizing power dissipation under the targeted specifications. To simplify the analysis, the

transformer for inductive peaking is neglected temporarily. The voltage gain of each cell can be derived as

(13) where (14) (15) Assuming (16) then we have (17) (18) Given the supply voltage (1.8 V), overdrive voltage mV , and conversion gain of each stage (8 dB),

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Fig. 9. Normalized! =I as a function of current ratioK.

Fig. 10. Simulated gain-bandwidth response of the optical receiver AFE.

the feedback resistor can be expressed in terms of and by substituting (17) for (13). Also, the normalized 3-dB bandwidth can be obtained by substituting (17) and (18) into (15). Taking power dissipation into consideration, the normalized is chosen as a figure of merit and its relation to is illustrated in Fig. 9. It can be shown that the achievable bandwidth at the cost of becomes saturated as approaches 1.6. It corresponds to

and mA per stage in this design. From another per-spective, if is too large, the achievable bandwidth becomes limited by the input pole of the transimpedance gain stage.

V. SIMULATION ANDEXPERIMENTALRESULTS

As the TIA and the LA are fully integrated on a single chip, it becomes difficult to measure and characterize their gain and bandwidth performance separately in this prototype. Fig. 10 shows the simulated gain response of the TIA, the post limiting amplifier (LA), and the optical receiver AFE when the two com-ponents are hooked up. The figure reveals that the conversion gain and the of the TIA and the LA are 53 dB , 8 GHz, and 40 dB, 8.4 GHz, respectively. As the insertion loss of the inter-stage buffer is about 6 dB, the AFE provides a total gain of 87 dB , and the 3-dB bandwidth is 7.6 GHz.

Fig. 11. 10-Gb/s bit-error rate performance with2 01 PRBS input.

Fig. 12. (a) 2.5-Gb/s eye diagram with016:8 dBm input power BER = 10 .y-scale: 43.9 mV/div, x-scale: 67.5 ps/div. (b) 5-Gb/s eye diagram with 016:2 dBm input power at BER = 10 .y-scale: 43.7 mV/div, x-scale: 30.6 ps/div.

With an Oepic P5030A photo detector, whose responsivity is 0.85 A/W and parasitic capacitance is about 0.15 pF, the mea-sured sensitivity of the optical receiver AFE at 10 Gb/s is about 12 dBm for a bit-error rate of less than . The bit-error rate performance at 10 Gb/s is summarized in Fig. 11. The tol-erated power level is up to 0 dBm by the built-in automatic gain

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Fig. 13. (a) 10-Gb/s eye diagram with012 dBm input power (sensitivity level) atBER = 10 .y-scale: 43.6 mV/div, x-scale: 16.6 ps/div. (b) 10-Gb/s eye diagram with 0 dBm input power (overload level) @BER = 10 .y-scale: 50 mV/div,x-scale: 16.5 ps/div.

control scheme. The input-referred noise current, , of the op-tical receiver is derived from its sensitivity performance. As

Sensitivity dBm (19) where is the responsivity of the photo detector, and is the extinction ratio. The corresponding is approximately 7.3 A .

Fig. 12(a) and (b) illustrate the measured eye diagrams at 2.5 and 5.5 Gb/s, respectively. The data jitter is about 43.5 ps (pp) for 2.5 Gb/s and 50.3 ps (pp) for 5.5 Gb/s. In these two cases the input sensitivity of the AFE is up to 16 dBm for bit-error rate less than . Fig. 13(a) illustrates the mea-sured 10-Gb/s eye diagram at the input power of sensitivity level 12 dBm , Fig. 13(b) illustrates the measured 10-Gb/s eye diagram when the input power is overloaded. The measured jitter is about 29.8 and 38.8 ps, respectively. In all cases the test pattern is pseudorandom bit stream (PRBS). Operating under a 1.8-V supply, the power dissipation is 210 mW, of which 40 mW is consumed by the output buffer. Fig. 14 illustrates the chip photograph. Fabricated in a 0.18- m CMOS technology, the chip size is 1028 m 1796 m, of which the TIA occupies

Fig. 14. Optical receiver AFE chip photograph.

a chip area of 330 m 550 m. The area that the LA occupies on the chip is 1170 m 865 m.

VI. CONCLUSION

This paper describes the design of a fully integrated 10-Gb/s optical receiver analog front-end using a generic 0.18- m CMOS technology. The optical AFE provides a conversion gain of 87 dB and a 3-dB bandwidth of about 7.6 GHz. The bandwidth is limited by the transimpedance amplifier for low-noise operation. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and a wide bandwidth is achieved by means of shunt feedback and induc-tive peaking. Instead of using bulky planar inductors or two asymmetric 3-D inductors, our design utilizes an innovative, fully symmetric 3-D transformer for inductive peaking in each differential pair. With this innovation, the chip area can be greatly reduced. Moreover, an AGC is built in to alleviate over-load-induced data jitter. Our proposed architecture is suitable for both low-cost and low-voltage applications.

ACKNOWLEDGMENT

The authors would like to thank CIC for chip manufacturing, and Dr. Li-Ren Huang and Dr. Chia-Ming Tsai at ITRI/STC for measurement support.

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Wei-Zen Chen was born in Yun-Lin, Taiwan,

R.O.C., on August 24, 1970. He received the B.S., M.S., and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1992, 1994, and 1999, respectively.

After graduation, he worked for Industrial Tech-nology Research Institute (ITRI), Hsin-Chu, Taiwan, on RF integrated circuit design. From 1999 to 2002, he was with the Department of Electrical Engineering, National Central University, Chung-Li, Taiwan. In 2002, he joined the Department of Elec-tronics Engineering, National Chiao-Tung University, where he is currently an Assistant Professor. His research interests are integrated circuits and systems for high speed networks and wireless communications.

Dr. Chen is a member of Phi Tau Phi.

Ying-Lien Cheng was born in Taiwan in 1979. She

received the B.S. and M.S. degree in electrical engi-neering from National Central University, Chung-Li, Taiwan, R.O.C., in 2001 and 2003, respectively.

Currently, she is an Engineer in the R&D Division of VIA Networking Technologies, Inc. Her research interest is CMOS high-speed circuit design for data communication.

Da-Shin Lin was born in Changhua, Taiwan,

R.O.C., in 1976. He received the B.S. degree in mechanical engineering from National Central University, Chung-Li, Taiwan, in 2001, and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan, in 2004.

Currently, he is an Engineer in the R&D Division of MediaTek, Inc. His research interests are focused on CMOS optical receiver design.