Abstract—Two low-leakage resistor-shunted diode strings are developed for use as power clamps in silicon–germanium (SiGe) BiCMOS technology. The resistors are used to bias the deep N-wells, significantly reducing the leakage current from the diode string. A methodology for selecting the values of the bias resistors is presented. For further reduction of the leakage current, an alternate design is presented: the resistor-shunted trigger bipolar power clamp. The power-clamp circuits presented herein may be used in cooperation with small double diodes at the I/O pins to achieve whole-chip electrostatic-discharge protection for RF ICs in SiGe processes.
Index Terms—Electrostatic discharge (ESD), modified resistor-shunted diode string (MR diode string), MR trigger bipolar ESD power clamp, power-rail ESD clamp circuit, resistor-shunted diode string (RS diode string), RS trigger bipolar ESD power clamp.
I. INTRODUCTION
T
HE SILICON–GERMANIUM (SiGe) BiCMOS technol-ogy with great RF performance of SiGe HBT has been recognized as one of the best technology solutions for wireless applications. Electrostatic-discharge (ESD) protection [1], [2], which has been a very important reliability issue in IC produc-tion, should be taken into consideration during circuit design and chip layout. In order to protect internal circuits from ESD damage, the power-rail ESD clamp circuit needs to be designed with the ESD diodes at I/O pins to achieve whole-chip ESD protection [3]. Fig. 1 shows the typical on-chip RF ESD-protection scheme in which the ESD diodes at I/O pins are codesigned with the power-rail ESD clamp circuit [4]–[6]. ESD stress may have positive or negative voltages on an input or output pin with respect to the grounded VDD or VSS pins. For comprehensive ESD verification, the pin-to-pin ESD stress and VDD-to-VSS ESD stress had also been specified to verify the whole-chip ESD robustness. Thus, the ESD clamp circuit between the power rails is very helpful for protecting RF I/O pins and RF core circuits against ESD damage [6]. Diode string is one solution that has been applied in the power-rail ESD clamp circuits [7], [8], which is operated in forward-biasedManuscript received January 11, 2006; revised July 25, 2006. This work was supported by the National Science Council (NSC), Taiwan, R.O.C., under Contract NSC95-2221-E-009-290.
The authors are with the Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: mdker@ieee.org).
Color versions of Figs. 11–21 are available at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2006.883153
Fig. 1. Typical on-chip RF ESD-protection scheme with codesigned input ESD diodes and the power-rail ESD clamp circuit. The diode string has been applied in the power-rail ESD clamp circuit.
condition to discharge ESD current. Therefore, it can sustain a very high ESD level in a small silicon area.
However, the main drawback for using diode string as power-rail ESD clamp circuit is leakage current, especially at high temperatures. A parasitic vertical p-n-p bipolar junction tran-sistor (BJT) exists in the conventional P+/N-well diode with the common grounded P-type substrate. This parasitic vertical p-n-p BJT causes high leakage current along the diode string [7]–[9], especially at high temperatures. Some modified designs on the diode string to reduce leakage current had been reported in [8], which are referred to as the cladded diode string, boosted diode string, and cantilever diode string. However, those de-signs, which have been verified in a bulk CMOS technology, still have high leakage current (∼mA) at the temperature of 125◦C [9]. In SiGe processes, deep trench (DT) has been used to reduce substrate leakage current of diode string [10], [11]. With the DT and N+ buried layer in SiGe process, the parasitic vertical open-base p-n-p BJT can be formed in the diode string because the N+ buried layer is floating [11]. As a result, the substrate leakage current is lower than that of the conventional P+/N-well diode string in CMOS processes.
Although Fig. 1 is applicable not only to RF circuits, this paper focuses on power-rail ESD clamp-circuit design in SiGe BiCMOS process, which is always dedicated to RF applica-tions. The importance of effective power-rail ESD clamp cir-cuits for RF ESD-protection design in SiGe BiCMOS processes has been demonstrated in [1], [2], [12], and [13]. Moreover, the study on diode strings used in power-rail ESD clamp circuits with reduced leakage current has been reported for RF ESD-protection applications [10], [11]. With the effective power-rail 1530-4388/$20.00 © 2006 IEEE
Fig. 2. Cross-sectional view of the conventional diode string with four stacked diodes in CMOS technology.
Fig. 3. Cross-sectional view of the four-stage diode string and its parasitic base–emitter tied p-n-p BJTs in a triple-well CMOS process. ESD clamp circuits, the sizes of ESD-protection devices at the
RF input node can be further reduced without sacrificing ESD robustness. Therefore, the impact of the ESD-protection circuit on the RF performance can be minimized. However, the main concern on the effective power-rail ESD clamp circuits de-signed with diode strings is the leakage issue in circuit normal operations, especially under a high-temperature environment.
In this paper, four power-rail ESD clamp circuits for RF ESD-protection design in SiGe BiCMOS technology are pro-posed, which are the resistor-shunted diode string (RS diode string), RS trigger bipolar ESD power clamp [14], modified resistor-shunted diode string (MR diode string), and MR trigger bipolar ESD power clamp. In the new proposed RS and MR diode strings, extra biases are applied to the deep N-well regions of the RS and MR diode strings to reduce leakage cur-rent. The characteristics of these new proposed power-rail ESD clamp circuits are also compared with those of the conventional diode string in a 0.18-µm SiGe BiCMOS process.
II. REVIEW ONDIODESTRINGS
A. Conventional Diode String in CMOS Technology
The cross-sectional view of the conventional four-stage diode string is shown in Fig. 2. Because of the parasitic vertical p-n-p BJTs in the forward-biased diodes, holes are injected from the P+ emitter into the N-well base, and part of holes are swept to the P-substrate collector. Consequently, the substrate leakage current in the conventional diode string is formed. If the current gain of the parasitic vertical p-n-p BJT is greater than unity, the total blocking voltage across the diode string cannot be linearly increased by increasing the number of stacked diodes in the diode string. This implies that more diodes would be needed to provide the desired blocking voltage. To reduce the leakage current of the conventional diode string, three modified designs had been reported in [7] and [8].
B. Modified Diode String to Reduce Leakage Current
A modified design to reduce leakage current by using triple-well technologies had been reported in [10]. Fig. 3 shows the cross-sectional view of the four-stage diode string with its parasitic base–emitter tied p-n-p BJTs in a triple-well CMOS process. The base–emitter junction cannot be forward-biased because the base and emitter are tied together. As a result, holes will not be injected into the base region of the parasitic vertical p-n-p BJT, and the current will flow through the P-well region to the next diode. Thus, the base–emitter tied configuration can effectively suppress the substrate leakage current. The substrate leakage current can be kept very small before the triple-well diode string is turned on.
III. NEWPROPOSEDRS DIODESTRING ANDRS TRIGGER BIPOLARESD POWERCLAMP
A. RS Diode String
The cross-sectional view of the new proposed RS diode string in a SiGe BiCMOS process is shown in Fig. 4. Compared with the conventional P+/N-well diode string, the new proposed RS diode string uses deep N-wells to isolate the P-wells from the common grounded P-substrate. An extra bias through the resistor R is applied through the N-well to the deep N-well to reduce leakage current into substrate. The structure and equivalent circuit of the RS diode string with its parasitic n-p-n BJTs are shown in Fig. 5.
In the new proposed RS diode string, each deep N-well is connected to the anode through a bias resistanceR. The con-nection of deep N-wells to the anode causes the parasitic n-p-n BJTs in the RS diode string to be slightly turned on. The current generated from the slightly turned-on n-p-n BJT in the diode will flow into the next diode in the RS diode string rather than into the common grounded P-substrate. Therefore, the leak-age current into the substrate is not increased in this new design.
Fig. 4. Cross-sectional view of the new proposed RS diode string with four stacked diodes.
Fig. 5. Structure and equivalent circuit of the new proposed RS diode string with four stacked diodes. When the RS diode string is used as the power-rail ESD clamp circuit, the anode is connected to VDD, and the cathode is grounded.
When the RS diode string is used as the power-rail ESD clamp circuit, the anode is connected to VDD, and the cathode is grounded. The total current flowing into the RS diode string should equal to that flowing out from the RS diode string. The total leakage current of the RS diode string is
Itotal leakage= IC1+ IC2+ IC3+ IC4+ I2 (1)
where all currents have been indicated in Fig. 5. Under normal circuit operating conditions, the RS diode string was designed so as to minimize its leakage current. In the new proposed RS diode string, the parasitic BJT1 was designed to be operated in the saturation mode while the parasitic BJT2, BJT3, and BJT4 were designed to be operated in the forward-active mode under normal circuit operating conditions. The emitter current (IE) and collector current (IC) of each BJT can be expressed
in terms of its base–emitter voltage(VBE) and base–collector
voltage(VBC) as IE= IS αF (eVBE/VT− 1) − I S(eVBC/VT− 1) (2) and IC= IS(eVBE/VT− 1) − IS αR (eVBC/VT− 1). (3)
The base–collector voltage(VBC) of BJT1, base–emitter
volt-age(VBE) of each BJT, and VDD are derived as
VBC1= R × I1 (4)
VBEn= VT[ln(IEn+ 1) − ln(IS)] , forn = 1 ∼ 4 (5)
and VDD= 4 n=1 VT[ln(IEn+ 1) − ln(IS)] (6)
where IS is the saturation current,VT is the thermal voltage,
αF is the common base current gain in the forward-active
mode, αR is the common base current gain in the
reverse-active mode, and IE and IC are the emitter and collector
current, respectively [15]. According to (4)–(6), the emitter and collector currents of BJT1 become
IE1= IS αF (IE1+1) IS −1 −IS(eRI1/VT−1) (7) and IC1= IS (IE1+1) IS −1 − IS αR (eRI1/VT−1). (8) It is straightforward that IE1= 1−IS αF − IS(eRI1/VT− 1) 1−α1 F . (9) From the equivalent circuit, the collector current of BJT2 has current-gain relationship with the emitter current of BJT1, since the emitter current of BJT1 is the base current of BJT2, and BJT2 is in the forward-active mode. Therefore,IC2is given by
IC2= β2IB2= β2IE1 (10)
where β2 is the common emitter current gain of BJT2.
Similarly, the collector currents of the BJT3 and BJT4 are
IC3= β3IB3 = β2β3IE1 (11)
and
IC4= β4IB4= β2β3β4IE1 (12)
whereβ3andβ4are the common emitter current gain of BJT3
Fig. 6. Power-rail ESD clamp circuit with the diode-triggered HBT in a SiGe BiCMOS process [16].
resistanceR is the sum of the four collector currents, which can be derived as
I1=IC1+IC2+IC3+IC4=IC1+(β2+β2β3+β2β3β4)IE1.
(13) Therefore, the total leakage current of the RS diode string becomes Itotal leakage= (1 + β2+ β2β3+ β2β3β4)IE1 = (1 + β2+ β2β3+ β2β3β4) × 1−IS αF − IS(eRI1/VT− 1) 1−α1 F =f(R). (14)
The total leakage current of the RS diode string is a function of the bias resistanceR and the common emitter current gain
β of each BJT. The minimum leakage current can be found
by equaling the differentiated expression of the total leakage with respect to R to zero. With this method, the optimized bias resistance to achieve the minimized leakage current can be found from (14).
B. RS Trigger Bipolar ESD Power Clamp
The power-rail ESD clamp circuit with the diode-triggered HBT in a SiGe BiCMOS process had been reported [16], as shown in Fig. 6. However, the leakage (or standby) current of this power-rail ESD clamp circuit is the main concern for low-power or portable applications. To further reduce the leakage current, the new proposed RS trigger bipolar ESD power clamp is shown in Fig. 7 with its equivalent circuit.
The leakage current of the RS trigger bipolar ESD power clamp can be derived in the same way. For the SiGe HBT, the base and collector current can be expressed as functions of
VBE. In the RS trigger bipolar ESD power clamp, the parasitic
BJT1 is in the saturation mode while the parasitic BJT2, BJT3, and BJT4 are in the forward-active mode under normal circuit operating conditions. The collector and emitter currents of each parasitic BJT are the same as (2) and (3), respectively. The volt-age equations in the equivalent circuit of Fig. 7 are given by
VBC1= R × I1 (15)
VBEn= VT[ln(IEn+ 1) − ln(IS)] , forn = 1∼ 4 (16)
VDD− 4
n=1
VT[ln(IEn+ 1) − ln(IS)] = VBE_HBT. (17)
Fig. 7. New proposed RS trigger bipolar ESD power clamp and its corre-sponding equivalent circuit.
Equation (17) is different from that of the aforementioned RS diode string because the cathode of the RS diode string, which is connected to ground in the pure RS diode string, is now connected to the base of HBT in this design. All currents of the RS diode string will finally flow into the base of HBT and the resistanceRoin this circuit configuration. The total leakage current along the RS trigger bipolar ESD power clamp can be expressed by
Itotal leakage= VBE_HBT
Ro + IB+ IC. (18)
The base and emitter currents of the SiGe HBT are given by
IB= qADpen 2 i WENde eVBE_HBT/VT (19) and IC= qADnbn 2 i WBNab eVBE_HBT/VT (20)
where Dpe is the diffusion coefficient of holes in the emitter,
Ndeis the donor concentration in the emitter,WEis the depth
of the emitter,Dnb is the diffusion coefficient of electrons in
the base, Nab is the acceptor concentration in the base, WB
is the basewidth,ni is the intrinsic carrier concentration,q is
the charge on an electron, andA is the area of the emitter/base junction [17].
The resistanceRobetween the base of SiGe HBT and ground will affect the total leakage current. Thus, there are two design parameters, R and Ro, in the RS trigger bipolar ESD power clamp for minimizing leakage current.
IV. MODIFIEDDESIGN OFMR DIODESTRING ANDMR TRIGGERBIPOLARESD POWERCLAMP
A. MR Diode String
The cross-sectional view of the new proposed MR diode string in a SiGe BiCMOS process is shown in Fig. 8. Similar to the RS diode string proposed in last section, the new proposed MR diode string uses deep N-wells to isolate the P-wells
Fig. 8. Cross-sectional view of the new proposed MR diode string with four stacked diodes.
Fig. 9. Equivalent circuit of the MR diode string with four stacked diodes in a SiGe BiCMOS process. When the MR diode string is used as the power-rail ESD clamp circuit, the anode andVbiasare connected to VDD, and the cathode is grounded.
from the common grounded P-substrate. Several extra biases through the biasing resistances are applied to the deep N-wells to reduce the leakage current into substrate. The structure and equivalent circuit of the MR diode string with parasitic n-p-n BJTs is shown in Fig. 9.
In the new proposed MR diode string, each deep N-well is connected to the anode through the bias resistances. The common emitter current gain(β) of the parasitic BJT whose collector is connected to a bias resistance can be further reduced in this configuration because each bias resistance connects the collector of a parasitic BJT and the collector of the next one. When current flows through the bias resistance, the voltage drop across it reduces the collector–emitter voltage of the parasitic BJT. As a result, the common emitter current gains of BJT1, BJT2, and BJT3 can be reduced. When the MR diode string is used as the power-rail ESD clamp circuit, the anode andVbias
are connected to VDD, and the cathode is grounded.
The total leakage current and the BJT1’s collector voltage are given by
Itotal leakage= I1+ I3 (21)
I3= IB1 (22)
and
V1= Vbias− R × I1. (23)
In the new proposed MR diode string, the parasitic BJT1, BJT2, and BJT4 were designed to be operated in the saturation mode, while the parasitic BJT3 was designed to be operated in the forward-active mode under normal circuit operating conditions. The following inequality has been demonstrated by the experi-mental result to validate this design:
R × I1< VBE1. (24)
The emitter and collector currents of the parasitic BJTs are the same as those in the RS diode string, which are given in (2) and (3). The currentI1in Fig. 9 is given by
I1= IC1+ I2 (25)
and
I2= IC2+ IC3. (26)
Based on (25) and (26),I1becomes
I1= IC1+ IC2+ IC3. (27)
The base–emitter voltage (VBE) of each parasitic BJT is
given by
VBEn= VT[ln(IEn+ 1) − ln(IS)] , for n = 1∼ 4. (28)
The base–collector voltage(VBC) of BJT1 is
VBC1= R × I1. (29)
The emitter and collector currents of BJT1 can be obtained with similar derivation as in the RS diode string and are given by
IE1= IS αF (IE1+ 1) IS − 1 − IS(eRI1/VT− 1) (30) and IC1= IS (IE1+ 1) IS − 1 − IS αR (eRI1/VT− 1). (31)
The base–collector voltage (VBC) and base–emitter voltage
(VBE) of BJT2 are VBC2= R × I1+ R × I2− VBE1 = R(I1+ I2) − VTln IE1+ 1 IS (32)
and
VBE2= VT[ln(IE2+ 1) − ln(IS)] . (33)
The emitter and collector currents of BJT2 are given by
IE2= IS αF (IE2+1) IS −1 −IS ISe R(I1+I2) VT IE1+1 −1 (34) and IC2= IS (IE2+1) IS −1 − IS αR ISe R(I1+I2) VT IE1+1 − 1 . (35) Since BJT3 is in the forward-active mode, its collector current can be derived as IC3= β3IB3= β3IE2 = β3 IS αF (IE2+1) IS −1 −IS ISe R(I1+I2) VT IE1+1 −1 . (36) With its collector shorted to the emitter, BJT4 is in the satu-ration mode. The anode is connected to VDD, and the cathode is grounded when the MR diode string is used as the power-rail ESD clamp circuit. In this case, the base–collector voltage (VBC) and base–emitter voltage (VBE) of BJT4 are equal.
Therefore, the emitter and collector currents of BJT4 can be simplified as IE4= IS αF − IS (IE4+ 1) IS − 1 (37) and IC4= IS−αIS R (IE4+ 1) IS − 1 . (38) After considering all parasitic BJTs, the total leakage current of the MR diode string is given by
Itotal leakage=I1+I3=I3+IC1+IC2+IC3=IE1+IC2+IC3.
(39) According to (30), (35), and (36), the total leakage can be cal-culated. The common emitter current gain(β) of the parasitic BJT is reduced by the bias resistances in the MR diode string. As a result, the total leakage current of the MR diode string can be further reduced. Substituting (30), (35), and (36) forIE1,
IC2, andIC3in (39) yields Itotal leakage = IS αF (IE1+1) IS −1 −IS(eRI1/VT− 1) + IS (IE2+1) IS −1 − IS αR ISe R(I1+I2) VT IE1+1 −1 + β3 IS αF (IE2+1) IS −1 −IS ISe R(I1+I2) VT IE1+1 −1 = f(R). (40)
Fig. 10. New proposed MR trigger bipolar ESD power clamp and its equiva-lent circuit.
The minimum total leakage current of the MR diode string can be found by choosing an appropriate bias resistance with the aid of (40). The total leakage current can be further reduced by using more diodes and bias resistances in the MR diode string.
As shown in (14) and (40), the expressions for the leakage current of the two proposed diode strings are functions of the bias resistance (R), saturation current (IS), common emitter
current gain(β), common base current gain (α), emitter cur-rent of each BJT, and the curcur-rent flows through each resistor. Each aforementioned parameter is also a function of the bias resistor (R). Moreover, the aforementioned parameters are dependent to each other. Therefore, it is very complicated to directly derive a simple expression on the optimum resistance, which can minimize the leakage current by hand calculation. To obtain the optimum resistance, methods such as numerical analysis by computer calculation should be resorted. If the exact parasitic n-p-n device parameters can be given, the optimal resistance to have a minimal leakage current can be obtained by HSPICE simulation.
B. MR Trigger Bipolar ESD Power Clamp
The fourth new proposed power-rail ESD clamp circuit is the MR trigger bipolar ESD power clamp, which is shown in Fig. 10 along with its equivalent circuit. The MR trigger bipolar ESD power clamp is also believed to have lower leakage current than the conventional diode string. The total leakage current of the MR trigger bipolar ESD power clamp can be obtained with similar derivation as that in the RS trigger bipolar ESD power clamp. The total leakage current along the MR trigger bipolar ESD power clamp is given by
Itotal leakage= VBER_HBT
o + IB+ IC (41)
where VBE_HBT,IB, andICare expressed in (17), (19), and
(20), respectively.
The resistanceRobetween the base of SiGe HBT and ground will affect the total leakage current. Similar to the RS trigger
Fig. 11. DCI–V characteristics of the conventional diode string with dif-ferent numbers(n = 2, 3, and 4) of stacked diodes under the temperature of 25◦C.
Fig. 12. DCI–V characteristics of the RS diode string with different numbers (n = 2, 3, and 4) of stacked diodes under the temperature of 25◦C and the bias
resistance of 10 kΩ.
bipolar ESD power clamp, there are two design parameters
R and Ro in the MR trigger bipolar ESD power clamp for minimizing leakage current.
V. EXPERIMENTALRESULTS
The four new proposed on-chip power-rail ESD clamp cir-cuits had been fabricated in a 0.18-µm SiGe BiCMOS process. The conventional diode string shown in Fig. 2 had also been fabricated in the same process with the same diode layout dimensions for comparison. During the measurement, the cath-odes of the RS diode string/MR diode string and the p-substrate were grounded by two separated channels, so that the cathode current and substrate current can be monitored separately. Each diode in this paper has the same device dimension ofW/L = 40µm/12 µm in layout pattern. The dc characteristics of the conventional diode string, RS diode string, and MR diode string with different numbers (n = 2, 3, and 4) of stacked diodes are shown in Figs. 11–13, respectively. TheVbiasand anode of the
MR diode string were shorted in the dc current–voltage (I–V ) measurement.
The RS and MR diode strings have lower substrate leakage current than that of the conventional diode string, because there are biases applied through the bias resistances into the deep
N-Fig. 13. DC I–V characteristics of the MR diode string with different numbers(n = 2, 3, and 4) of stacked diodes under the temperature of 25◦C and the bias resistance of 10 kΩ. The Vbiasand anode of the MR diode string were shorted in dcI–V measurement.
Fig. 14. Relationship between bias resistance(R) and total leakage current of RS and MR diode strings with four stacked diodes and the bias condition of VDD= Vbias= 1.8 V, which were measured at the temperatures of 75◦C and 125◦C, respectively.
well. For the circuit applications with VDD of 1.8 V, the sub-strate leakage current in the RS diode string (shown in Fig. 12) with four stacked diodes can be two orders of magnitude lower than that of the conventional diode string, as shown in Fig. 11.
The relationship between bias resistance (R) and the total leakage current through the RS diode string and MR diode string with four stacked diodes(n = 4) and the bias condition of VDD= Vbias= 1.8 V at different temperatures is shown in
Fig. 14. The total leakage current through the RS diode string or MR diode string(n = 4) is increased when the temperature is increased from 75 ◦C to 125◦C. As shown in Fig. 14, the total leakage current of the MR diode string is about one order of magnitude lower than that of the RS diode string under the condition of the same bias resistance and temperature. The total leakage current of the RS diode string and MR diode string can be minimized by selecting the appropriate bias resistance with the aid of (14) and (40), respectively. From the measured results of the test chip fabricated in a 0.18-µm SiGe BiCMOS process, the RS and MR diode strings with four stacked diodes have the minimized leakage current at 125 ◦C by using the
Fig. 15. Comparison on total leakage currents of the conventional diode string, RS diode string, and MR diode string with four stacked diodes(n = 4) andR = 10 kΩ at 125◦C.
Fig. 16. TLP-measuredI–V characteristics of the conventional diode string with different numbers(n = 1, 2, 3, and 4) of stacked diodes.
bias resistance of 10 and 20 kΩ, respectively. The relationships between the voltage across the conventional diode string, RS diode string, and MR diode string with four stacked diodes and their total leakage current at 125◦C are compared in Fig. 15. TheVbiasin the MR diode string is 1.8 V in this measurement.
All bias resistances used in this comparison is 10 kΩ for the RS and MR diode strings. The MR diode string has the lowest leakage current, while the conventional diode string has the highest leakage current. As illustrated in Fig. 15, the total leakage current of the MR diode string is about one order of magnitude lower than that of the conventional diode string in the voltage range from 0.1 to 1.9 V.
With a bias resistance of 10 kΩ, the ESD robustness of the conventional diode string, RS diode string, and MR diode string with different numbers of stacked diodes has been investigated by using the transmission-line-pulse (TLP) generator with a pulsewidth of 100 ns. The TLP-measuredI–V characteristics of the conventional diode string, RS diode string, and MR diode string with different numbers (n = 1, 2, 3, and 4) of stacked diodes are shown in Figs. 16–18, respectively. The dependence of the secondary breakdown current (It2) of the conventional
Fig. 17. TLP-measured I–V characteristics of the RS diode string with different numbers(n = 1, 2, 3, and 4) of stacked diodes.
Fig. 18. TLP-measuredI–V characteristics of the MR diode string with different numbers(n = 1, 2, 3, and 4) of stacked diodes.
diode string, RS diode string, and MR diode string on the number (n) of stacked diodes is shown in Fig. 19. The Vbias
and anode of the MR diode string were shorted together in the It2 measurement. The It2 of the RS diode string and MR diode string are larger than that of the conventional diode string when the number of stacked diodes exceeds two. This implies that the new proposed RS diode string and MR diode string have not only lower leakage current but also higher ESD robustness, as compared to the conventional diode string. With an It2 of greater than 4 A, the new proposed RS diode string and MR diode string with four stacked diodes can sustain the human-body-model ESD stress of∼6 kV. As shown in Fig. 19, the It2 of the RS diode string and MR diode string does not decrease as the number of stacked diodes increases. Consequently, the number of stacked diodes in the RS and MR diode strings can be reasonably increased to get a higher blocking voltage without degradation in ESD robustness.
A comparison of the total leakage current among the SiGe HBT triggered by the conventional diode string, RS diode string, and MR diode string with four stacked diodes at 125◦C under differentRo resistances is shown in Fig. 20, where all
Fig. 19. Dependence of secondary breakdown current (It2) of the conven-tional diode string, RS diode string, and MR diode string on the number of stacked diodes. TheVbiasand anode of MR diode string were shorted in the It2 measurement.
Fig. 20. Comparison on the total leakage currents of the SiGe HBT triggered by the conventional diode string, RS trigger bipolar ESD power clamp, and MR trigger bipolar ESD power clamp under differentRo resistances. All the bias resistances are 10 kΩ with four stacked diodes, bias condition of VDD= 1.8 V, and temperature of 125◦C.
the bias resistances are 10 kΩ, and VDD is 1.8 V. As shown in Fig. 20, The total leakage current of the new proposed RS trigger bipolar ESD power clamp and MR trigger bipolar ESD power clamp is about two orders of magnitude lower than that of the HBT triggered by the conventional diode string with the same number of stacked diodes and the same HBT device dimension.
As compared with the conventional string, the leakage current is reduced by using the RS diode string. According to Fig. 5, the potentials at the collector electrodes of the four parasitic BJTs are equal. Each base in the parasitic BJT is connected to the emitter of the preceding parasitic BJT, and the base of the parasitic BJT1 is connected to the anode. As a result, the parasitic BJT1 is in the saturation mode while the parasitic BJT2, BJT3, and BJT4 are in the forward-active mode under normal circuit operating conditions. Therefore, the BJT current will be amplified by a factor ofβ + 1 through each forward-active parasitic BJT. Consequently, the leakage
Fig. 21. TLP-measured I–V curves of the SiGe HBT triggered by the conventional diode string, RS trigger bipolar ESD power clamp, and MR trigger bipolar ESD power clamp with four stacked diodes andR = Ro= 10 kΩ. current increases as the number of forward-active parasitic BJTs increases. For the purpose of decreasing the number of forward-active parasitic BJTs, the modified design of the MR diode string is proposed and shown in Fig. 9. The common emitter current gain (β) of the parasitic BJT whose collector is connected to a bias resistance can be further reduced in this configuration, because the voltage drop across the bias resis-tance reduces the collector–emitter voltage of the parasitic BJT. In the MR diode string, the parasitic BJT1, BJT2, and BJT4 are in the saturation mode while only the parasitic BJT3 is in the forward-active mode under normal circuit operating conditions. With only one forward-active parasitic BJT, the leakage current is minimized by the new proposed MR diode string.
When the SiGe HBT is applied as the ESD clamp device, the HBT should be taken into consideration to evaluate the leakage current. Because the leakage current of the RS diode string is not minimized, the SiGe HBT forms the fifth base–emitter junction in series with the existing four base–emitter junctions between VDD and VSS. Thus, the leakage current of the RS diode string can be further reduced by using the RS trigger bipolar ESD power clamp. On the other hand, since the leakage current of the MR diode string is already minimized, applying the SiGe HBT cannot further reduce the leakage current sig-nificantly. Therefore, as shown in Figs. 15 and 20, the leakage current of the MR diode string, RS trigger bipolar ESD power clamp, and MR trigger bipolar ESD power clamp is almost the same, which is around 1.5–2 nA.
The TLP-measuredI–V curves of the SiGe HBT triggered by the conventional diode string, RS trigger bipolar ESD power clamp, and MR trigger bipolar ESD power clamp with four stacked diodes andR = Ro= 10 kΩ are compared in Fig. 21, where the current is normalized to the emitter area of the SiGe HBT. As shown in Fig. 21, the MR trigger bipolar ESD power clamp has the lowest turn-on resistance, while the HBT triggered by the conventional diode string has the highest turn-on resistance. ESD clamp device with lower turn-turn-on resistance would have lower voltage across itself during ESD stress. Thus, the voltage on the input node of the circuit to be protected would be lower during ESD stress. Accordingly, the MR trigger
Fig. 22. Power-rail ESD clamp circuit designed with diode string for mixed-voltage applications [12].
bipolar ESD power clamp can sustain the highest It2 per unit emitter area, which implies to have the highest ESD robustness among these three designs. To sustain a higher ESD level, the SiGe HBT with a larger device dimension should be used in power-rail ESD clamp circuits.
VI. COMPARISONWITHPREVIOUSLY REPORTEDDIODESTRINGS
A recently reported power-rail ESD clamp circuit designed with diode string for mixed-voltage applications is shown in Fig. 22 [12]. According to Fig. 22, the power-rail ESD clamp circuit consists of a two-stage Darlington clamp network using a SiGe HBT trigger with base open and SiGe HBT clamp element. In a power-rail ESD clamp circuit, the clamp device must have a high breakdown voltage to sustain the voltage between VDD and VSS, while the trigger device should have a low breakdown voltage to immediately initiate the base current into the clamp device before the voltage across the power-rail ESD clamp circuit damages the core circuits. Thus, the trigger HBT with low breakdown voltage and high cutoff frequency (fT) and the ESD clamp HBT with high breakdown voltage
and low cutoff frequency(fT) are used in this power-rail ESD clamp circuit.
When the collector-to-emitter voltage of the HBT is below the breakdown voltage, no current flows through the trigger HBT. Therefore, with base grounded, the clamp HBT is not turned on under normal circuit operating conditions. Under ESD condition, the voltage on VDD exceeds the collector-to-emitter breakdown voltage(BVCEO), and current flows into the
base of the ESD clamp HBT to discharge the ESD current from VDD to VSS. The resistorRballastis used for resistor ballasting
to improve ESD robustness. The trigger voltage of the power-rail ESD clamp circuit can be varied by changing the number of series varactors.
Another ESD-protection circuit designed with diode string for mixed-voltage interface, which is referred to as the snubber-clamped diode string, is shown in Fig. 23 [13]. In this
mixed-Fig. 23. ESD-protection circuit designed with diode string for mixed-voltage interface [13].
voltage interface ESD-protection circuit, the diode string is placed between the I/O pad and VDD to protect the 3.3-V/5-V mixed-voltage interface circuit. The diode string forms a multi-stage BJT amplifier in a Darlington configuration. The bipolar base current is amplified by each successive stage when each stage is in the forward-active mode. To break the Darlington effect of amplifying the leakage current, three additional snub-ber diodes are placed on the base electrodes of the parasitic BJTs. With the snubber diodes, the base voltage of the para-sitic BJT is clamped, and the leakage current amplification is limited. Any elements, such as resistors, p-channel MOSFETs, or diodes, which can prevent a forward-active condition of the parasitic BJT, can be used to limit the Darlington amplification. The snubber-clamped diode string, RS diode string, and MR diode string proposed in this paper utilize the same concept to reduce the leakage current, which is preventing the parasitic BJTs of the diode string from being in the forward-active mode to amplify the leakage current. In the snubber-clamped diode string, the base potential is boosted by the snubber diodes, while in the RS diode string and MR diode string, the collector potential is lowered by the voltage drop of the bias resistor.
VII. CONCLUSION
Four new designs to minimize the leakage current of the power-rail ESD clamp circuit realized by diode string for RF circuits had been proposed and verified in a 0.18-µm SiGe BiCMOS process. With an additional extra bias circuit to supply current into the N-well of the diodes in the RS diode string, the overall leakage current of the RS diode string can be reduced. The leakage current can be further reduced and minimized by using the new proposed MR diode string, which is introduced by the similar idea. The design equations to minimize the leakage current in the RS diode string and MR diode string have also been derived in this paper. By selecting the appropriate bias resistance, the total leakage current of the RS diode string and MR diode string can be kept much smaller than that of the conventional diode string. This makes the RS diode string and MR diode string more promising as the on-chip power-rail ESD clamp circuit. Moreover, the RS diode
ACKNOWLEDGMENT
The authors would like to thank the support of wafer fab-rication in a 0.18-µm SiGe BiCMOS process from TSMC. Especially, they would also thank Dr. T.-C. Ong, J.-H. Lee, and Y.-H. Wu of TSMC, Hsinchu, Taiwan, R.O.C. The authors would also like to thank the reviewers for their valuable sugges-tions and comments to improve this publication.
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University. He has published more than 270 technical papers in international journals and conferences in the field of reliability and quality design for CMOS integrated circuits. He has also proposed many inventions to improve the reliability and quality of integrated circuits, which have been granted with 113 U.S. patents and 123 R.O.C. (Taiwan) patents. He has been invited to teach and offer consultations on reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.; Silicon Valley, San Jose, CA; in Singapore; and in the Mainland China. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in thin-film-transistor liquid-crystal display.
Dr. Ker was a recipient of the Dragon Thesis Award from Acer Foundation, the National Invention Award in Taiwan in 2005 for one of his patents on electrostatic-discharge protection design, and many research awards from ITRI, National Science Council, and National Chiao-Tung University. He was selected as one of the Ten Outstanding Young Persons in Taiwan by the Junior Chamber International in 2003 and as a Distinguished Lecturer in the IEEE CAS Society for the period 2006-2007. He has been the Foundation President of Taiwan ESD Association since 2001. He has also served as a member of the technical program committee and a session chair of numerous international conferences. He is currently a Associate Editor of the IEEE TRANSACTIONS ONVLSI SYSTEMS.
Yuan-Wen Hsiao (S’03) was born in Taiwan,
R.O.C., in 1982. He received the B.S. degree from the Department of Electronics Engineering, National Chiao-Tung University (NCKU), Hsinchu, Taiwan, R.O.C., in 2004. He is currently working toward a Ph.D. degree at the Institute of Electronics, NCKU.
His current research interests include RF circuit design and ESD-protection design for RF ICs. He is also an honorary member of the Phi Tau Phi Society.
Woei-Lin Wu received the B.S. degree from the
Department of Electrophysics, National Chiao-Tung University (NCKU), Hsinchu, Taiwan, R.O.C., in 2003 and the M.S. degree from the Institute of Elec-tronics, NCKU, in 2005.
In 2005, she joined the Sunplus Technology Cor-poration, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C., as a Designer. Her main research interests include on-chip ESD-protection designs.
![Fig. 6. Power-rail ESD clamp circuit with the diode-triggered HBT in a SiGe BiCMOS process [16].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7617031.130925/4.891.207.293.103.258/power-clamp-circuit-diode-triggered-sige-bicmos-process.webp)
![Fig. 22. Power-rail ESD clamp circuit designed with diode string for mixed- mixed-voltage applications [12].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7617031.130925/10.891.522.773.102.365/power-clamp-circuit-designed-diode-string-voltage-applications.webp)
