Abstract— The instability of the gate bias and drain bias stresses is observed at high temperature in amorphous InGaZnO thin-film transistors (a-IGZO TFTs). The transfer characteristics of a-IGZO TFTs at different temperatures are also investigated in this paper. The transfer curve exhibits an apparent subthreshold current stretchout phenomenon at high temperature. The stretchout phenomenon becomes more serious with the increase of the temperature. In addition, thermally induced holes are accumulated by the negative gate voltage and get trapped in the gate dielectric or at the dielectric/channel interface at high temperature. The negative threshold voltage shifts with stress time and this is because the trapped holes induce more electrons. For drain bias stress at high temperature, the transfer curve exhibits an apparent shift during drain bias stress at high temperature compared with the same at room temperature. At high temperature, thermally induced holes are trapped in the gate insulator, especially near the drain region. Capacitance-voltage measurements have been used to prove the nonuniform hole-trapping phenomenon. Furthermore, the simulation of the capacitance-voltage and current-voltage curves also have been applied to confirm the hole-trapping distribution. The obtained results clarify that the instability is caused by nonuniform hole-trapping phenomenon.
Index Terms— Bias stress, indium gallium zinc oxide (IGZO), technology computer-aided design (TCAD), temperature, thin-film transistors (TFTs).
I. INTRODUCTION
R
ECENTLY, portable electronic products have combined display [1], [2], memory [3]–[7], and logic devices. Amorphous oxide thin-film transistors (TFTs), such as indium-gallium-zinc oxide (IGZO) TFTs have attracted considerable Manuscript received November 12, 2013; revised January 17, 2014 and February 26, 2014; accepted April 16, 2014. Date of current version May 16, 2014. This work was supported by the National Science Council of Taiwan under Contract NSC 102-2120-M-110-001. The review of this paper was arranged by Editor H.-S. Tae.G.-W. Chang and Y.-H. Tai are with the Department of Photonics, Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: [email protected]; [email protected]).
T.-C. Chang is with the Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan, the Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 701, Taiwan, and also with the Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (e-mail: [email protected]).
J.-C. Jhu, Y.-E. Syu, and F.-Y. Jian are with the Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: [email protected]; [email protected]; [email protected]).
T.-M. Tsai, K.-C. Chang, and Y.-C. Hung are with the Institute of Materials Science and Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (e-mail: [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2319105
attention for their use in active matrix displays due to their high mobility (∼10 cm2/V-sec) [8], largeON/OFFcurrent ratio (>108) [9], fairly good uniformity, and good transparency. Furthermore, the low process temperature and low cost are desirable for large flat panel display applications [10], [11]. In particular, a-IGZO TFT has been recognized as a potential device for switching/driving TFTs in active matrix organic light-emitting diode displays (AMOLED), which require TFTs with high current drivability to achieve uniform brightness. The stability of TFT under long-term current operation is crit-ical in the case of current-driven AMOLED displays because it influences pixel signal level/emission intensity [12]–[14]. For the a-IGZO TFTs to act as the display’s backplane electronics, reliability and stability are very important. In previous studies, only the instability caused by gas ambient [15]–[19] and light issue [20], [21] have been proposed as critical issues in the application of display industry. However, TFT in active matrix display is usually influenced by heat from the light source and operated conditions [22], [23]. It should be carefully investigated, because in a real operating situation the effect of temperature influences the TFT under applied bias. Moreover, the reliability issue for a-IGZO TFT operated on turn-OFF state (VG = 0 V and VD > 0 V) stress at high temperature
has not yet been studied. In this paper, we investigate gate bias and drain bias stresses at the different temperatures and explain the stress effect with assistance of band diagrams. In addition, we discuss the abnormal subthreshold leakage current with temperature dependence of the a-IGZO TFT. Finally, the capacitance-voltage measurement and technology computer-aided design (TCAD) simulation system are used to confirm the proposed mechanism.
II. EXPERIMENTALSETUP
Bottom gate coplanar a-IGZO TFTs were produced on a glass substrate in this paper. Plasma-enhanced chemical vapor deposition (PECVD)-derived SiOx (300 nm) film as the gate insulator was grown at 370 °C over the patterned Ti/Al/Ti trilayer gate electrodes. The Ti/Al/Ti source/drain electrodes were formed by sputtering and then patterned into the dimensions of channel width (W ) from 5 to 30 μm and channel length (L) of 10 μm. A 30-nm-thick a-IGZO film was deposited by dc magnetron sputtering system at room temperature using a target of In:Ga:Zn= 1:1:1 in atomic ratio. The plasma discharge power was 300 W under the pressure of 5 mTorr ambiance of O2/Ar gas mixture at the ratio of 6.7%. 0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
Fig. 1. ID–VG curves of a-IGZO TFTs under negative gate bias (VG= −30 V) at (a) 300 K and (b) 400 K.
After defining the active region, the devices were capped with a 200 nm SiOx layer by PECVD at 170 °C and sequentially annealed in oven at 330 °C for 2 h. The electrical properties of the a-IGZO TFTs were analyzed using Agilent B1500A Semiconductor Device Analyzer in a dark environment. The threshold voltage (VT) is defined as the gate voltage when the
normalized drain current (NID= ID×L/W) reaches 10−10A.
III. RESULTS ANDDISCUSSION
Fig. 1(a) and (b) shows the transfer characteristics of as-fabricated a-IGZO TFTs in the experiment of negative bias temperature instability (NBTI) stress with Vg= −30 V at 300 and 400 K, respectively. The stress time is from 150 to 1000 s. At 300 K, the transfer curves hardly shift under negative gate bias stress, which is consistent with previous reports [24]–[26]. The invariability of curves can be explained by the lack of holes in channel. There are no holes that could be attracted into gate insulator by the negative gate bias. On the other hand, when the temperature is increased to 400 K with −30 V stress, the VT under stress time of
1000 s shifts significantly to the negative direction by 20.21 V compared with the VT at the initial state, that is, stress time
is 0 s. At high temperature with negative gate bias stress, the thermal induced holes from defect states are accumulated by the negative gate voltage and trapped in the gate dielectric or at the dielectric/channel interface. The trapped holes induce more electrons to shift the curves negatively with stress time. In general, a-IGZO-TFTs have no holes in channel [24], [25]. However, after negative gate bias stress at 400 K, the transfer curves clearly shift to left direction. Moreover, the transfer curves stretch out and abnormal subthreshold leakage current is significant before negative bias stress at 400 K as shown in Fig. 1(b) with black line. Next, we discuss the unique behavior of the subthreshold leakage current for a-IGZO TFTs at high temperature. Fig. 2 shows the transfer characteristics of a-IGZO TFTs at the different temperatures between 300 and 450 K. As seen in this figure, the I –V curves shift to the negative direction and drain current (ID)
raises with increasing temperature. It is well known for oxide semiconductors that the free electrons in the materials are mainly due to the detrapping from sub-bandgap trap states and the generation of oxygen vacancies [27], [28]. Thermally excited electrons are detrapped from relatively shallow sub-bandgap trap states. In addition, more oxygen vacancies are induced by thermal excitation, therefore, more free electrons
Fig. 2. ID–VGcurves of a-IGZO TFTs at the different temperatures between 300 and 450 K.
Fig. 3. (a) Schematic of the device structure with basic device operation. (b) Energy band diagram at 300 K.
are generated. The lower VT observed at the higher
temper-ature can be because of these free electrons from the sub-bandgap trap states and generated along with the oxygen vacancies [29], [30]. Furthermore, the significant abnormal subthreshold leakage current that is observed at 400 K and this stretchout phenomenon becomes more serious with increasing the temperature. However, this temperature effect is reversible in that the transfer characteristics at 300 K can be restored after the high-temperature measurements.
While the IGZO TFT is turned on at 300 K, a positive bias was applied to the gate and drain was given a constant positive bias as shown in Fig. 3(a). Electrons could overcome the barrier between source and channel and move to drain through channel as shown in Fig. 3(b). Unlike those at 300 K, the transfer characteristics at 400 K can be separated into stretchout and normal regions by VT as can be seen from
Fig. 2. The mechanisms for these two distinctive regions are proposed in Fig. 4(a) and (b). As shown in Fig. 4(a), when the gate voltage is below VT, the trap-induced thermal-generation
holes moves to the source side owing to the transverse electric field, the holes accumulate at the source region that leads to the source side barrier lowering. The lowering enhances electrons injection from the source and causes an apparent subthreshold leakage current. When VG is larger than VT, the
Fig. 4. Energy band diagram of proposed mechanisms for these two distinctive regions (a) gate voltage is below VT and (b) gate voltage is above
VT at 400 K.
Fig. 5. (a) Normalized current–voltage characteristics at the different drain voltages. (b) Energy band diagram with the different drain voltages.
the a-IGZO and source. The holes accumulation on the source-side would flow to the source when the a-IGZO TFTs turned on. The barrier height becomes much lower with the increase of the gate voltage; therefore, the holes cannot accumulate at source-side, as shown in Fig. 4(b).
The status of hole accumulation is further examined by mea-suring the normalized current–voltage (VG–ID) characteristics
at the different drain voltages, as shown in Fig. 5(a). At 400 K, the subthreshold leakage current increases significantly with the drain bias increase. Furthermore, the stretchout voltage is more negative when the drain bias becomes larger and the subthreshold leakage current saturates when the drain voltage (VD) above 5 V. It is implied that the thermal-induced holes
could drift to the source barrier owing to the transverse electri-cal field by the drain bias. The holes accumulate at the source region which leads to the source side barrier lowering. The lower source side barrier enhances electrons injection from the source and causes an apparent subthreshold leakage current. When the drain bias increase, the large transverse electrical field results in the more holes drift to the source region, as shown as Fig. 5(b). This phenomenon makes the source barrier lowering become more serious. Thus, the subthreshold leakage current raises with the drain bias increase. On the other hand, when the drain bias is larger than 5 V, the source barrier lowering saturates since all the thermal excited holes drift to the source region. Therefore, the stretchout phenomenon saturates when the drain bias is above 5 V.
In addition to NBTI, the reliability issue for a-IGZO TFT operated in the turn-OFF state (VG = 0 V and VD > 0 V)
at high temperature was investigated. Fig. 6(a) shows the transfer curves of ID–VG for a-IGZO TFT before and after
Fig. 6. Characteristics of transfer curves ID–VG before and after drain bias stress at (a) 300 K and (b) 400 K.
Fig. 7. (a) Schematic diagram of hole-trapping mechanism under after bias stress. (b) Energy band diagram from A to A.
drain bias stress at 300 K with a bias stress condition of
VD = 25 V and VG,S = 0 V for 50–1000 s. The electrical
curves almost exhibit no shift under positive drain bias stress. By contrast with drain stress at 300 K, Fig. 6(b) shows the electrical curves for a-IGZO TFT before and after drain bias stress at 400 K operated under the similar stress condition. At 400 K, the transfer curves stretch out in the subthreshold region. The stretchout phenomenon is caused by the same reason as discussed in Fig. 2. After stress at 400 K, the VT
shifts significantly to the negative Vg direction by 1.68 V. The subthreshold swing (SS) before drain stress and after 1000 s drain stress is 347 and 376 mV/dec, respectively. The subthreshold swing fractional change (SS) value is 29 mV/dec which is defined bySS (mV/dec) = SSa− SSb, where SSa refer to after stress and SSb refer to before stress, respectively. The negative Vg shift with slight degradation of SS indicates that the state creation is negligible. It is suggested that electrons are attracted to the drain electrode owing to the positive drain bias, as shown in Fig. 7(a). The thermal-induced holes are repelled simultaneously to the gate dielectric layer by positive drain voltage and trapped in the gate dielectric or dielectric/channel interface. Fig. 7(b) shows the corresponding band diagram from A to A in Fig. 7(a). The trapped holes in the gate dielectric lead to channel barrier lowering. The channel barrier lowering enhances electrons injection from source to channel which makes it easier to turn on TFT. Furthermore, the barrier lowering near drain side is more serious than that of the source side because of the larger electrical field of the former. However, the VT is decided on
the highest barrier side. Therefore, the VT is determined by the
Fig. 8. (a) CGS− VG and (b) CGD− VG transfer characteristics of a-IGZO TFT before and after drain bias stress.
can be explained by the lack of holes in channel. Therefore, the instability of drain bias stress is more pronouonced at the high temperature.
To further clarify the instability effect, the capacitance-voltage (C–V ) measurement of a-IGZO TFT was used to prove the proposed mechanism. Fig. 8(a) shows the CGS–VG
curves before and after drain bias stress (VD= 25 V) at 400 K.
In the CGS–VG measurement, capacitance measurement high
(CMH) is applied to the gate electrode and the source electrode is connected to capacitance measurement low (CML). After 1000 s drain stress, VT variation with no degradation of SS
is observed, which is similar to the ID–VG transfer curves as
shown in Fig. 6(b). In CGS−VG measurement, the amount of carrier is measured from source region to channel as shown the inset of Fig. 8(a). The barrier lowering induced easier carrier injection to the channel that results in a smaller VT. Therefore,
the CGS−VGcurve after drain bias stress shifts in parallel with
original curve to the negative direction. However, the CGD−VG
curves, that is, CMH is applied to the gate electrode while the CML is connected to the drain electrode, exhibit an obvious degradation by hump effect and negative VT shift after the
drain bias stress, as shown in Fig. 8(b). The result indicates this only occurs in the channel near the drain region. As larger bias is applied at the drain electrode, a stronger vertical electric field exists in the channel near this area. This result shows the severe hole-trapping phenomenon near the drain region which induces serious barrier-lowering in the channel near drain region as shown in Fig. 7(b). The serious barrier-lowering induces hump effect of CGD−VG curve. Therefore, the
two-stage degradation in CGD–VG curve which includes hump
effect and negative VT shift occurs after drain bias stress at
the high temperature.
According to the above discussion, the hump effect of
CGD−VGcurve is correlated to the gate-drain vertical electrical
field. To further examine the proposed mechanism, TCAD sim-ulation system was employed. Fig. 9(b) shows the simsim-ulation results of CGD−VG curves for the nonuniform hole-trapping
model after drain bias stress. Fig. 9(a) shows the simulation device structure. In this simulation, hole trapping in the dielec-tric is 1 × 1015/cm3 and the concentration of hole injection near the drain is adjusted to 1.2 × 1016/cm3. Combined with the experimental data, we can find that the simulation of hump behavior matches with the experimental results after drain bias stress. In addition to CGD−VG curves, the transfer curve of ID–VG is simulated as shown in Fig. 9(b). The VT after stress
shifts to the negative direction by 1.79 V compared with the
Fig. 9. (a) Schematic of simulation device structure and the simulation results of electrical properties of (a) CGD− VGand (b) ID− VG curves.
VT at the initial state and SS value is 35 mV/dec. The
curve shifts to left with slight SS degradation is consistent with the experimental results shown in Fig. 6(b). These simulation results further verify the characteristic degradation after drain bias stress, which is also proved by our nonuniform hole-trapping model.
IV. CONCLUSION
The transfer characteristics of a-IGZO TFTs at the different temperatures and the instability of bias stress at high tem-perature have been investigated. The transfer curve exhibits an apparent subthreshold current stretchout phenomenon at high temperature and this phenomenon becomes more serious with the increase of the temperature. The negative gate bias temperature instability experiment has been used to prove the thermally induced holes generation. In addition, the transfer characteristics with different drain voltages have been used to confirm the status of holes accumulation. Moreover, the temperature instability of the drain bias can be observed at high temperature. During drain bias stress at high tempera-ture, thermally induced holes are trapped in gate insulator, especially near the drain region. The C–V measurement and the simulation results are applied to prove the nonuniform hole-trapping phenomenon. These results clarify the temper-ature is a critical parameter on the operation of a-IGZO TFT device.
ACKNOWLEDGMENT
This work was performed at the National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in Kaohsiung-Pingtung area, NSYSU Center for Nanoscience and Nanotechnology, and assisted by AU Optronics.
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Geng-Wei Chang is currently pursuing the Ph.D. degree with the Department of Photonics and the Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan.
He is currently a Visiting Research Scholar with Texas A&M University, College Station, TX, USA. His current research interests include thin-film tran-sistor, nonvolatile memory, and solar cell.
Ting-Chang Chang (SM’12) is currently a Chair Professor with the Department of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan. He has authored more than 300 articles in SCI journals. He holds 54 U.S. patents and 114 Taiwan patents.
Jhe-Ciou Jhu is currently pursuing the Ph.D. degree with the Institute of Physics, National Sun Yat-sen University, Kaohsiung, Taiwan.
Tsung-Ming Tsai received the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2005.
He is currently an Associate Professor with the Department of Materials and Optoelectronic Sci-ence, National Sun Yat-sen University, Kaohsiung, Taiwan. His current research interests include resis-tance random access memory, supercritical criti-cal carbon dioxide technology, and next-generation memory technology.
Yong-En Syu received the Ph.D. degree in physics from National Sun Yat-sen University, Kaohsiung, Taiwan, in 2012.
He is currently with Taiwan Semiconductor Man-ufacturing Company, Tainan, Taiwan.
Ya-Chi Hung received the M.S. degree from the Institute of Materials Science and Engineer-ing, National Sun Yat-sen University, Kaohsiung, Taiwan, in 2012.
