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行政院國家科學委員會補助專題研究計畫成果報告
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※※※※※※※※※※※※※※※※※※※※※※※
※ 電漿製程對 N-型及 P-型金氧半場效電晶體 ※
※ 之損傷機制研究 ※
※ Mechanism of Plasma Process Induced Damage ※
※ On N-type and P-type MOSFET ※
※※※※※※※※※※※※※※※※※※※※※※※※
計畫類別：■個別型計畫 □整合型計畫
計畫編號：NSC 89－2215－E－009－074－
執行期間： 88 年 11 月 01 日至 89 年 07 月 31 日
計畫主持人：崔秉鉞
共同主持人：無
本成果報告包括以下應繳交之附件：
□赴國外出差或研習心得報告一份
□赴大陸地區出差或研習心得報告一份
□出席國際學術會議心得報告及發表之論文各一份
□國際合作研究計畫國外研究報告書一份
執行單位：國立交通大學 電子工程學系
中 華 民 國 89 年 10 月 10 日
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行政院國家科學委員會專題研究計畫成果報告
電漿製程對 N-型及 P-型金氧半場效電晶體之損傷機制研究
Mechanism of Plasma Pr ocess Induced Damage on N-type and
P-type MOSFET
計畫編號：NSC 89-2215-E-009-074
執行期限：88 年 11 月 01 日至 89 年 07 月 31 日
主持人：崔秉鉞 交通大學電子工程學系
共同主持人：無
計畫參與人員：黃誌鋒、劉沛傑、陳鵬森 交通大學電子研究所
一、中文摘要 本計畫著重在接觸窗 之介電層蝕刻 之電漿製程損傷機制研究•P-型電晶體所 受損傷比 N-型電晶體嚴重，且損傷程度與 接觸窗之總面積成正比•大部份損傷經後 段製程後轉為隱性缺陷，對元件基本性質 影響不大，但在熱載子可靠度測試時會產 生影響•介電層蝕刻的安全天線比例低於 導體蝕刻，此為未來嵌入式製程所必需慎 重面對的課題• 關鍵詞：電漿製程損傷、天線比例、介電 層蝕刻 Abstr actPlasma process induced damage from high-density plasma dielectric etcher was studied. It was observed that PMOS devices were damaged more readily than NMOS devices. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at conductor etch. Thus, plasma damage during dielectric etch in high-density plasma system must be considered carefully.
Keywor ds: plasma process induced damage,
antenna ratio, dielectric etch
二、緣由與目的 電漿製程已廣泛應用於積體電路(IC)製 造上•由於電漿系統中充滿加速的帶電粒 子，會對製造中的元件造成許多種損傷 [1]• 這之中最中要的是電荷堆積(charge build-up)•由於電荷堆積會被曝露在電漿中 的 導 體 面 積 放 大 ， 又 稱 為 天 線 效 應 (antenna effect) [2-26]•在過去十餘年中， 大部份的研究均著重在導體的電漿蝕刻製 程上 [2-17]，也就是複晶矽層及金屬層• 近年來，因為接觸窗(contact hole)及通 孔(via hole)的深寬比逐漸增加 [27]，介電 層蝕刻在深次微米製程所扮演的角色也愈 來愈受重視•但是針對介電層蝕刻的電漿 損商所進行的研究卻不多[28-32]，對損傷 機制的了解更是有限•本專題計畫即針對 以高密度電漿系統執行介電層蝕刻所造成 的天線效應進行研究•包括完整的測試結 構設計、多項元件參數的測量、可靠度的 評估等等•希望對介電層蝕刻造成的損傷 機制有更多的認識，了解對元件的影響， 並評估其嚴重程度• 三、結果與討論 I. 實驗設計 本計畫採用 0.25 微米 CMOS 製程，閘 氧化層厚度為 5nm，通道長度及寬度分別 為 0.24um 及 5.0um•NMOS 的閘極為 N 型 複晶矽，PMOS 閘極為 P 型複晶矽•複晶 矽對閘氧化層的天線比例是 2000•接觸窗 的數量分別是 125、625、1275 及 2875，相 對應的天線比例是 7、37、75 及 170•接觸
3 窗直徑及間距都是 0.3um，有些元件用不同 的接觸窗大小及間距，以了解對損傷的影 響•接觸窗蝕刻是在電感耦合式的高密度 電漿系統中進行•所有元件的閘極都從第 一層金屬開始並聯到保護二極體以避免金 屬蝕刻及後續製程的影響•圖一是測試結 構的示意圖• II. 實驗結果 我們首先測量複晶矽天線比為 10,000 而接觸窗只有一個的元件，所有參數均顯 示元件沒有受到損傷，因此 2,000 的天線比 例是安全的設計•如果不同的接觸窗設計 有元件受損的跡象，必然是因為接觸窗製 程所造成• 接下來測量不同接觸窗數量的 NMOS 及 PMOS 元件的基本直流參數包括低電場 閘極電流(Ig)、臨界電壓(Vt)、互導(gm)及 次臨界斜率(S)•NMOS 的所有參數都看不 出與接觸窗數量的關係，只有 PMOS 的 Ig 顯示出接觸窗數量愈多則高漏電流的元件 愈多，如圖二所示•這顯示 Ig 是最敏感的 直流參數•PMOS 比 NMOS 易受到製程損 傷可能與損傷發生時的電壓極性有關• 其次，我們選擇另一組元件施加電應力 (FN stress)使流過閘氧化層的電量達到 10 mC/cm2 以 偵 測 是 否 有 電 中 性 的 損 傷 存 在• PMOS 的 Ig及 Vth都顯示出接觸窗數 量愈多分佈愈廣，如圖三(左)及(右)所示• 這表示有些損傷在後段製程轉變為電中性 的隱性缺陷 (hidden defect)•又因為施加應 力後 Vth 的改變受接觸窗數量影響，但 gm and S 的變化則無，隱性缺陷應是以氧化層 中的陷阱(oxide trap)型態存在• NMOS 經 FN stress 後，只有接觸窗最 多的元件的 Ig 從 2 pA 增加到 10 pA，其它 元件及參數都未顯示出製程損傷的跡象• 這也佐證 NMOS 比 PMOS 不易受到製程損 商• 我 們 也 嘗 試 用 熱 載 子 應 力 測 試 (hot carrier stress) 來評估製程損傷•PMOS 用 最大閘電流條件，NMOS 用最大基板電流 條件•PMOS 的 Vth 劣化率隨接觸窗數量 增加而增加，如圖四(左)，gm和 S 的劣化 則和接觸窗數量無關•這是因為 PMOS 的 劣化機制是電子被捕捉在氧化層中 [30-32]，既然隱性缺陷是氧化層中的陷阱，注 入的熱電子可以被隱性缺陷所捕捉，不需 要自行產生陷阱，分佈較無隱性缺陷的元 件廣，所以 Vth 的劣化率隨接觸窗數量增 加而增加，gm和 S 的劣化則和接觸窗數量 無關• NMOS 也顯示出 Vth 的劣化率隨接觸窗 數量增加而增加的現象，如圖四(右)，這再 一次支持隱性缺陷是氧化層中的陷阱的推 論•也同時表示 hot carrier stress 比 FN stress 容易看出隱性缺陷的存在與否•
不同接觸窗大小 (0.3 um, 0.25 um, 0.2 um) 或間距 (0.3 um, 0.6 um, 1.2 um)的元 件的直流特性都幾乎一樣 (接觸窗數目為 625)•為提高對製程損傷的鑑別能力，進 一步對這些 PMOS 施加 hot carrier stress•
圖五(左)是不同接觸窗大小的 PMOS 經 hot carrier stress 後的 Vth 劣化情形•似 乎接觸窗愈小劣化就愈輕，但幅度差別不 大•這可能是因為數量不變的情況下，接 觸窗愈小，天線比例愈低，所以損傷較輕• 這樣的結果顯示接觸窗蝕刻在 0.2um 時， 仍不會有電子遮避效應•圖五(右)是不同接 觸窗間距的 PMOS 經 hot carrier stress 後的 Vth 劣化情形•間距愈大則劣化愈嚴重，這 可能可以用局部電場分佈來解釋 [15]，但 詳細的原因在本計畫中尚未能確認•值得 慶幸的是在真實的電路中，多個接觸窗通 常會用最小間距，所以問題應不嚴重• 三、計畫成果自評 本計畫對介電層蝕刻製程的電漿製程 損傷進行了深入的探討•N-型電晶體及 P-型電晶體的基本電性參數及可靠度均已列 入評估項目，符合計畫原設定希望綜合比 較各種參數的變化以偵測損傷的發生的構 想• 本計畫共達成下列結論： 1. 確認低電場閘級電流在介電層蝕刻製 程下仍是最能反應奠漿損傷的直流參 數• 2. 經過後段製程，多數損傷轉為隱性缺 陷，缺陷 以氧化 層中之陷 阱型態 存 在•此類隱性缺陷必須以電應力測試 才能偵測到•
4 3. 在熱載子測試時，因為 PMOS 的熱載 子損傷機制與電漿製程的隱性缺陷同 為氧化層中的陷阱，故顯示與天線比 例相吻合的趨勢• 4. 損傷程度 與接觸 窗總面積 成正比 關 係，與接觸窗大小無關•可知在實驗 範圍內並無電子遮蔽效應發生• 5. 介 電 層 蝕 刻 的 安 全 天 線 比 例 低 於 100，遠低於導體蝕刻的安全天線比例 (約 10K)• 上述結果提供對介電層蝕刻步驟的電 漿製程損傷機制深入的了解，也顯示出介 電層蝕刻可能造成比導體蝕刻更嚴重的製 程傷害•對發展中的嵌入式製程提供預 警• 本計畫之部份研究成果已整理為學術 論文，並通過 Microelectronics Reliability 期刊之審查，正排版待刊中•原稿請見附 件• 五、參考文獻
1. S. J. Fonash, Proc. of International
Symposium on Plasma Process Induced Damage, P2ID-96, 1996, pp.195.
2. T. Watanabe and Y. Yoshida, Solid State
Tech. pp.263, April 1984.
3. K. H. Ryden, H. Norstrom, C. Nender,
and S. Berg, J. Electrochem. Soc.pp.3113, vol.134, No.12., 1987.
4. F. Shone, K. Wu, J. Shaw, E. Hokelet, S.
Mittal, and A. Haranahalli, Proc.
International Symposium of VLSI
Technology, 1989, pp.73.
5. W. M. Greene, J. B. Kruger, and G. Kooi,
J. Vac. Sci. Technol., vol-B9, pp.366, 1991.
6. C. T. Gabriel, J. Vac. Sci. Technol.,
vol-B9, pp.370, 1991.
7. H. Shin, C. C. King, T. Horiuchi, and C.
Hu, IEEE Electron Devices Lett., vol-12, No.8, pp.404, 1991.
8. S. Fang and J. P. McVittie, IEEE
Electron Devices Lett., vol-13, No.6, pp.347, 1992.
9. H. Shin and C. Hu, IEEE Trans. on Semi.
Manu., vol-6, No.1, pp.96, 1993.
10. M. R. Lin, P. Fang, H. Heiler, R. Lee, R. Rakkhit, and L. Shen, IEEE Electron Devices Lett., vol-15, No.1, pp.25, 1994. 11. K. R. Mistry, B. J. Fishbein, and B. S.
Doyle, Proc. International Reliability Physics Symposium, 1994, pp.42.
12. K. Noguchi and K. Okumura, Proc.
International Reliability Physics
Symposium, 1994, pp.232.
13. X. Li, R. Divakaruni, J. T. Hsu, V. Prabhakar, P. Aum, D. Chan, and C. R. Viswanathan, IEEE Electron Devices Lett., vol-15, No.4, pp.140, 1994.
14. K Hashimoto, Jpn. J. Appl. Phys. Vol.33, pp.6013, 1994.
15. B. Y. Tsui, S. H. Liu, G. L. Lin, J. H. Ho, C. H. Chang, and C. Y. Lu, IEEE Electron Devices Lett., vol.16, No.2, pp.64, 1995.
16. A. B. Joshi, L. Chung, B. W. Min, and D. L. Kwong, Proc. International Reliability Physics Symposium, 1996, pp.300.
17. K. P. Cheung and C. P. Chang, J. Appl. Phys., vol.75, No.9, pp.4415, 1994 18. S. Krishnan, S. Rangan, S. Hattangady,
G. Xing, K. Brennan, M. Rodder, and S. Ashok, International Electron Device Meeting Tech, Dig., 1997, pp.445.
19. S. Krishnan, W. W. Dostalik, K. Brennan, and S. Aur, International Electron Device Meeting Tech, Dig., 1996, pp.731.
20. S, Ma, and J. P. McVittie, Proc. of International Symposium on Plasma Process Induced Damage, 1996, pp.20. 21. P. K. Aum, R. Brandshaft, D. Brandshaft,
and T. B. Dao, IEEE Trans. Electron Devices, vol.45, No.3, pp.722, 1998. 22. W. Lukaszek, Proc. of International
Symposium on Plasma Process Induced Damage, 1996, pp.30.
23. H. C. Cheng, W. Lin, T. K. Kang, Y. C. Peng, and B. T. Dai, IEEE Electron Devices Lett., vol-19, No.6, pp.183, 1998.
24. S. Krishnan and Ajith Amerasekera, Proc. International Reliability Physics Symposium, 1998, pp.302.
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25. T. Makabe, J. Atsui, M. Shibata, and N.
Nakano, Proc. Of International
Symposium on Plasma Process Induced Damage, 1998, pp.156.
26. K. Noguchi, H. Ohtake, S. Samukawa, and T. Horiuchi, Proc. of International Symposium on Plasma Process Induced Damage, 1998, pp.176.
27. The national Technology Roadmap for Semiconductors. Semiconductor Industry Association, pp.101, 1997.
28. M. Okandan, S. J. Fonash, O. O. Awadelkarim, Y. D. Chan, and Fred Preuninger, IEEE Electron Devices Lett., vol-17, No.8, pp.388, 1996.
29. N. Matsunaga, H. Yoshinari, K. Tomioka, and H. Shibata, Proc. of the International Interconnect Technology Conference, IITC-99, San Francisco, May, 1999, pp.276.
30. C Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, IEEE Trans. Electron Devices, vol.32, No.3, pp.375, 1985.
31. W. S. Chang, B. Davari, M. R. Wordeman, Y. Taur, C. C. C. Hsu, and M. D. Rodriguez, IEEE Trans. Electron Devices, vol.39, No.4, pp.959, 1992. 32. C. C. H. Hsu, D. S. Wen, M. R.
Wordeman, Y. Taur, and T. H. Ning, IEEE Trans. Electron Devices, vol.41, No.5, pp.675, 1994. 圖一. 本計畫使用之測試結構示意圖• 圖二. 不同接觸窗數目的 NMOS 元件低電場 閘極電流累積分佈• 圖三. PMOS 經 FN stress 後的(左)閘極電流 及(右)臨界電壓漂移累積分佈•FN stress 條件是-1mA/cm2，10 second. 圖四. (左)NMOS 及(右)PMOS 經熱載子應 力測試後的臨界電壓漂移累積分佈•PMOS 應力測試條件是 Vds=-5V 及 Vgs=-0.8V• NMOS 應 力 測 試 條 件 是 Vds=4.5V 及 Vgs=1.6V. 圖五. (左)不同接觸窗大小及(右)不同接觸 窗間距的 PMOS 經熱載子應力測試後的臨 界電壓漂移累積分佈•應力測試條件是 Vds=-5V 及 Vgs=-0.8V• Active layer Poly-Si layer Contact layer Metal layer 0 20 40 60 80 100
1.E-13 1.E-12 1.E-11 1.E-10 1.E-09 1.E-08
Gate Current (A)
Cumulatiove Probability (%) CT No.=2875 CT No.=1275 CT No.=625 CT No.=125 0 20 40 60 80 100
1.E-13 1.E-11 1.E-09 1.E-07
Gate Current (A)
Cumulative Probability (%) CT No.=2875 CT No.=1275 CT No.=625 CT No.=125 0 20 40 60 80 100 0 3 6 9 12 15
Threshold Voltage Shift (mV)
Cumulative Probability (%) CT No.=2875 CT No.=1275 CT No.=625 CT No.=125 0 5 10 15 20 25
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Stress Time (sec)
Threshold Voltage Shift (mV)
CT No.=125 CT No.=625 CT No.=1275 CT No.=2875 0 0.1 0.2 0.3 0.4
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Stress Time (sec)
Threshold Voltage Shift (V)
CT No.=125 CT No.=625 CT No.=1275 CT No.=2875 0 3 6 9 12 15
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Stress Time (sec.)
Threshold Voltage Shift (mV)
CT=0.3 um CT=0.25 um CT=0.2 um 0 3 6 9 12
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 Stress Time (sec.)
Threshold Voltage Shift (mV)
SP=0.3 um SP=0.6 um SP=1.2 um
6
Plasma Char ging Damage dur ing Contact Hole Etch
In High-Density Plasma Etcher
Bing-Yue Tsuia,*, Shyue-Shyh Linb, Chia-Shone Tsaic, and Chin C. Hsiab
a. Department of Electronics Engineering, National Chiao-Tung University, 1001, Ta-Hsueh Road, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5712121 ext.54170 Fax : 886-3-5724361
E-mail : [email protected]
b. Deep Sub-micron Technology Division, ERSO/ITRI, Hsinchu, Taiwan, R.O.C. c. Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan, R.O.C.
Abstr act
Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at conductor etch. although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully.
Keywor ds : plasma process induced damage; dielectric etch; high-density plasma; latent
I. Intr oduction
Plasma process had been widely used in integrated circuit (IC) manufacturing. Since plasma system has charged and accelerated particles, several kind of damage may be induced during plasma process. The damages can be divided into four categories : (a) physical damage due to ion bombardment; (b) metal contamination from chamber and gas piping; (c) radiation damage due to glow discharge and ion bombardment; (d) charging damage due to unbalanced charge in plasma [1]. Among these damages, charging damage attracts much more attention in the past ten years because the damage may be magnified by the total exposed conducting area. It is the so-called antenna effect [2-26].
In the past, much work has been devoted to antenna effect during conducting layer etch, e.g. poly-Si layer and metal layer [2-17]. Basic mechanisms, damage modes, impacts on device and circuit, test structures, and measurement techniques have been discussed widely. From these fundamental understandings, low damage process, protection strategy, and new plasma reactor were proposed [18-26]. It is also well accepted that PPID (Plasma Process Induced Damage) can be withstood after optimizing process and circuit design.
Dielectric etch becomes more and more important in deep sub-micron era, because the aspect ratio of contact and via hole become larger and larger for DRAM process [27]. On the other hand, dual damascene process becomes main stream for metal patterning as Cu interconnect is used instead of Al interconnect [28]. Conventional metal etch is replaced by dielectric etch in damascene process. Therefore, dielectric etch is more and more important in IC manufacture, especially at backend of line (BEOL) processes. Unfortunately, less work has been done in the field of PPID of dielectric etch [29-33]. In ref.[29], the authors reported that only gate current was degraded by PPID. But only fresh device characteristics were measured and only area antenna effect was discussed. In ref.[30-32], the authors discussed the contact
etch damage on various thickness oxides. But the contact size is as large as 4 µm2. In ref.[33],
plasma system.
In this paper, we reported a comprehensive assessment of the PPID during dielectric etch in a high-density plasma (HDP) etcher. A set of test structures with various contact number, contact size, and contact space was designed. Various device parameters were measured before and after stress to separate latent damages from permanent defects. Hot carrier resistance was also evaluated. It is observed that under the same area antenna ratio, dielectric etch induces more severe damage to gate oxide than conductor etch does. Thus, PPID during dielectric etch must be considered carefully.
II. Exper iments
Both NMOS and PMOS devices were fabricated by a standard 0.25 µm
single-poly-triple-metal CMOS technology using shallow trench isolation structure. Gate oxide was
thermally grown to 5 nm thick. N+ and P+ doped-Si was used as gate electrode for NMOS and
PMOS devices, respectively. All devices used to monitor damage are identical and channel
length and channel width is 0.24 µm and 5 µm, respectively. In order to place more contacts to
poly-Si gate, and to exclude the effect of different antenna ratio during poly-Si etch, the antenna ratio of poly-Si pad area to gate oxide area was set to 2K for all devices. Devices with contact number of 125, 625, 1275, and 2875 corresponding to area antenna ratio (AAR) of 7,
37, 75, and 170, respectively, were designed. The typical contact size is 0.3 x 0.3µm2 and the
contact space is 0.3 µm. For some test structures the contact size and contact space are changed to study the effect of contact size and contact density, respectively. Contact etch was performed in a high density plasma system with inductively coupled plasma (ICP) source. The
plasma density at wafer surface is about 1011 ions/cm2. All devices were protected by p-n
diode and connected by the first layer metal to avoid damages from other plasma processes. Fig.1 shows the schematic diagram of the test structure used in this work.
transconductance (gm), sub-threshold swing (S) were all measured before and after Fowler-Nordheim (F-N) stress to separate the latent damages from permanent defects. The specification of Ig is 10 pA which is typical limitation of the noise and leakage current of the automatic measurement system. The F-N stress was performed in inversion polarity at the
current density of 1 mA/cm2 for 10 sec. Channel hot carrier stress was performed on
NMOSFET devices at maximum substrate current and PMOSFET devices at maximum gate current to evaluate the impact of damages on device integrity.
III. Results and Discussion
Since the poly-Si area must be large enough to contain more contact holes, the damage level at poly-Si etch step must be examined at first. Four device parameters, Ig,
Vth, gm, and S, were all measured on NMOS and PMOS devices with various AAR at
poly-Si layer. The contact number is one and the metal pad is connected to a protection diode. It is observed that even if the AAR of poly-Si is as high as 10K, no degradation of any parameters were observed. These results imply that the poly-Si AAR of 2K used for contact hole etch experiments will not introduce damage during poly-Si etch. Furthermore, the protection diode at metal-1 level is effective to avoid damage at metal etch step. All damages observed for higher contact hole AAR must be attributed to the contact hole etch step.
1. Damage Observation
Fig.2(a), (b), and (c) show the cumulative probability plots of Ig, Vth, and gm of NMOS
devices with various contact number before F-N stress, respectively. Although slight
difference of mean value of Ig is observed, all of them are within specification. The slight
difference of Ig may be arisen from the different surface leakage current since various structures are placed at various position of the test chip. Neither yield nor deviation degrades
with the increase of contact number for all parameters. Fig.3(a), (b), and (c) show the
cumulative probability plots of Ig, Vth, and gm of PMOS devices with various contact number
before F-N stress, respectively. PMOS devices with large contact number show wider spread
of Ig. Although the distribution of Vth and gm of PMOS devices do not show any contact
number dependence, the obvious correlation between Ig distribution and contact number reflects that PPID occurred and resulted in permanent damage to PMOS devices during contact etch. Sub-threshold swing was also measured, but no contact number dependence was observed for both NMOS and PMOS devices.
From the direct measurement results, two important phenomena were observed. At first, Ig is the most sensitive parameter to reveal damage among the measured DC parameters of devices. This can be easily understood. Oxide charges induced by PPID can be neutralized after BEOL processes. However, most of the trap sites can not be removed at the relatively
low process temperature (around 400 oC). Low field Ig is related to oxide trap sites while the
other device parameters are related to the trapped charges. Therefore, Ig can reflect PPID more
sensitive. The current-voltage characteristics of high Ig devices show stress induced leakage current (SILC). This confirms the existence of oxide trap sites. This result is similar to that reported in ref.[30-32, 34]. Second, PMOS device is damaged easier than NMOS device. This may be due to the polarity of charging during plasma process or due to the difference of poly-Si doping type and is still under investigation.
2. Latent Damages
To determine if any defects were passivated during BEOL processes, another device
populations were F-N stressed to 10 mC/cm2, and Ig, Vth, gm, and S were measured. Fig.4(a) is
the cumulative probability plot of Ig of PMOS devices with various contact numbers after
stress. It shows that devices with more contact holes have much wider Ig distribution after
stress) –Vth (before stress), is larger for devices with more contact holes as shown in Fig.4(b).
However, no apparent gm and S shift difference was observed on PMOS devices with different
antenna ratio after stress (not shown). These phenomena indicate that most of the plasma process induced defects were passivated during BEOL processes. Since these defects only results in Vth shift but not gm and S shift after stress, these passivated defects were located in gate oxide but not at oxide/silicon interface.
NMOS devices were also F-N stressed to reveal latent damages. However, except the mean value of NMOS devices with 2875 contact holes (AAR=170) increased from 2 pA to 10 pA, the other parameters did not show contact number dependence. The latent damages in NMOS devices are much less than that in PMOS devices. This confirms that NMOS device shows less PPID than PMOS device in this experiment.
It should be noted that the F-N stress used is not strong. The only purpose is to re-generate hidden damages. So, if device was not damaged by PPID, Ig will not increase after F-N stress. The results indicate that the device with largest AAR is damaged seriously during contact etch. Since the sensitivity of F-N test is lower than hot carrier test, hot carrier stress was performed in the next step. It was shown that hot carrier stress can resolve latent damages even if the contact number is only several hundreds.
3. Impact on Hot Carrier Resistance
Fig.5(a) shows the Vth shift of PMOS devices with various contact numbers after hot
carrier stress at Vds=-5V and Vgs=-0.8V. Higher contact number structure shows higher Vth
degradation rate. The other parameters such as gm and S do not show contact number
dependence. There are two possible explanations. First, no significant interface states were generated during hot carrier stress. It is reasonable because it is well accepted that the major degradation mechanism of PMOS devices under hot carrier stress is oxide trap but not interface state [35-37]. Second, the injected electrons were trapped at those trap sites
generated during plasma process in major. Since the plasma process induced defects are
uniformly distributed in channel region, the trapped electrons distributed broader. The Vth
shift of NMOS devices stressed at Vds=4.5V and Vgs=1.6V also show contact number dependence similar to that of PMOS devices as shown in Fig.5(b). These results confirm that defects located in gate oxide were passivated during BEOL processes and can be re-generated
during electrical stress. Although the amount Vth degradation of NMOS devices is higher than
that of PMOS devices, the difference between various contact number of NMOS devices is less apparent than that of PMOS devices. This is consistent with the conclusion in previous sections that NMOS device show less PPID than PMOS device. Furthermore, the major degradation mechanism of NMOS and PMOS devices under hot carrier stress is interface traps and oxide traps, respectively. The observed phenomenon also supports the argument that the latent damages are in the form of oxide traps.
4. Effect of Contact Hole Size and Contact Hole Density
At first, cumulative probability of Ig of NMOS and PMOS devices with various contact
hole size of 0.2, 0.25 and 0.3 µm (aspect ratio of 3.75, 3.0, and 2.5) and various contact hole
of 0.3, 0.6, and 1.2 µm) are measured. Since the contact number is 600 and 625 for devices
with various contact hole size and various contact hole space, respectively. No difference of Ig distribution was observed. This is not surprising according to the results shown in section 3.1. To improve the resolution, hot carrier stress was performed on PMOS devices. The stress condition is the same as that used in previous section.
Fig.6(a) shows the Vth shift of PMOS devices with various contact hole size after hot
carrier stress. It seems smaller contact hole results in smaller Vth shift. This may be due to the
reduction of antenna ratio by a factor of 2.25 as contact hole size is reduced from 0.3 µm to
0.2 µm. No electron shading enhanced effect was observed.
carrier stress. It is surprising that the larger the contact hole space, the larger the Vth shift. This may be due to the local field disturbing effect [38]. To deeply understand the mechanism required additional works on the local field distribution which is beyond the scope of this paper. Fortunately, the contact hole space will be pushed to technology limitation to improve the circuit density. This wide space layout does not occur at real circuit.
IV. Conclusion
In this work, the PPID during contact hole etch in a HDP system was investigated comprehensively. Among the devices DC parameters, Ig is the most sensitive parameter to reveal the permanent defects. Some permanent defects were hidden during the BEOL process. These latent damages in the form of oxide trap exist in gate oxide. They can be re-generated after F-N stress or hot carrier stress. NMOS devices show less PPID than NMOS devices in this work.
The PPID shows good correlation with the number of contact, i.e. the total area of contact holes. The hot carrier degradation decreases with the decrease of contact hole size due to the reduction of antenna ratio. The PPID is enhanced by the wide contact hole space. Fortunately, it will not be issues in real circuit. It is also observed that the safe antenna ratio of contact hole etch is much less than that of conductor. Therefore, PPID during contact hole or via hole etch must be considered carefully.
Acknowledgement
The authors wish to thank Dr. Y. S. Jean for part of hot carrier stress. This work is partially supported by the National Science Council, ROC, under the contract No. NSC89-2215-E-009-074.
Refer ences
1. S. J. Fonash. Photons, charging current, hydrogen, and particle bombardment – the four
horsemen of plasma etching. In : Proc. Of International Symposium on Plasma Process Induced Damage, P2ID-96, Santa Clara, May 1996, pp.195.
2. T. Watanabe, Y. Yoshida. Dielectric breakdown of gate insulator due to reactive ion
etching. Solid State Tech. pp.263, April 1984.
3. K. H. Ryden, H. Norstrom, C. Nender, S. Berg. Oxide breakdown due to charge
accumulation during plasma etching. J. Electrochem. Soc.pp.3113, vol.134, No.12., 1987.
4. F. Shone, K. Wu, J. Shaw, E. Hokelet, S. Mittal, A. Haranahalli, Gate oxide charging and
its elimination for metal antenna capacitor and transistor in VLSI CMOS double layer metal technology. In : Proc. International Symposium of VLSI Technology, VLSI-89, Kyoto, 1989, pp.73.
5. W. M. Greene, J. B. Kruger, G. Kooi. Magnetron etching of polysilicon : electrical
damage. J. Vac. Sci. Technol., vol-B9, pp.366, 1991.
6. C. T. Gabriel. Gate oxide damage from polysilicon etching. J. Vac. Sci. Technol., vol-B9,
pp.370, 1991.
7. H. Shin, C. C. King, T. Horiuchi, C. Hu. Thin oxide charging current during plasma
etching of aluminum. IEEE Electron Devices Lett., vol-12, No.8, pp.404, 1991.
8. S. Fang, J. P. McVittie. A model and experiments for thin oxide damage from wafer
charging in magnetron plasma. IEEE Electron Devices Lett., vol-13, No.6, pp.347, 1992.
9. H. Shin, C. Hu. Monitoring plasma-process induced damage in thin oxide. IEEE Trans.
on Semi. Manu., vol-6, No.1, pp.96, 1993.
10. M. R. Lin, P. Fang, H. Heiler, R. Lee, R. Rakkhit, L. Shen. Characterization and optimization of metal etch processes to minimize charging damage to submicron transistor gate oxide. IEEE Electron Devices Lett., vol-15, No.1, pp.25, 1994.
11. K. R. Mistry, B. J. Fishbein, B. S. Doyle. Effect of plasma-induced charging damage on n-channel and p-channel MOSFET hot carrier reliability. In : 32th Proc. International Reliability Physics Symposium, IRPS 94, San Hose, April 1994, pp.42.
12. K. Noguchi, K. Okumura. The effect of plasma-induced oxide and interface degradation on hot carrier reliability. In : 32th Proc. International Reliability Physics Symposium, IRPS 94, San Hose, April 1994, pp.232.
13. X. Li, R. Divakaruni, J. T. Hsu, V. Prabhakar, P. Aum, D. Chan, C. R. Viswanathan. Effect of plasma poly etch on effect channel length and hot carrier reliability in submicron transistor. IEEE Electron Devices Lett., vol-15, No.4, pp.140, 1994.
14. K Hashimoto. Charging damage caused by electron shading effect. Jpn. J. Appl. Phys. Vol.33, pp.6013, 1994.
15. B. Y. Tsui, S. H. Liu, G. L. Lin, J. H. Ho, C. H. Chang, C. Y. Lu. Recovery phenomenon and local field sensitivity of wafer charge-up effect of magnetically enhanced reactive ion etch system. IEEE Electron Devices Lett., vol.16, No.2, pp.64, 1995.
16. A. B. Joshi, L. Chung, B. W. Min, D. L. Kwong. Gate oxide thickness dependence of RIE-induced damages on N-channel MOSFET reliability. In : 34th Proc. International Reliability Physics Symposium, IRPS 96, Las Vegas, April 1996, pp.300.
17. K. P. Cheung, C. P. Chang. Plasma-charging damage : a physical model. J. Appl. Phys., vol.75, No.9, pp.4415, 1994
18. S. Krishnan, S. Rangan, S. Hattangady, G. Xing, K. Brennan, M. Rodder, S. Ashok. Assessment of charge-induced damage to ultra-thin gate MOSFETs. In : International Electron Device Meeting Tech, Dig. IEDM-97, Washington D.C., December 1997, pp.445.
19. S. Krishnan, W. W. Dostalik, K. Brennan, S. Aur. Inductively coupled plasma (ICP) metal etch damage to 30-60 Å gate oxide. In : International Electron Device Meeting Tech, Dig. IEDM-96, San Francisco, December 1996, pp.731.
20. S, Ma, J. P. McVittie. Prediction of plasma charging induced gate oxide tunneling current and antenna dependence by plasma charging probe. In : Proc. Of International Symposium on Plasma Process Induced Damage, P2ID-96, Santa Clara, May 1996, pp.20.
21. P. K. Aum, R. Brandshaft, D. Brandshaft, T. B. Dao. Controlling plasma charge damage in advanced semiconductor manufacturing – challenge of small feature size device, large chip size, and large wafer size. IEEE Trans. Electron Devices, vol.45, No.3, pp.722, 1998. 22. W. Lukaszek. Quantifying wafer charging during via etch. In : Proc. of International Symposium on Plasma Process Induced Damage, P2ID-96, Santa Clara, May 1996, pp.30.
23. H. C. Cheng, W. Lin, T. K. Kang, Y. C. Peng, B. T. Dai. A novel two-step etching to suppress the charging damages during metal etching employing helicon wave plasma. IEEE Electron Devices Lett., vol-19, No.6, pp.183, 1998.
24. S. Krishnan, Ajith Amerasekera. Antenna protection strategy for ultra-thin gate MOSFETs. In : 36th Proc. International Reliability Physics Symposium, IRPS 98, Reno, March/April 1998, pp.302.
25. T. Makabe, J. Atsui, M. Shibata, N. Nakano. Toward charging free plasma processes : phase space modeling between pulsed plasma and microtrench. In : Proc. Of International Symposium on Plasma Process Induced Damage, P2ID-98, Honolulu, June, 1998, pp.156. 26. K. Noguchi, H. Ohtake, S. Samukawa, T. Horiuchi. Suppression of topography-dependent charging damage to MOS devices using pulse-time-modulated plasma. In : Proc. Of International Symposium on Plasma Process Induced Damage, P2ID-98, Honolulu, June, 1998, pp.176.
27. The national Technology Roadmap for Semiconductors. Semiconductor Industry Association, pp.101, 1997.
28. The national Technology Roadmap for Semiconductors. Semiconductor Industry Association, pp.101, 1997.
29. M. Okandan, S. J. Fonash, O. O. Awadelkarim, Y. D. Chan, and Fred Preuninger. Soft-breakdown damage in MOSFET’s due to high-density plasma etching exposure. IEEE Electron Devices Lett., vol-17, No.8, pp.388, 1996.
30. D. Park and C. Hu. Plasma charging damage on ultra-thin gate oxide. In : Proc. of International Symposium on Plasma Process Induced Damage, P2ID-97, San Francisco, May, 1997, pp.15.
31. D. Park, M. Kennard, Y. Melaku, N. Benjamin, T. J. King, and C. Hu. Stress-induced leakage current due to charging damage : gate oxide thickness and gate poly-Si etching condition dependence. In : Proc. of International Symposium on Plasma Process Induced Damage, P2ID-98, Honolulu, June, 1998, pp.56.
32. D. Park and C. Hu. The prospect of process-induced charging damage in future thin gate oxides. Microelectronics Reliability, vol.39, pp.567, 1999.
33. N. Matsunaga, H. Yoshinari, K. Tomioka, H. Shibata. Damascene process induced charging damage phenomenon. In : Proc. of the International Interconnect Technology Conference, IITC-99, San Francisco, May, 1999, pp.276.
34. C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chien, S. K. Hsien, and T. Y. Huang. Plasma-induced charging damage in ultrathin (3nm) nitrided oxide. In : Proc. of International Symposium on Plasma Process Induced Damage, P2ID-99, Monterey, May, 1999, pp.141.
35. C Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, K. W. Terrill. Hot electron-induced MOSFET degradation – model, monitor, and improvement. IEEE Trans. Electron Devices, vol.32, No.3, pp.375, 1985.
36. W. S. Chang, B. Davari, M. R. Wordeman, Y. Taur, C. C. C. Hsu, and M. D. Rodriguez.
A high-performance 0.25-µm CMOS technology : I-design and characterization. IEEE
Trans. Electron Devices, vol.39, No.4, pp.959, 1992.
37. C. C. H. Hsu, D. S. Wen, M. R. Wordeman, Y. Taur, T. H. Ning. A comprehensive study of hot-carrier instability in P- and N-type poly-Si gated MOSFET’s. IEEE Trans. Electron Devices, vol.41, No.5, pp.675, 1994.
38. B. Y. Tsui, S. H. Her, G. L. Lin, J. H. Ho, C. H. Chang, and C. Y. Lu. Recovery phenomenon and local field sensitivity on wafer charge-up effect of magnetically enhanced reactive ion etch system. IEEE Electron Device Lett., vol.16, No.2, pp.64, 1994.
Figur e Captions
Fig.1. Schematic diagram of the test structure used to study the plasma process induced damage during contact hole etch. The area antenna ratio at poly-Si layer is 1000. Structures with various contact number, contact size, and contact density are all designed and measured.
Fig.2. Cumulative probability plots of (a) gate current Ig, (b) threshold voltage Vth, and (c)
transconductance gm of NMOS devices with various contact number before F-N stress.
Fig.3. Cumulative probability plots of (a) gate current Ig, (b) threshold voltage Vth, and (c)
transconductance gm of PMOS devices with various contact number before F-N stress.
Fig.4. Cumulative probability plots of (a) gate current and (b) threshold voltage shift of PMOS devices with various contact number after F-N stress at inversion polarity at 1
mA/cm2 for 10 second.
Fig.5. Threshold voltage shift of (a) PMOS devices and (b) NMOS devices with various contact numbers after hot carrier stress. The PMOS devices is stressed at Vds=-5 V and
Vgs=-0.8 V. The NMOS devices is stressed at Vds=4.5 V and Vgs=1.6 V.
Fig.6. Threshold voltage shift of PMOS devices with various contact hole size of 0.2, 0.25
and 0.3 µm. The contact space is 0.3 µm and the number is 600.
Fig.7. Threshold voltage shift of PMOS devices with various contact hole space of 0.3, 0.6,
Fig.1
Active layer
Poly-Si layer
Contact layer
Fig.2(a)
0
20
40
60
80
100
1.E-13 1.E-12 1.E-11 1.E-10 1.E-09 1.E-08
Gate Current (A)
Cumulatiove Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.2(b)
0
20
40
60
80
100
0.50
0.55
0.60
0.65
Threshold Voltage (V)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.2(c)
0
20
40
60
80
100
75
80
85
90
Transconductance (uA/V)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.3(a)
0
20
40
60
80
100
1.E-13
1.E-12
1.E-11 1.E-10
1.E-09
1.E-08
Gate Current (A)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.3(b)
0
20
40
60
80
100
0.50
0.52
0.54
0.56
0.58
0.60
Threshold Voltage (V)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.3(c)
0
20
40
60
80
100
17
18
19
20
21
22
Transconductance (uA/V)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.4(a)
0
20
40
60
80
100
1.E-13
1.E-11
1.E-09
1.E-07
Gate Current (A)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
Fig.4(b)
0
20
40
60
80
100
0
3
6
9
12
15
Threshold Voltage Shift (mV)
Cumulative Probability (%)
CT No.=2875
CT No.=1275
CT No.=625
CT No.=125
0
5
10
15
20
25
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
Stress Time (sec)
Threshold Voltage Shift (mV)
CT No.=125
CT No.=625
CT No.=1275
CT No.=2875
Fig.5(a)0
0.1
0.2
0.3
0.4
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
Stress Time (sec)
Threshold Voltage Shift (V)
CT No.=125
CT No.=625
CT No.=1275
CT No.=2875
Fig.5(b)Fig.6
0
3
6
9
12
15
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
Stress Time (sec.)
Threshold Voltage Shift (mV)
CT=0.3 um
CT=0.25 um
CT=0.2 um
Fig.7
