應用於無線感測網路之超低耗能無線微感測模組的設計與製作-子計畫二：超低耗能系統之智慧型電源管理

子計畫二：超低耗能系統之智慧型電源管理

中 華 民 國 95 年 10 月 16 日

II. R e s e a r c h S t e p s ...3 i . In t e g r a t e d S y s t e m A n a l y s i s ...3 i i . S t r u c t u r e D i s c u s s i o n ...4 i i i . Im p l e m e n t t h e D C -D C P o w e r C o n v e r t e r ...5
P o w e r M a n a g e m e n t R e v i e w ...5
S y s t e m S u m m a r y ...6
A c t u a l C i r c u i t D e s i g n ...8 III. P r o j e c t S c h e d u l e & A c h i e v e m e n t A n t i c i p a t i o n ... 11 i . P r e s e n t A c h i e v e m e n t ... 11
Im p l e m e n t t h e l o w p o w e r D C / D C c o n v e r t e r IC : ... 11
T h e w h o l e c h i p s i m u l a t i o n : ... 11 i i . R e s e a r c h P l a n ...12

The design of the DC/DC converter...12

S m a rt p ow er su p p l y ...12

I . T h e P u r p o s e a n d t h e I m p o r t a n c e

Recently, new emerging applications such as RFID and wireless sensor network , which consume v ery low power and utiliz e the energy harv ested f rom the env ironment, are gaining more attention. In these applications, the energy are collected f rom solar, v ib ration, heat or radioactiv e decay of matters and at the same time the amount of energy av ailab le is limited and the source is unstab le.

In some env ironment, such as the M E M S power generator, the harv ested v oltage source may b e much lower. A t the same time in order to reduce the cost of the dev ice, ex pensiv e v oltage regulator should b e av oided. U nstab le source poses new challenges in the design of the power management circuit and computation paradigm f or the applications.

M oreov er, the b attery charger is also considered f or the no dynamics env ironment. T he charger charge the b attery in the standb y period.

In this work , we propose a power management system f or energy-limited source applications. W e propose a supply-side charge-b ased computation paradigm where computation is carried out only when the energy harv ested f rom the env ironment is enough to ex ecute a specif ied operation of the computation.

I I . R e s e a r c h S t e p s

Due to the output power of the M E M S generator could b e unstab le caused b y the v ib ration of the surrounding and the v ariation of the load, we need the adaptiv e power management mechanism to enhance the transf er ef f iciency of the conv erter with a stab le power output. T he conv entional power transf er module is designed a constant v alue, and this output power must mak e the load to work normally in any situations.

In other words, this output power v alue is the max imum v alue of the load

consumption. B ut considering the actual application, the processor, DRA M , monitor, etc. are not in heav y load situation any time. E specially the portab le communication dev ice is of ten at the standb y mode, so the ef f iciency of the whole load range will get much attention at the actual application. T he output power of the adaptiv e power management will b e reduced when the needed processing speed is lower. T he power j ust b e lif ted up when the system needed.

Figure 2: The p ower consump tion of the conv entional and the adap tiv e p ower management

In theory, the dynamic power is proportional to the sq uare of the operation v oltage, so we should utiliz e the av erage v oltage scaling to reduce the unnecessary power

consumption. H owev er in order to adj ust the operation v oltage to conf orm to ev ery demand f or the load, we hav e to ex port the wide range and high ef f iciency power supply.

i . In t e g r a t e d S y s t e m A n a l y s i s

T he output v oltage of the M E M S generator is a time-v ariab le v oltage. T he property of this v oltage may b e an aperiodic or unreliab le v oltage. S o we must regulate this v oltage to ensure operating the f unctions of the whole circuit. W e ex pect to utiliz e a low power consumption DC / DC switching conv erter.

Figure 4: The sk etch of the outp ut v oltage of M E M S

T he peak v oltage generated b y M E M S is ab out 1 6V . T hus high v oltage lev el will damage the circuit dev ice seriously if the circuit isn’ t f ab ricated b y high v oltage C M O S technology.

Figure 5: The whole p ower structure include the M E M S generator

E x cept the main step-down conv erter circuit, we should tak e care of the ultra high v oltage lev el unex pectedly. If the v oltage is too high, it can draw out the current to press the v oltage. A nd it also charge the large capacitor to reduce the output ripple if the input power is enough.

i i . S t r u c t u r e D i s c u s s i o n

T ypically, we of ten use the linear regulator, such as low dropout regulator (L DO ) . H owev er, the drawb ack of this structure is the low transf er ef f iciency at the large drop v oltage b etween the output and supply v oltage. Presently currently applied switching regulator, the transf er ef f iciency will b e up to 90 % , and the large output load range.

Tab le 1: The linear and switching regulator comp are

In this proj ect, L DO is not the suitab le choice b ecause the low ef f iciency. A lthough the switching conv erter is dif f icult to design, its sev eral adv antages still driv e us to implement it.

i i i . Im p l e m e n t t h e D C -D C P o w e r C o n v e r t e r
P o w e r M a n a g e m e n t R e v i e w

A s we k now, dynamic (or adaptiv e) v oltage scaling (DV S ) techniq ue is widely used as one of the most ef f ectiv e means f or achiev ing energy-ef f iciency design. G enerally speak ing, power consumption has b ecome the most

important issue in portab le b attery-powered applications and high-perf ormance desk top and serv er applications. T he attractiv e salient f eatures of DV S systems trigger the design of f ast and adaptiv e-output-v oltage DC -DC conv erters with high ef f iciency ov er a wide load range.

Figure 6: Three control modes conv erter that efficiency as functions of outp ut current.

A popular techniq ue to improv e the ef f iciency ov er a wide load range is the hyb rid mode, which is composed of pulse-width modulation (PW M ) and pulse-f req uency modulation (PFM ) . H yb rid mode achiev es a high ef f iciency f or the load current region A and B in Figure 6. H owev er, there ex ists an ef f iciency dropping region C in Figure 6. It means that the ef f iciency curv e is not smooth

at the transition b etween PW M mode and PFM mode. It is a matter of ef f iciency and current load range f or hyb rid-mode modulation techniq ue. T he hyb rid-mode modulation can maintain a high ef f iciency b y closing the two peak ef f iciency v alues to reduce the ef f iciency drop at the sacrif ice of load range. T heref ore, a dithering sk ip modulator is proposed to raise the ef f iciency

b etween PW M and PFM curv es in Figure 6. In other words, the ef f iciency drop b etween PW M and PFM modes can b e raised b y the nov el DS M mode.

B esides, a nov el load sensor is also proposed f or DS M in order to dynamically switch among these three modes, which are PW M , PFM , and DS M modes. Furthermore, compared with PS M mode and b urst mode, DS M mode uses the dithering techniq ue to reduce the output ripple. Due to the insertion of DS M mode, a wide load range and high ef f iciency can b e achiev ed without sacrif icing the load range of conv entional hyb rid mode. B esides, the improv ed result is ex pected as the smooth ef f iciency curv e f rom PW M mode curv e to DS M mode curv e and f urther ex tending to PFM mode without increasing the output v oltage ripple.

S y s t e m S u m m a r y

Figure 7: Block diagram of the tri-mode b uck conv erter

controller, which is composed of PW M , PFM , and DS M modes. B esides, the load sensor estimates the load condition and sends the digital decision code (D1 , D2,..., DN ) to decoder in order to dynamically select an optimum

modulator among these three modulators. C ompared with the prior design, the b uck DC -DC conv erter does not need an ex ternal pin to decide the optimum modulator b ecause of the nov el load sensor.

Figure 8: Timing diagrams for dithering sk ip modulator

T he concept of DS M mode is illustrated in Figure 8. T he decreasing load current increases the siz e of DS period as shown in Figure 8 (a) to (c) . T he latter section will prov e the siz e of DS period is inv ersely proportional to the load current. T hus, a DS period gradually contains more DS modules when the load current continuously decreases. In order to reduce the output v oltage ripple, the dithering sk ip techniq ue is implemented b y the DS module. T he f unction of a DS module is to mak e the DC -DC conv erter sk ip one switching pulse among three continuous switching cycles. C ertainly, much power can b e retrenched b y reducing the switching consumption of power M O S FE T b ecause of the gradual decrease of load current.

A c t u a l C i r c u i t D e s i g n 1 . C urrent S ensing C ircuit

Figure 9: C urrent sensing techniq ue with S E N S E FE T top ology

In. Figure 9, a f ormal current sensing techniq ue called S E N S E FE T topology is proposed b y prior literature [ 8] . During the sensing period, the P-type power M O S FE T is turned on b y setting signal S W _ P low and the sensing current Isense is eq ual to a thousandth of inductor current IL . B y the sensing resistor Rsense, the sensing current can b e transf erred to sensing v oltage V sense. T hus, the peak v alue of sensing v oltage can stand f or the load condition of the output. H owev er, ev en though V sense is direct proportional to the load current, it is dif f icult f or simple comparators to decide the switching points of three controllers b ecause the v ariation of V sense is too small.

2. T ri-mode C ontroller

Figure 10 : Tri-mode controller is comp osed of P W M , P FM , and D S M modes

A ccording to the operation codes in T ab le 2, the tri-mode controller composed of three modulators is shown in Figure 1 0 . Depending on the load condition, the tri-mode controller selects one optimum modulator f rom these three modulators to generate the switching signals S W _ P and S W _ N f or P-type power M O S FE T M p and N -type power M O S FE T M n,

f eedb ack control is adopted.

T he comparator named as ‘comp1 ’ is used f or PFM mode to

determine whether the output v oltage is eq ual to the desired output v oltage lev el or not. If V PFM signal is eq ual to “0 ” , the comparators ‘comp1 ’ and ‘comp3 ’ are turned of f and their output v alues are set to “1 ” . T he other comparator ‘comp2’ is utiliz ed to turn of f N -type power M O S FE T M n to prev ent negativ e inductor current.

T he digital decision code (V PW M , V PFM ) decides one optimum modulator f rom the three modulators f or the tri-mode controller. If the code (V PW M , V PFM ) is eq ual to (1 , 0 ) , the conv erter is switched to PW M mode. S imilarly, the conv erter is switched to DS M mode when the code (V PW M , V PFM ) is eq ual to (0 , 0 ) . In the meanwhile the dithering sk ip circuit is ready to sk ip some pulses of PW M mode to sav e much power consumption. O wing to the dithering techniq ue, the output v oltage ripple can b e smaller than that of PS M mode or b urst mode [ 4 -6] . C ertainly, the power consumption can b e reduced b y the sk ipping pulses and the sk ipping pulses do not dramatically af f ect the output v oltage b ecause of dithering techniq ue.

3 . C urrent-M ode Delay-L ine A / D C onv erter

Figure 11: S chematic of the current-mode delay-line A / D conv erter

T he proposed current-mode delay-line A / D conv erter is composed of a sample-and-hold circuit, a V -I conv erter, a current-mode delay-line chain, and a register. During a sensing period, there are two regions to complete the generation of dithering sk ip pulses. A t the b eginning of the sensing period, a sampling clock clk sam starts the f irst region, which is the sample region. In order to av oid unnecessary mode switching and sav e the power

consumption, the sensing clock clk sam is periodically generated f or sev eral times of switching cycles.

4 . Decoder and Dithering S k ip C ode G enerator

Figure 12: D iagram of the mode decoder Figure 13: D ither sk ip p ulses generator

A simple ex ample shows the implementation of the mode decoder in Figure 1 2. T hree digital mode b its are selected f rom the digital word (D1 , D2,..., DN ) . T he selection of digital mode b its def ines the siz es of three mode region. T hus, the selection rule is determined b y the trade-of f b etween ef f iciency and output v oltage

I I I . P r o j e c t S c h e d u l e & A c h i e v e m e n t A n t i c i p a t i o n

T his integrated proj ect is q uite complex . T he k inds of the low power DC / DC conv erter are numerous. H owev er the research in the application to M E M S generator must consider the b alance b etween the little generated power and the ef f iciency of the system.

i . P r e s e n t A c h i e v e m e n t

T he high ef f iciency, wide input v oltage range, stab le output v oltage, and low power DC / DC conv erter is proposed. T his circuit transf ers the power f rom the M E M S generator to supply the other S O C f unction b lock s.

Im p l e m e n t t h e l o w p o w e r D C / D C c o n v e r t e r IC :

W e will implement the low power DC / DC conv erter IC this year, which can receiv e the power f rom the M E M S generator and transf er the stab le v oltage to supply the whole system. Due to the v oltage f rom the M E M S generator is ab out 1 6V , we designed the protect circuit and used high v oltage C M O S process. W e hope the ef f iciency of the power transf er achiev e 95 % .
T h e w h o l e c h i p s i m u l a t i o n :

Figure 1 4 : W av ef orms of delay-line chain with temperature

v ariations(-4 0 ° C ~ 1 4 0 ° C ) . (a) L oad current = 1 20 mA . (b ) L oad current = 4 0 mA .

Figure 1 5 : W av ef orms of proposed DC -DC b uck conv erter. L oadcurrent = 1 20 mA

Figure 1 6: M easured PW M , DS M and PFM mode conv erter ef f iciency asV DD = 3 .6v , V out = 1 .8v

i i . R e s e a r c h P l a n

The design of the DC/DC converter

W e will research the DC / DC conv erter structure under the M E M S generator supply to f ind the max imum power transf er ef f iciency. T he dif f erent implement of the DC / DC conv erter will f ollow the sev eral prob lems at the dif f erent system. B ut we should reduce the numb er of the ex ternal component.

S m a rt p ow er su p p l y

W e will mak e ef f orts in optimum power management, according to the f req uency of the digital signal process b lock , system power using ef f iciency, load v ariation, and the amount of the stored energy.

I V . R e f e r e n c e

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[ 8] H assan Pooya Forghani-z adeh, G ab riel A . Rincon-M ora, “C urrent-sensing techniq ues f or DC -DC conv erters,” M W S C A S -2 0 0 2 v ol.2, pp. II-5 77 - II-5 80 , A ug. 20 0 2.

[ 9] C heung Fai L ee and Philip K . T . M ok , “A M onolithic C urrent-M ode C M O S DC -DC C onv erter with O n-C hip C urrent-S ensing T echniq ue,” IEEE J. S o l i d -S t a t e C i r c u i t s , v ol. 3 9, no. 1 , pp. 3 -1 4 , J an. 20 0 4 .

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