An Isolated Full-Bridge DC–DC Converter With
1-MHz Bidirectional Communication Channel
Ru-Shiuan Yang, Student Member, IEEE, Lon-Kou Chang, and Hung-Chi Chen, Member, IEEE
Abstract—This paper presents a novel isolated full-bridge dc/dc
converter with bidirectional communication capability. The trans-former in the proposed converter is utilized as an isolation inter-face for transferring both energy and data. Power delivery and forward data transfer are conducted simultaneously by modifying the full-bridge switching phase. Backward data transfer is realized by manipulating the amplitude of the resonant signal through modulating the impedance of the resonant tank at the secondary side of the transformer. Finally, the operation principle of the proposed converter was verified on a 900-mW prototype operating at 1 MHz from a 12-V dc input.
Index Terms—Bidirectional communication, data transmission,
full-bridge converter, isolation,LLC, resonance, transformer. I. INTRODUCTION
I
N NUMEROUS applications, such as telephony [1]–[3], electricity usage meter [4], medical instrument [5], and industrial control system [6], isolated interfaces are required for safety and grounding. In conventional approaches, power conversion and communication function are realized with in-dependent interface circuits. For isolated dc/dc power conver-sion, a transformer is applied as a power transfer device. For data communication, extra pulse transformers, optocouplers, or high-voltage capacitors are applied as data transfer interface. Some methods combine power supply and data communication in common isolation barrier, like in [7] and [8]. This paper presents a novel isolated full-bridge dc/dc converter with bidi-rectional communication capability. It provides a high insula-tion quality and a high integrainsula-tion design with reduced cost and device counts by using a common isolated transformer that facilitates power and data transfer.Generally, L–C combination resonant technology is
em-ployed in power converters [9]–[21] to achieve soft switching for increasing the efficiency. In the proposed design, the reso-nant operation is developed to achieve “data transmission.”
The operations of the proposed converter for providing bidi-rectional communication are as follows: 1) Power delivery and forward data transfer can be made simultaneous by altering Manuscript received April 7, 2010; revised August 11, 2010; accepted October 6, 2010. Date of publication November 29, 2010; date of current ver-sion August 12, 2011. This work was supported by the National Science Coun-cil of Taiwan under Contract NSC 96-2221-E-009-239-MY3: “An Isolated Full-Bridge DC/DC Converter with Bidirectional Communication Capability.” R.-S. Yang and H.-C. Chen are with the Department of Electri-cal Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]; hcchen@ cn.nctu.edu.tw).
L.-K. Chang is with Macroblock, Inc., Hsinchu 30072, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2010.2095397
Fig. 1. Block diagram of the proposed power converter.
the full-bridge switching phase. A positive or negative voltage phase across the primary winding of the transformer represents a 0 or 1 signal of forward datum, respectively. 2) The backward data transfer is attained by manipulating the amplitude of a resonant signal through modulating the impedance of the res-onant tank at the secondary side of the transformer. Therefore, backward datum can be retrieved by detecting the different amplitudes of the resonant signal across the primary winding of the transformer. A low power-loss backward data transfer is achieved through the resonant operation of the transformer after the transformer is fully demagnetized. No additional supplied power is needed to transfer backward data. Via these two data transfer approaches, isolated bidirectional data communication is accomplished.
II. CIRCUIT ANDOPERATIONPRINCIPLE
Fig. 1 shows the block diagram of the proposed isolated dc/dc converter, including the converter and data communication stages. The data communication stage includes a primary con-trol circuit and secondary concon-trol circuit to achieve bidirectional communication. The primary control circuit is employed to transfer forward data from the Host side to the I/O side through the transformer and simultaneously transfer power to the load in the I/O side. The secondary control circuit is utilized to transfer backward data from the I/O side to the Host side through the transformer. Additionally, the primary and secondary control circuits are also used for receiving the data transmitted from the opposite sides.
Fig. 2 shows the power conversion stage of the proposed power converter which includes four circuit blocks: 1) an isolated transformer that transfers power and data; 2) a full-bridge switching stage, including transistors Q1,Q2,Q3, and
Q4, that generates a switching signal according to the forward
datumT X1; 3) rectifier diodesD5, D6, D7, D8 and an output
capacitor CO that provides a supply voltage to the load and the secondary control circuit; and 4) an impedance modulator, 0278-0046/$26.00 © 2010 IEEE
Fig. 2. Proposed dc/dc converter including the impedance modulator.
Fig. 3. Key waveforms of the proposed converter.
including diodesD9andD10 and transistorQ5, that controls
the impedance of the transformer according to the backward datumT X2.
Fig. 3 shows four operational states (States 1–4) in a switch-ing cycleTSduring bidirectional communication. Table I shows
the control table of the on-transistors related to the transmitted forward datumT X1and backward datumT X2in each
opera-tion state.
A. State 1[t0−t1]: Duration of Power and Forward
Data Transfer
In this state, power is transferred from the input dc bus(VIN)
to the load through the full-bridge stage and rectifier diodes. According to the transistor switching control shown in Table I, the voltage polarity of the full-bridge converter’s outputVABis
manipulated by the logic state of forward datumT X1. Through
the voltage polarity control, power and forward datumT X1
can be transferred simultaneously to the secondary side through the isolated transformer. After rectification, the coupled voltage
TABLE I
CONTROLTABLE OF THE ON-TRANSISTORSRELATED TO THETRANSMITTEDDATUM
VCDacross the transformer secondary winding generates the dc
output voltage(VO). Meanwhile, the transferred forward datum is retrieved simply by a level-detect circuit in the transformer secondary side.
When transmitted forward datumT X1 is 0, transistors Q1
and Q3 are turned on, resulting in VAB= VIN; otherwise,
VAB= −VIN for the case of T X1= 1. When VAB= VIN,
rectifier diodes D5 and D7 are turned on. The current of
the secondary winding iLs(t) = n∗(iLk(t) − iLm(t)), where
n is the turn ratio of the transformer, i.e., n = NP/NS. The
increasing rate of the magnetizing current of the transformer is given by
diLm(t)
dt =
n(VO+ 2VD)
Lm (1)
whereVOis the average output voltage andVD is the forward
conduction voltage of the rectifier diode.
Since the leakage inductance Lk is much smaller than the
magnetizing inductance Lm of the transformer, the voltage
across the leakage inductance is low, such that VLk VLm.
The voltage on the magnetizing inductance is approximately equal to input voltage, i.e., VIN≈ n(VO+ 2VD). Assuming
that the conditionΔVLk VLkis satisfied, the voltage across
the leakage inductorVLk can be seen as a constant. Therefore,
the switching current of the leakage inductanceiLk in State 1
increases linearly. It can be expressed as
iLk(t) t1 t0 = VIN− n(VO+ 2VD) Lk × t. (2)
B. State 2[t1−t3]: Duration of Transformer Demagnetization
The case ofT X1= 0 is assumed for illustrating the circuit
operation. If the current through an inductor is forced to change rapidly, a very high voltage will be induced to resist the current change. Whent = t1, all of the full-bridge transistors are turned
off, a very high negative voltage is induced across the leakage inductor, and it forces the body diodes of transistorsQ2andQ4
to turn on. The leakage inductor is demagnetized rapidly until
iLkdecreases toiLm(t1), i.e.,
iLm(t1) = iLm(t0) +n(VO+ 2VD)Dr1TS
Lm (3)
where Dr1−4’s denote the duty ratios of States 1–4. While
Fig. 4. Equivalent circuit of the proposed converter in State 3.
body diodes of transistorsQ2 andQ4 until it is fully
demag-netized. The switching current of the leakage inductanceiLkin
State 2 decreases linearly as the same rate of (2).
In this state, whileiLk> iLm, both the currentsiLkandiLm
flow to the transformer in phase. They will induce an output currentiS to load through the rectifiers. SinceLmis reversely
biased,Lm will demagnetize just as shown in (1). WhileiLk
decays to a value, i.e.,iLk < iLm, some of the energy of the
magnetizing inductance Lm will be pumped to the input dc
bus,VIN, through the leakage inductanceLk. After the leakage
inductor is fully demagnetized,iLkdecays to zero, and the body
diodes of transistorsQ2andQ4are turned off. Thus, the energy
stored in the magnetizing inductanceLmof the transformer will
wholly flow to the outputVO through the secondary winding
of the transformer and the rectifier diodes D6 and D8. The
reflected voltage of the primary inductanceVLm is−n(VO+
2VD). The magnetizing inductor Lmdemagnetizes as the same rate of (1). In contrast,VLmwill ben(VO+ 2VD) if T X1= 1,
in which the transistorsQ2andQ4switch the transformer.
In this design, the magnetizing current iLm is in
discon-tinuous conduction mode. The magnetizing inductanceLm is
charged in State 1 and then discharged completely in State 2. The voltage across the magnetizing inductor in States 1 and 2 is
|n(VO+ 2VD)|. Thus, Δtmag= Δtdmag, whereΔtmagis the
magnetizing period ofLm, i.e.,Δtmag= Dr1TS, andΔtdmag
is the demagnetizing period ofLm.
Att = t2, the time wheniLk(t2) decays to zero, the body
diodes of transistorsQ2andQ4will not conduct. The leakage
inductorLkstarts to resonate along with the equivalent parasitic
capacitorsCP. In practice, the resonant amplitude in State 2
decays due to the parasitic resistance along the resonant path. The initial value of VLk is very small in the beginning of
oscillation time. That is why the oscillation amplitude is very small in State 2. The equivalent parasitic capacitorCP across the terminals A and B includes the following: 1) the parasitic capacitors of the transistors, such asCP 1−CP 4; 2) the parasitic
capacitors of the primary winding of the transformer; and 3) the parasitic capacitors between the conduction wires on the printed circuit board.
C. State 3[t3−t5]: Duration of L–L–C Resonance and
Backward Data Transfer
Fig. 4 shows the equivalent circuit of the proposed converter in State 3. In this state, the resonant quality factor (Q
fac-tor) is determined by the ON/OFF state of the transistor Q5.
WhenT X2= 1, transistor Q5 is turned on, and resistor RS
is connected to terminals C and D. The resistor RS changes the impedance across terminals A and B and results in a low quality factor and high oscillation damping (Fig. 3). Conversely,
whenT X2= 0, transistor Q5is off att4; thus, an approximate
infinite Q factor will be obtained, and VAB will have a large
oscillation amplitude that is approximate toVIN. By detecting
the oscillation amplitude of VAB, backward datum can be
retrieved. Moreover, no extra supplied power is required to transfer backward data.
Att = t3, the transistorQ5is off. The magnetizing inductor
Lm is demagnetized completely. The rectifier diodes at the
secondary side of the transformer are off. At this moment, since the energy stored in the parasitic capacitanceCPstarts to transfer to the magnetizing inductanceLmandLk, a resonant cycle is activated by the resonant tankLk−Lm−CP. Thus, the
resonant frequency can be obtained as
ωr1= 1
Cp(Lm+ Lk)
(4)
where the conduction and core losses of the transformer and the turn-on resistance of the MOSFETs are ignored. SinceiLkand
iLm are 0 att3and transistorQ5remains off, the amplitude of
the resonant signalVABin State 3 will be equal to|VAB(t3)|.
AsVINandVOare the assigned values,t3can be estimated or
detected by using a current sensor in the secondary side. For as-suring obtaining complete demagnetization of the transformer, a short time delayΔt is inserted before activating transistor Q5
to send the backward datum. At t = t4= t3+ Δt, transistor
Q5 is turned on/off according to the logic state of transmitted
backward datum T X2 to ensure that the transformer is fully
demagnetized. Furthermore, for ensuring that the amplitude of resonant signal is well modulated, Q5 is better to be turned
on before one-fourth resonant cycle when VCD changed its
polarity.
D. State 4[t5−t6]: Duration of Synchronization
In this state, Q3 and Q4 are both on, and voltages across
the primary and secondary windings of the transformer will remain 0 until time t6 which is the end of a switching cycle
TS. Att = t6,VAB has an abrupt edge at the end of State 4,
and the operation will return to State 1. This abrupt edge is used to generate the synchronization pulse signal(P LS) in the secondary control circuit shown in Fig. 6.
Fig. 5 shows a feasible primary control circuit of the pro-posed power converter. The primary control circuit has five circuit blocks: 1) a clock generator that provides a clock sig-nal CK1 for the primary control circuit; 2) a communication
unit and a serial bus interface for receiving/transferring data from/to the Host side; 3) a state controller that generates signals
S11,12,13, and 14’s to control operation timing of the proposed
converter; 4) a phase-modulation circuit that controls the full-bridge switching phase and transmits the forward datumT X1;
and 5) a threshold-level detector that retrieves the backward datum intoRX2 by detecting the voltage level of the primary
winding voltage|VAB| in State 3.
Fig. 6 shows a feasible secondary control circuit for the proposed power converter. It includes the following five blocks: 1) a communication unit and serial bus interface that re-ceives/transfers data from/to the I/O side; 2) a regulator that
Fig. 5. Primary control circuit.
Fig. 6. Secondary control circuit.
provides a regulated dc voltage to the circuit on the transformer secondary side; 3) a synchronous controller that generates synchronous state signalsS21,22,23, and 24’s to synchronize the
operation timing between the primary and secondary control circuits; 4) an impedance modulator that transfers the backward datumT X2; and 5) a phase detector that retrieves the forward
datum intoRX1by detecting the voltage of terminal D on the
transformer secondary winding in State 1. WhenVD exceeds
the reference voltageVREF, thenRX1 is set to 1; otherwise,
RX1is set to 0.
Proper timing control is important to successfully retrieve the forward data sent from the primary control circuit. Fig. 7 shows the waveforms produced by the timing recovery circuit in the secondary control circuit. The timing recovery circuit in Fig. 6 is utilized to generate the synchronous state signalsS21−24’s
at the secondary side of the transformer to emulate the timing signalsS11−14’s. When State 4 ends, a new switching cycle
will start, and the voltageVAB across the primary winding of
the transformer will have an abrupt edge. This abrupt edge is used for the synchronization at the transformer secondary side.
Fig. 7. Associated waveforms of the synchronous controller.
It causes an edge change toVCD. Through detecting this edge
change, the synchronization pulse signalP LS is generated by
a cycle detector in the secondary control circuit. This pulse signal P LS is used for performing the synchronization. By
sensing the positive and negative edges of theP LS, the timing
recovery circuit will generate a sample-and-hold(SH) signal and an end-of-cycle(EOC) signal. Conventionally, the timing recovery circuit can be implemented by using a constant current to charge a capacitor C1. The EOC signal is coupled to
discharge the capacitorC1, therefore initiating a new switching
cycle as shown in Fig. 7.
The duty ratios of the four operational statesDr1,2,3, and 4’s,
as shown in Fig. 7, are designed as constants by a voltage divider connected to a signalVC2. SignalVC2is the maximum
value of VC1, the voltage across the capacitor C1, sampled
by SH. The signal VC2 is sampled before the signal VC1 is
discharged. The duty ratios can be regenerated at the secondary side of the transformer, which is based on the relationship
R1: R2: R3: R4= Dr1: Dr2: Dr3: Dr4. Therefore,
syn-chronous state signalsS21,22,23, and 24’s of the secondary
con-trol circuit can be easily produced by comparingVC1andVC2.
III. DESIGNCONSIDERATIONS
The component parameters of the equivalent circuit in Fig. 4, namely, Lk, Lm, CP, and R, must be selected carefully to
maximize the performance and ensure a reliable backward data transfer. Once the equivalent parasitic capacitorCPand leakage inductance of transformer Lk are measured, the magnetizing inductanceLmand resistance of the impedance modulatorRS
can be derived.
The two cases of the proposed converter operated in State 3 (Fig. 4), according to the logic state of transmitted backward datumT X2, are discussed as follows.
A. Case 1 (Q5OFF)
TheQ factor of a resonant circuit is defined as the ratio of
equivalent to
Q = ωr
maximum energy stored average power dissipated
. (5) In Case 1, when the transmitted backward dataT X2= 0, Q5
is turned off.CP,Lk, andLmform as anL − L − C resonant
tank with resonant frequencyωr1= 1/(2π√(Cp(Lm+ Lk))).
As no resistive element exists in the resonant circuit, the Q
factor in Case 1 is infinite. Restated, the amplitude of resonant signalVABwill not decay during the switching cycle period. To
ensure that the backward data can be correctly retrieved by the threshold-level detector of the primary control circuit, at least one-half resonant cycle should exist in the duration of State 3. Accordingly, minimum magnetizing inductance Lm can be
obtained from
Dr3TS > π
Cp(Lm+ Lk). (6)
B. Case 2 (Q5ON)
In Case 2, when the transmitted backward dataT X2= 1,
Q5 is turned on. Resistance R is paralleled to magnetizing
inductance Lm, where R = n2R
S. Thus, the resonant fre-quency and theQ factor of the resonant circuit change. Since
the imaginary part of resonant circuit impedance Im(ZAB) is
zero at resonance, the resonant frequency in Case 2 can be obtained by ωr2= −m +√m2− 4n 2 (7) where m = CpR 2(L m+ Lk)2− L2mLk CpL2mL2k n = − R2(L m+ Lk) CpL2mL2k .
As a result, the quality factor of the resonant circuit in Case 2,
QCASE2, can be obtained from (5) and (7), given as
QCASE2 = ωr2CpRe(ZAB) = ω3r2L2mRCp [ω2 r2CpR(Lm+ Lk)−R]2+ ωr22 L2m(ωr22 CpLk− 1)2. (8) There are three possible resonant models in Case 2 according toR value: 1) L–L–C model, in case R approximates to ∞;
2)L–C model, in case R approximates to 0; and 3) L–L–C–R
model. As shown in (8), QCASE2 will be∞ when resistance
R is ∞. This result is the same as that in Case 1 since the
resonant circuit is the same. Moreover, when settingR value as
0, the resonant tank contains onlyCPandLk, andQCASE2will
Fig. 8 (a)R versus ωr2. (b)R versus quality factor.
be ∞. Thus, QCASE2 has a valley point (QCASE2,opt, Ropt)
in response to the change of resistanceR, which is shown in
Fig. 8(b).
To choose an appropriate resistance R value is important
for a reliable backward data transfer. When R is connected
across the secondary winding of the transformer in State 3, the resonant voltage has a decay function e−ωt, where α = ωr/(2Q). When the resonant circuit is operated at a critical
damped condition such thatQ = 0.5, then e−αtwill be as small as 0.04 at timet = π/ωr. Therefore, for the design satisfying
QCASE2< 0.5, the overdamped condition will ensure that the
backward data can be retrieved correctly by the threshold-level detector in the primary control circuit. Similarly,Q < 0.5 will
generate a good data retrieval capability in Case 2.
An example is given hereinafter. Assume thatCP = 150 pF,
Lk= 0.25 uH, and Lm= 16 uH. The curves of ωr2(R) and
QCASE2(R) with respect to resistance R can be obtained from
(7) and (8) and are shown in Fig. 8(a) and (b). It results in a minimum resistance (Rmin= 38 Ω) and a maximum
resistance (Rmax= 153 Ω) to satisfy QCASE2= 0.5. An
ap-propriate value of R is acquired to provide a reliable
back-ward data transfer. For the design optimization, a minimal Q
value,QCASE2,opt, is helpful for resonant signalVABdecaying
rapidly. The correspondingR value is Ropt = 56 Ω.
Another reliable backward data transfer can also be achieved when the resonant circuit in Case 2 meets the following approximations: 1) If XLk |R//jXLm|, then the resonant
circuit in Case 2 can be approximated to a second-order parallelR−Lm−CP resonant circuit with quality factorQP =
(√(CP/Lm)) ∗ R, or 2) if XLm R, then the resonant
cir-cuit in Case 2 can be approximated to a second-order se-ries R−Lk−CP resonant circuit with quality factor QS =
(√(Lk/CP))/R. This approximation provides a convenient
consideration by choosing anR value that is close to QP < 0.5
orQS < 0.5. Fig. 8(b) shows the curves for the three types of
quality factors with respect to resistanceR.
IV. EXPERIMENTALRESULTS
An experimental prototype has been built to verify the opera-tion principles of the proposed design. The specificaopera-tions of the prototype are as follows.
1) VIN: 12 V.
2) IO: 0–90 mA.
3) VO: 10 V (full load) to 12 V (no load).
4) fS: 1 MHz.
5) Dr1: Dr2: Dr3: Dr4= 9 : 9 : 9 : 5.
The power conversion stage shown in Fig. 2 consists of the following components.
1) Q1, Q2, Q3, Q4, Q5: VN0606 N-channel MOSFETs.
2) High- and low-side drivers for the full-bridge: IR2110. 3) D5, D6, D7, D8, D9, D10: SB160 diodes.
4) CO: 1-μF ceramic capacitor.
5) Transformer: n = NP/NS = 1, Lm= 15.9 μH, Lk =
0.25 μH, MPP Core, the outer diameter is 13 mm, and the thickness is 5 mm.
First, we choose Lm= 15.9 uH. The measurement shows
that the resonant period ofVABis 312 ns in State 3. Therefore,
the equivalent parasitic capacitor of the switches across the terminals A and B can be estimated as CP = 152.68 pF,
and the resonant frequency satisfies the requirement given by (6). Finally, by findingQCASE2,opt= 0.25, the resistance of
the impedance modulatorRS = R/n2= 56 Ω was chosen to
achieve an optimized backward data transfer.
Since the transformer is operated at Discontinuous Conduc-tion Mode (DCM), there is no magnetic saturaConduc-tion concern for the transformer. The average output voltageVOis 10.18 V at the full-load output current of 91.9 mA, and the maximum output voltage is 12 V at no-load condition. The efficiency η of the
proposed converter not including the control circuit is 83% at full load in the conditionsT X1= 0 and T X2= 0 during 5-min
operation (Q5 is always turned off). The efficiencyη is 82%
at full load for the conditionsT X1= 0 and T X2= 1 (Q5 is
always turned on). As a result, it shows that the backward data transfer is a low-power-consumption approach.
Fig. 9 shows the experimental results of the proposed con-verter in four possible data-transmission cases. Fig. 9 also shows the gate signals of transistors Q1, Q5 and the voltage
across the transformer primary winding (VAB). For forward
data transmission, the voltage phase ofVAB presents the
for-ward datum T X1 transmitted in State 1. For backward data
transmission, the amplitudes of the resonant signal as men-tioned in State 3 have also been successfully modulated by the backward datum T X2 and can be clearly identified by a
Fig. 9. Experimental waveforms for the proposed design.
threshold level as expected. Finally, all the waveforms have well matched the theoretical ones.
V. CONCLUSION
The isolated full-bridge dc/dc converter with bidirectional communication capability has been presented with illustrations of its operations and analyses. A novel backward data transfer circuit, which is achieved by manipulating the amplitude of the resonant signal, is presented. An efficient approach for finding an appropriate range of modulation resistance to achieve reliable backward data communication is also presented. The experimental results have demonstrated that the proposed con-verter provides isolated power conversion and bidirectional communication via the same switching cycle. In conclusion, the proposed power converter provides high isolation capability by using an isolated transformer and has a small device footprint.
REFERENCES
[1] W. C. D’Angelo and J. F. Latu, “Digital isolation barrier as interface bus for modems,” U.S. Patent 7 330 544, Feb. 12, 2008.
[2] D. Liu, “Electrical isolation techniques for DSL modem,” U.S. Patent 7 269 210, Sep. 11, 2007.
[3] E. R. Worley, “Design of telephone line interface circuits using a two chip opto-coupler with LEDs integrated onto silicon chips,” U.S. Patent no. 6 757 381, Jun. 29, 2004.
[4] B. A. Smith, K. Tang, V. Levi, and J. Owens, “High voltage isolation by capacitive coupling,” U.S. Patent 7 675 444, Mar. 9, 2010.
[5] D. J. Haupert, C. R. Levan, T. J. Winkler, and J. M. Kruse, “Interface devices for instruments in communication with implantable medical de-vices,” U.S. Patent 6 580 948, Jun. 17, 2003.
[6] J. G. Calvin, “Control system methods and apparatus for inductive communication across an isolation barrier,” U.S. Patent 7 684 475, Mar. 23, 2010.
[7] T. J. Dupuis, G. T. Tuttle, J. W. Scott, N. S. Sooch, and D. R. Welland, “Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting,” U.S. Patent 7 515 672, Apr. 7, 2009.
[8] R. Hershbarger and K. Fukahori, “Method and apparatus for synchroniza-tion of data in a transformer circuit,” U.S. Patent 7 408 996, Aug. 5, 2008.
[9] X. Jin, W. Wu, X. Sun, and J. Liu, “Resonant tank and transformer design in series resonant converter,” in Conf. Rec. IEEE IAS Annu. Meeting, 2005, pp. 1475–1482.
[10] L. H. S. C. Barreto, E. A. A. Coelho, V. J. Farias, J. C. de Oliveira, L. C. de Freitas, and J. B. Vieira, Jr., “A quasi-resonant quadratic boost converter using a single resonant network,” IEEE Trans. Ind. Electron., vol. 52, no. 2, pp. 552–557, Apr. 2005.
[11] A. Bucher, T. Durbaum, D. Kubrich, and A. Stadler, “Comparison of different design methods for the parallel resonant converter,” in Proc.
EPE-PEMC, 2006, pp. 810–815.
[12] S. Zheng and D. Czarkowski, “Modeling and digital control of a phase-controlled series-parallel resonant converter,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 707–715, Apr. 2007.
[13] C. Adragna, S. De Simone, and C. Spini, “A design methodology for LLC resonant converters based on inspection of resonant tank currents,” in Proc. IEEE APEC, 2008, pp. 1361–1367.
[14] H. Sheng, Y. Pei, and F. Wang, “Impact of resonant tank structures on transformer size for a high power density isolated resonant converter,” in
Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 2975–2981.
[15] J. Biela, U. Badstuebner, and J. W. Kolar, “Impact of power density maximization on efficiency of dc–dc converter systems,” IEEE Trans.
Power Electron., vol. 24, no. 1, pp. 288–300, Jan. 2009.
[16] C. S. Tang, Y. Sun, Y. G. Su, S. K. Nguang, and A. P. Hu, “Determining multiple steady-state ZCS operating points of a switch-mode contactless power transfer system,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 416–425, Feb. 2009.
[17] J. L. Sosa, M. Castilla, J. Miret, L. Garcia de Vicuna, and J. Matas, “Modeling and performance analysis of the dc/dc series–parallel resonant converter operating with discrete self-sustained phase-shift modulation technique,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 697–705, Mar. 2009.
[18] J. M. Kwon, W. Y. Choi, and B. H. Kwon, “Single-switch quasi-resonant converter,” IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 1158–1163, Apr. 2009.
[19] M. Borage, K. V. Nagesh, M. S. Bhatia, and S. Tiwari, “Design of LCL-T resonant converter including the effect of transformer winding capacitance,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1420–1427, May 2009.
[20] E. H. Kim and B. H. Kwon, “Zero-voltage and zero-current switching full-bridge converter with secondary resonance,” IEEE Trans. Ind. Electron., vol. 57, no. 3, pp. 1017–1025, Mar. 2010.
[21] R. Casanueva, C. Brañas, F. J. Azcondo, and F. J. Díaz, “Teaching resonant converters: Properties and applications for variable loads,” IEEE Trans.
Ind. Electron., vol. 57, no. 10, pp. 3355–3363, Oct. 2010.
Ru-Shiuan Yang (S’07) was born in Taoyuan,
Taiwan, in 1981. She received the Associate’s de-gree in electronic engineering from the National Taipei Institute of Technology, Taipei, Taiwan, in 2001 and the B.S. degree in electronic engineering from the National Yunlin University of Science and Technology, Yunlin, Taiwan, in 2003. She is cur-rently working toward the Ph.D. degree in the Insti-tute of Electrical and Control Engineering, National Chiao-Tung University, Hsinchu, Taiwan.
Her research interests include energy conversion, power management, and industrial electronics application.
Lon-Kou Chang received the B.S. degree in
elec-tronic engineering from Chung Yuan Christian Uni-versity, Chung-Li, Taiwan, in 1975, the M.S. de-gree in electronic engineering from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1977, and the Ph.D. degree in electrical engineer-ing from the University of Maryland, College Park, in 1995.
In 1983, he was with the Department of Control Engineering, NCTU. In 2008, he retired from the NCTU as an Associate Professor. He is currently with Macroblock, Inc., as a Consultant in power IC design.
Hung-Chi Chen (M’06) was born in Taichung,
Taiwan, in June 1974. He received the B.S. and Ph.D. degrees from the Department of Electrical En-gineering, National Tsing-Hua University, Hsinchu, Taiwan, in 1996 and 2001, respectively.
In October 2001, he was a Researcher with the En-ergy and Resources Laboratory, Industrial Technol-ogy Research Institute, Hsinchu. Since August 2006, he has been with the Department of Electrical Engi-neering, National Chiao-Tung University, Hsinchu, where he is currently an Associate Professor. His research interests include power electronics, power factor correction, motor and inverter-fed control, and DSP/MCU/FPGA-based implementation of digital control.
